tlb.hh revision 2090
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ALPHA_MEMORY_HH__ 30#define __ALPHA_MEMORY_HH__ 31 32#include <map> 33 34#include "arch/alpha/isa_traits.hh" 35#include "arch/alpha/faults.hh" 36#include "base/statistics.hh" 37#include "mem/mem_req.hh" 38#include "sim/sim_object.hh" 39 40class ExecContext; 41 42class AlphaTLB : public SimObject 43{ 44 protected: 45 typedef std::multimap<Addr, int> PageTable; 46 PageTable lookupTable; // Quick lookup into page table 47 48 AlphaISA::PTE *table; // the Page Table 49 int size; // TLB Size 50 int nlu; // not last used entry (for replacement) 51 52 void nextnlu() { if (++nlu >= size) nlu = 0; } 53 AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const; 54 55 public: 56 AlphaTLB(const std::string &name, int size); 57 virtual ~AlphaTLB(); 58 59 int getsize() const { return size; } 60 61 AlphaISA::PTE &index(bool advance = true); 62 void insert(Addr vaddr, AlphaISA::PTE &pte); 63 64 void flushAll(); 65 void flushProcesses(); 66 void flushAddr(Addr addr, uint8_t asn); 67 68 // static helper functions... really EV5 VM traits 69 static bool validVirtualAddress(Addr vaddr) { 70 // unimplemented bits must be all 0 or all 1 71 Addr unimplBits = vaddr & EV5::VAddrUnImplMask; 72 return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); 73 } 74 75 static void checkCacheability(MemReqPtr &req); 76 77 // Checkpointing 78 virtual void serialize(std::ostream &os); 79 virtual void unserialize(Checkpoint *cp, const std::string §ion); 80}; 81 82class AlphaITB : public AlphaTLB 83{ 84 protected: 85 mutable Stats::Scalar<> hits; 86 mutable Stats::Scalar<> misses; 87 mutable Stats::Scalar<> acv; 88 mutable Stats::Formula accesses; 89 90 protected: 91 void fault(Addr pc, ExecContext *xc) const; 92 93 public: 94 AlphaITB(const std::string &name, int size); 95 virtual void regStats(); 96 97 Fault * translate(MemReqPtr &req) const; 98}; 99 100class AlphaDTB : public AlphaTLB 101{ 102 protected: 103 mutable Stats::Scalar<> read_hits; 104 mutable Stats::Scalar<> read_misses; 105 mutable Stats::Scalar<> read_acv; 106 mutable Stats::Scalar<> read_accesses; 107 mutable Stats::Scalar<> write_hits; 108 mutable Stats::Scalar<> write_misses; 109 mutable Stats::Scalar<> write_acv; 110 mutable Stats::Scalar<> write_accesses; 111 Stats::Formula hits; 112 Stats::Formula misses; 113 Stats::Formula acv; 114 Stats::Formula accesses; 115 116 protected: 117 void fault(MemReqPtr &req, uint64_t flags) const; 118 119 public: 120 AlphaDTB(const std::string &name, int size); 121 virtual void regStats(); 122 123 Fault * translate(MemReqPtr &req, bool write) const; 124}; 125 126#endif // __ALPHA_MEMORY_HH__ 127