tlb.hh revision 1762 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ALPHA_MEMORY_HH__
30#define __ALPHA_MEMORY_HH__
31
32#include <map>
33
34#include "arch/alpha/isa_traits.hh"
35#include "base/statistics.hh"
36#include "mem/mem_req.hh"
37#include "sim/sim_object.hh"
38
39class ExecContext;
40
41class AlphaTLB : public SimObject
42{
43  protected:
44    typedef std::multimap<Addr, int> PageTable;
45    PageTable lookupTable;	// Quick lookup into page table
46
47    AlphaISA::PTE *table;	// the Page Table
48    int size;			// TLB Size
49    int nlu;			// not last used entry (for replacement)
50
51    void nextnlu() { if (++nlu >= size) nlu = 0; }
52    AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
53
54  public:
55    AlphaTLB(const std::string &name, int size);
56    virtual ~AlphaTLB();
57
58    int getsize() const { return size; }
59
60    AlphaISA::PTE &index(bool advance = true);
61    void insert(Addr vaddr, AlphaISA::PTE &pte);
62
63    void flushAll();
64    void flushProcesses();
65    void flushAddr(Addr addr, uint8_t asn);
66
67    // static helper functions... really EV5 VM traits
68    static bool validVirtualAddress(Addr vaddr) {
69        // unimplemented bits must be all 0 or all 1
70        Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
71        return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
72    }
73
74    static void checkCacheability(MemReqPtr &req);
75
76    // Checkpointing
77    virtual void serialize(std::ostream &os);
78    virtual void unserialize(Checkpoint *cp, const std::string &section);
79};
80
81class AlphaITB : public AlphaTLB
82{
83  protected:
84    mutable Stats::Scalar<> hits;
85    mutable Stats::Scalar<> misses;
86    mutable Stats::Scalar<> acv;
87    mutable Stats::Formula accesses;
88
89  protected:
90    void fault(Addr pc, ExecContext *xc) const;
91
92  public:
93    AlphaITB(const std::string &name, int size);
94    virtual void regStats();
95
96    Fault translate(MemReqPtr &req) const;
97};
98
99class AlphaDTB : public AlphaTLB
100{
101  protected:
102    mutable Stats::Scalar<> read_hits;
103    mutable Stats::Scalar<> read_misses;
104    mutable Stats::Scalar<> read_acv;
105    mutable Stats::Scalar<> read_accesses;
106    mutable Stats::Scalar<> write_hits;
107    mutable Stats::Scalar<> write_misses;
108    mutable Stats::Scalar<> write_acv;
109    mutable Stats::Scalar<> write_accesses;
110    Stats::Formula hits;
111    Stats::Formula misses;
112    Stats::Formula acv;
113    Stats::Formula accesses;
114
115  protected:
116    void fault(MemReqPtr &req, uint64_t flags) const;
117
118  public:
119    AlphaDTB(const std::string &name, int size);
120    virtual void regStats();
121
122    Fault translate(MemReqPtr &req, bool write) const;
123};
124
125#endif // __ALPHA_MEMORY_HH__
126