tlb.cc revision 2132
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sstream> 30#include <string> 31#include <vector> 32 33#include "arch/alpha/alpha_memory.hh" 34#include "base/inifile.hh" 35#include "base/str.hh" 36#include "base/trace.hh" 37#include "config/alpha_tlaser.hh" 38#include "cpu/exec_context.hh" 39#include "sim/builder.hh" 40 41using namespace std; 42using namespace EV5; 43 44/////////////////////////////////////////////////////////////////////// 45// 46// Alpha TLB 47// 48#ifdef DEBUG 49bool uncacheBit39 = false; 50bool uncacheBit40 = false; 51#endif 52 53#define MODE2MASK(X) (1 << (X)) 54 55AlphaTLB::AlphaTLB(const string &name, int s) 56 : SimObject(name), size(s), nlu(0) 57{ 58 table = new AlphaISA::PTE[size]; 59 memset(table, 0, sizeof(AlphaISA::PTE[size])); 60} 61 62AlphaTLB::~AlphaTLB() 63{ 64 if (table) 65 delete [] table; 66} 67 68// look up an entry in the TLB 69AlphaISA::PTE * 70AlphaTLB::lookup(Addr vpn, uint8_t asn) const 71{ 72 // assume not found... 73 AlphaISA::PTE *retval = NULL; 74 75 PageTable::const_iterator i = lookupTable.find(vpn); 76 if (i != lookupTable.end()) { 77 while (i->first == vpn) { 78 int index = i->second; 79 AlphaISA::PTE *pte = &table[index]; 80 assert(pte->valid); 81 if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { 82 retval = pte; 83 break; 84 } 85 86 ++i; 87 } 88 } 89 90 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 91 retval ? "hit" : "miss", retval ? retval->ppn : 0); 92 return retval; 93} 94 95 96void 97AlphaTLB::checkCacheability(MemReqPtr &req) 98{ 99 // in Alpha, cacheability is controlled by upper-level bits of the 100 // physical address 101 102 /* 103 * We support having the uncacheable bit in either bit 39 or bit 40. 104 * The Turbolaser platform (and EV5) support having the bit in 39, but 105 * Tsunami (which Linux assumes uses an EV6) generates accesses with 106 * the bit in 40. So we must check for both, but we have debug flags 107 * to catch a weird case where both are used, which shouldn't happen. 108 */ 109 110 111#if ALPHA_TLASER 112 if (req->paddr & PAddrUncachedBit39) { 113#else 114 if (req->paddr & PAddrUncachedBit43) { 115#endif 116 // IPR memory space not implemented 117 if (PAddrIprSpace(req->paddr)) { 118 if (!req->xc->misspeculating()) { 119 switch (req->paddr) { 120 case ULL(0xFFFFF00188): 121 req->data = 0; 122 break; 123 124 default: 125 panic("IPR memory space not implemented! PA=%x\n", 126 req->paddr); 127 } 128 } 129 } else { 130 // mark request as uncacheable 131 req->flags |= UNCACHEABLE; 132 133#if !ALPHA_TLASER 134 // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 135 req->paddr &= PAddrUncachedMask; 136#endif 137 } 138 } 139} 140 141 142// insert a new TLB entry 143void 144AlphaTLB::insert(Addr addr, AlphaISA::PTE &pte) 145{ 146 AlphaISA::VAddr vaddr = addr; 147 if (table[nlu].valid) { 148 Addr oldvpn = table[nlu].tag; 149 PageTable::iterator i = lookupTable.find(oldvpn); 150 151 if (i == lookupTable.end()) 152 panic("TLB entry not found in lookupTable"); 153 154 int index; 155 while ((index = i->second) != nlu) { 156 if (table[index].tag != oldvpn) 157 panic("TLB entry not found in lookupTable"); 158 159 ++i; 160 } 161 162 DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 163 164 lookupTable.erase(i); 165 } 166 167 DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); 168 169 table[nlu] = pte; 170 table[nlu].tag = vaddr.vpn(); 171 table[nlu].valid = true; 172 173 lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 174 nextnlu(); 175} 176 177void 178AlphaTLB::flushAll() 179{ 180 DPRINTF(TLB, "flushAll\n"); 181 memset(table, 0, sizeof(AlphaISA::PTE[size])); 182 lookupTable.clear(); 183 nlu = 0; 184} 185 186void 187AlphaTLB::flushProcesses() 188{ 189 PageTable::iterator i = lookupTable.begin(); 190 PageTable::iterator end = lookupTable.end(); 191 while (i != end) { 192 int index = i->second; 193 AlphaISA::PTE *pte = &table[index]; 194 assert(pte->valid); 195 196 // we can't increment i after we erase it, so save a copy and 197 // increment it to get the next entry now 198 PageTable::iterator cur = i; 199 ++i; 200 201 if (!pte->asma) { 202 DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); 203 pte->valid = false; 204 lookupTable.erase(cur); 205 } 206 } 207} 208 209void 210AlphaTLB::flushAddr(Addr addr, uint8_t asn) 211{ 212 AlphaISA::VAddr vaddr = addr; 213 214 PageTable::iterator i = lookupTable.find(vaddr.vpn()); 215 if (i == lookupTable.end()) 216 return; 217 218 while (i->first == vaddr.vpn()) { 219 int index = i->second; 220 AlphaISA::PTE *pte = &table[index]; 221 assert(pte->valid); 222 223 if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { 224 DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 225 pte->ppn); 226 227 // invalidate this entry 228 pte->valid = false; 229 230 lookupTable.erase(i); 231 } 232 233 ++i; 234 } 235} 236 237 238void 239AlphaTLB::serialize(ostream &os) 240{ 241 SERIALIZE_SCALAR(size); 242 SERIALIZE_SCALAR(nlu); 243 244 for (int i = 0; i < size; i++) { 245 nameOut(os, csprintf("%s.PTE%d", name(), i)); 246 table[i].serialize(os); 247 } 248} 249 250void 251AlphaTLB::unserialize(Checkpoint *cp, const string §ion) 252{ 253 UNSERIALIZE_SCALAR(size); 254 UNSERIALIZE_SCALAR(nlu); 255 256 for (int i = 0; i < size; i++) { 257 table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 258 if (table[i].valid) { 259 lookupTable.insert(make_pair(table[i].tag, i)); 260 } 261 } 262} 263 264 265/////////////////////////////////////////////////////////////////////// 266// 267// Alpha ITB 268// 269AlphaITB::AlphaITB(const std::string &name, int size) 270 : AlphaTLB(name, size) 271{} 272 273 274void 275AlphaITB::regStats() 276{ 277 hits 278 .name(name() + ".hits") 279 .desc("ITB hits"); 280 misses 281 .name(name() + ".misses") 282 .desc("ITB misses"); 283 acv 284 .name(name() + ".acv") 285 .desc("ITB acv"); 286 accesses 287 .name(name() + ".accesses") 288 .desc("ITB accesses"); 289 290 accesses = hits + misses; 291} 292 293void 294AlphaITB::fault(Addr pc, ExecContext *xc) const 295{ 296 uint64_t *ipr = xc->regs.ipr; 297 298 if (!xc->misspeculating()) { 299 ipr[AlphaISA::IPR_ITB_TAG] = pc; 300 ipr[AlphaISA::IPR_IFAULT_VA_FORM] = 301 ipr[AlphaISA::IPR_IVPTBR] | (AlphaISA::VAddr(pc).vpn() << 3); 302 } 303} 304 305 306Fault 307AlphaITB::translate(MemReqPtr &req) const 308{ 309 InternalProcReg *ipr = req->xc->regs.ipr; 310 311 if (AlphaISA::PcPAL(req->vaddr)) { 312 // strip off PAL PC marker (lsb is 1) 313 req->paddr = (req->vaddr & ~3) & PAddrImplMask; 314 hits++; 315 return NoFault; 316 } 317 318 if (req->flags & PHYSICAL) { 319 req->paddr = req->vaddr; 320 } else { 321 // verify that this is a good virtual address 322 if (!validVirtualAddress(req->vaddr)) { 323 fault(req->vaddr, req->xc); 324 acv++; 325 return ItbAcvFault; 326 } 327 328 329 // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 330 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 331#if ALPHA_TLASER 332 if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && 333 VAddrSpaceEV5(req->vaddr) == 2) { 334#else 335 if (VAddrSpaceEV6(req->vaddr) == 0x7e) { 336#endif 337 // only valid in kernel mode 338 if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != 339 AlphaISA::mode_kernel) { 340 fault(req->vaddr, req->xc); 341 acv++; 342 return ItbAcvFault; 343 } 344 345 req->paddr = req->vaddr & PAddrImplMask; 346 347#if !ALPHA_TLASER 348 // sign extend the physical address properly 349 if (req->paddr & PAddrUncachedBit40) 350 req->paddr |= ULL(0xf0000000000); 351 else 352 req->paddr &= ULL(0xffffffffff); 353#endif 354 355 } else { 356 // not a physical address: need to look up pte 357 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), 358 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 359 360 if (!pte) { 361 fault(req->vaddr, req->xc); 362 misses++; 363 return ItbPageFault; 364 } 365 366 req->paddr = (pte->ppn << AlphaISA::PageShift) + 367 (AlphaISA::VAddr(req->vaddr).offset() & ~3); 368 369 // check permissions for this access 370 if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) { 371 // instruction access fault 372 fault(req->vaddr, req->xc); 373 acv++; 374 return ItbAcvFault; 375 } 376 377 hits++; 378 } 379 } 380 381 // check that the physical address is ok (catch bad physical addresses) 382 if (req->paddr & ~PAddrImplMask) 383 return MachineCheckFault; 384 385 checkCacheability(req); 386 387 return NoFault; 388} 389 390/////////////////////////////////////////////////////////////////////// 391// 392// Alpha DTB 393// 394AlphaDTB::AlphaDTB(const std::string &name, int size) 395 : AlphaTLB(name, size) 396{} 397 398void 399AlphaDTB::regStats() 400{ 401 read_hits 402 .name(name() + ".read_hits") 403 .desc("DTB read hits") 404 ; 405 406 read_misses 407 .name(name() + ".read_misses") 408 .desc("DTB read misses") 409 ; 410 411 read_acv 412 .name(name() + ".read_acv") 413 .desc("DTB read access violations") 414 ; 415 416 read_accesses 417 .name(name() + ".read_accesses") 418 .desc("DTB read accesses") 419 ; 420 421 write_hits 422 .name(name() + ".write_hits") 423 .desc("DTB write hits") 424 ; 425 426 write_misses 427 .name(name() + ".write_misses") 428 .desc("DTB write misses") 429 ; 430 431 write_acv 432 .name(name() + ".write_acv") 433 .desc("DTB write access violations") 434 ; 435 436 write_accesses 437 .name(name() + ".write_accesses") 438 .desc("DTB write accesses") 439 ; 440 441 hits 442 .name(name() + ".hits") 443 .desc("DTB hits") 444 ; 445 446 misses 447 .name(name() + ".misses") 448 .desc("DTB misses") 449 ; 450 451 acv 452 .name(name() + ".acv") 453 .desc("DTB access violations") 454 ; 455 456 accesses 457 .name(name() + ".accesses") 458 .desc("DTB accesses") 459 ; 460 461 hits = read_hits + write_hits; 462 misses = read_misses + write_misses; 463 acv = read_acv + write_acv; 464 accesses = read_accesses + write_accesses; 465} 466 467void 468AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const 469{ 470 ExecContext *xc = req->xc; 471 AlphaISA::VAddr vaddr = req->vaddr; 472 uint64_t *ipr = xc->regs.ipr; 473 474 // Set fault address and flags. Even though we're modeling an 475 // EV5, we use the EV6 technique of not latching fault registers 476 // on VPTE loads (instead of locking the registers until IPR_VA is 477 // read, like the EV5). The EV6 approach is cleaner and seems to 478 // work with EV5 PAL code, but not the other way around. 479 if (!xc->misspeculating() 480 && !(req->flags & VPTE) && !(req->flags & NO_FAULT)) { 481 // set VA register with faulting address 482 ipr[AlphaISA::IPR_VA] = req->vaddr; 483 484 // set MM_STAT register flags 485 ipr[AlphaISA::IPR_MM_STAT] = 486 (((Opcode(xc->getInst()) & 0x3f) << 11) 487 | ((Ra(xc->getInst()) & 0x1f) << 6) 488 | (flags & 0x3f)); 489 490 // set VA_FORM register with faulting formatted address 491 ipr[AlphaISA::IPR_VA_FORM] = 492 ipr[AlphaISA::IPR_MVPTBR] | (vaddr.vpn() << 3); 493 } 494} 495 496Fault 497AlphaDTB::translate(MemReqPtr &req, bool write) const 498{ 499 RegFile *regs = &req->xc->regs; 500 Addr pc = regs->pc; 501 InternalProcReg *ipr = regs->ipr; 502 503 AlphaISA::mode_type mode = 504 (AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]); 505 506 507 /** 508 * Check for alignment faults 509 */ 510 if (req->vaddr & (req->size - 1)) { 511 fault(req, write ? MM_STAT_WR_MASK : 0); 512 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr, 513 req->size); 514 return AlignmentFault; 515 } 516 517 if (pc & 0x1) { 518 mode = (req->flags & ALTMODE) ? 519 (AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE]) 520 : AlphaISA::mode_kernel; 521 } 522 523 if (req->flags & PHYSICAL) { 524 req->paddr = req->vaddr; 525 } else { 526 // verify that this is a good virtual address 527 if (!validVirtualAddress(req->vaddr)) { 528 fault(req, (write ? MM_STAT_WR_MASK : 0) | 529 MM_STAT_BAD_VA_MASK | 530 MM_STAT_ACV_MASK); 531 532 if (write) { write_acv++; } else { read_acv++; } 533 return DtbPageFault; 534 } 535 536 // Check for "superpage" mapping 537#if ALPHA_TLASER 538 if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && 539 VAddrSpaceEV5(req->vaddr) == 2) { 540#else 541 if (VAddrSpaceEV6(req->vaddr) == 0x7e) { 542#endif 543 544 // only valid in kernel mode 545 if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) != 546 AlphaISA::mode_kernel) { 547 fault(req, ((write ? MM_STAT_WR_MASK : 0) | 548 MM_STAT_ACV_MASK)); 549 if (write) { write_acv++; } else { read_acv++; } 550 return DtbAcvFault; 551 } 552 553 req->paddr = req->vaddr & PAddrImplMask; 554 555#if !ALPHA_TLASER 556 // sign extend the physical address properly 557 if (req->paddr & PAddrUncachedBit40) 558 req->paddr |= ULL(0xf0000000000); 559 else 560 req->paddr &= ULL(0xffffffffff); 561#endif 562 563 } else { 564 if (write) 565 write_accesses++; 566 else 567 read_accesses++; 568 569 // not a physical address: need to look up pte 570 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), 571 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 572 573 if (!pte) { 574 // page fault 575 fault(req, (write ? MM_STAT_WR_MASK : 0) | 576 MM_STAT_DTB_MISS_MASK); 577 if (write) { write_misses++; } else { read_misses++; } 578 return (req->flags & VPTE) ? (Fault)PDtbMissFault : (Fault)NDtbMissFault; 579 } 580 581 req->paddr = (pte->ppn << AlphaISA::PageShift) + 582 AlphaISA::VAddr(req->vaddr).offset(); 583 584 if (write) { 585 if (!(pte->xwe & MODE2MASK(mode))) { 586 // declare the instruction access fault 587 fault(req, MM_STAT_WR_MASK | 588 MM_STAT_ACV_MASK | 589 (pte->fonw ? MM_STAT_FONW_MASK : 0)); 590 write_acv++; 591 return DtbPageFault; 592 } 593 if (pte->fonw) { 594 fault(req, MM_STAT_WR_MASK | 595 MM_STAT_FONW_MASK); 596 write_acv++; 597 return DtbPageFault; 598 } 599 } else { 600 if (!(pte->xre & MODE2MASK(mode))) { 601 fault(req, MM_STAT_ACV_MASK | 602 (pte->fonr ? MM_STAT_FONR_MASK : 0)); 603 read_acv++; 604 return DtbAcvFault; 605 } 606 if (pte->fonr) { 607 fault(req, MM_STAT_FONR_MASK); 608 read_acv++; 609 return DtbPageFault; 610 } 611 } 612 } 613 614 if (write) 615 write_hits++; 616 else 617 read_hits++; 618 } 619 620 // check that the physical address is ok (catch bad physical addresses) 621 if (req->paddr & ~PAddrImplMask) 622 return MachineCheckFault; 623 624 checkCacheability(req); 625 626 return NoFault; 627} 628 629AlphaISA::PTE & 630AlphaTLB::index(bool advance) 631{ 632 AlphaISA::PTE *pte = &table[nlu]; 633 634 if (advance) 635 nextnlu(); 636 637 return *pte; 638} 639 640DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB) 641 642BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) 643 644 Param<int> size; 645 646END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) 647 648BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB) 649 650 INIT_PARAM_DFLT(size, "TLB size", 48) 651 652END_INIT_SIM_OBJECT_PARAMS(AlphaITB) 653 654 655CREATE_SIM_OBJECT(AlphaITB) 656{ 657 return new AlphaITB(getInstanceName(), size); 658} 659 660REGISTER_SIM_OBJECT("AlphaITB", AlphaITB) 661 662BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) 663 664 Param<int> size; 665 666END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) 667 668BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB) 669 670 INIT_PARAM_DFLT(size, "TLB size", 64) 671 672END_INIT_SIM_OBJECT_PARAMS(AlphaDTB) 673 674 675CREATE_SIM_OBJECT(AlphaDTB) 676{ 677 return new AlphaDTB(getInstanceName(), size); 678} 679 680REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB) 681 682