tlb.cc revision 1865
14120Sgblack@eecs.umich.edu/* 24120Sgblack@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 34120Sgblack@eecs.umich.edu * All rights reserved. 44120Sgblack@eecs.umich.edu * 54120Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64120Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74120Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94120Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114120Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124120Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144120Sgblack@eecs.umich.edu * this software without specific prior written permission. 154120Sgblack@eecs.umich.edu * 164120Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174120Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184120Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194120Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274120Sgblack@eecs.umich.edu */ 284120Sgblack@eecs.umich.edu 294120Sgblack@eecs.umich.edu#include <sstream> 304120Sgblack@eecs.umich.edu#include <string> 315334Sgblack@eecs.umich.edu#include <vector> 324120Sgblack@eecs.umich.edu 334120Sgblack@eecs.umich.edu#include "arch/alpha/alpha_memory.hh" 344120Sgblack@eecs.umich.edu#include "base/inifile.hh" 354120Sgblack@eecs.umich.edu#include "base/str.hh" 364120Sgblack@eecs.umich.edu#include "base/trace.hh" 374120Sgblack@eecs.umich.edu#include "config/alpha_tlaser.hh" 384120Sgblack@eecs.umich.edu#include "cpu/exec_context.hh" 394120Sgblack@eecs.umich.edu#include "sim/builder.hh" 404120Sgblack@eecs.umich.edu 414120Sgblack@eecs.umich.eduusing namespace std; 424120Sgblack@eecs.umich.eduusing namespace EV5; 434120Sgblack@eecs.umich.edu 444120Sgblack@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 454120Sgblack@eecs.umich.edu// 464120Sgblack@eecs.umich.edu// Alpha TLB 474120Sgblack@eecs.umich.edu// 484120Sgblack@eecs.umich.edu#ifdef DEBUG 494120Sgblack@eecs.umich.edubool uncacheBit39 = false; 504120Sgblack@eecs.umich.edubool uncacheBit40 = false; 514120Sgblack@eecs.umich.edu#endif 524120Sgblack@eecs.umich.edu 534120Sgblack@eecs.umich.edu#define MODE2MASK(X) (1 << (X)) 544120Sgblack@eecs.umich.edu 554120Sgblack@eecs.umich.eduAlphaTLB::AlphaTLB(const string &name, int s) 564120Sgblack@eecs.umich.edu : SimObject(name), size(s), nlu(0) 574120Sgblack@eecs.umich.edu{ 584120Sgblack@eecs.umich.edu table = new AlphaISA::PTE[size]; 594120Sgblack@eecs.umich.edu memset(table, 0, sizeof(AlphaISA::PTE[size])); 604120Sgblack@eecs.umich.edu} 614120Sgblack@eecs.umich.edu 624120Sgblack@eecs.umich.eduAlphaTLB::~AlphaTLB() 634120Sgblack@eecs.umich.edu{ 644120Sgblack@eecs.umich.edu if (table) 654120Sgblack@eecs.umich.edu delete [] table; 664120Sgblack@eecs.umich.edu} 674120Sgblack@eecs.umich.edu 684120Sgblack@eecs.umich.edu// look up an entry in the TLB 694120Sgblack@eecs.umich.eduAlphaISA::PTE * 704120Sgblack@eecs.umich.eduAlphaTLB::lookup(Addr vpn, uint8_t asn) const 714120Sgblack@eecs.umich.edu{ 724120Sgblack@eecs.umich.edu // assume not found... 734120Sgblack@eecs.umich.edu AlphaISA::PTE *retval = NULL; 744120Sgblack@eecs.umich.edu 754120Sgblack@eecs.umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 764120Sgblack@eecs.umich.edu if (i != lookupTable.end()) { 774120Sgblack@eecs.umich.edu while (i->first == vpn) { 784120Sgblack@eecs.umich.edu int index = i->second; 794120Sgblack@eecs.umich.edu AlphaISA::PTE *pte = &table[index]; 804120Sgblack@eecs.umich.edu assert(pte->valid); 814120Sgblack@eecs.umich.edu if (vpn == pte->tag && (pte->asma || pte->asn == asn)) { 824120Sgblack@eecs.umich.edu retval = pte; 834120Sgblack@eecs.umich.edu break; 844120Sgblack@eecs.umich.edu } 854120Sgblack@eecs.umich.edu 864202Sbinkertn@umich.edu ++i; 875069Sgblack@eecs.umich.edu } 884202Sbinkertn@umich.edu } 895659Sgblack@eecs.umich.edu 904601Sgblack@eecs.umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 914202Sbinkertn@umich.edu retval ? "hit" : "miss", retval ? retval->ppn : 0); 925124Sgblack@eecs.umich.edu return retval; 935083Sgblack@eecs.umich.edu} 944679Sgblack@eecs.umich.edu 955083Sgblack@eecs.umich.edu 964679Sgblack@eecs.umich.eduvoid 974679Sgblack@eecs.umich.eduAlphaTLB::checkCacheability(MemReqPtr &req) 984202Sbinkertn@umich.edu{ 994202Sbinkertn@umich.edu // in Alpha, cacheability is controlled by upper-level bits of the 1005124Sgblack@eecs.umich.edu // physical address 1014249Sgblack@eecs.umich.edu 1024240Sgblack@eecs.umich.edu /* 1034202Sbinkertn@umich.edu * We support having the uncacheable bit in either bit 39 or bit 40. 1044202Sbinkertn@umich.edu * The Turbolaser platform (and EV5) support having the bit in 39, but 1054997Sgblack@eecs.umich.edu * Tsunami (which Linux assumes uses an EV6) generates accesses with 1065135Sgblack@eecs.umich.edu * the bit in 40. So we must check for both, but we have debug flags 1074997Sgblack@eecs.umich.edu * to catch a weird case where both are used, which shouldn't happen. 1084997Sgblack@eecs.umich.edu */ 1095192Ssaidi@eecs.umich.edu 1105192Ssaidi@eecs.umich.edu 1114120Sgblack@eecs.umich.edu#if ALPHA_TLASER 1124202Sbinkertn@umich.edu if (req->paddr & PAddrUncachedBit39) { 1135649Sgblack@eecs.umich.edu#else 1145649Sgblack@eecs.umich.edu if (req->paddr & PAddrUncachedBit43) { 1155647Sgblack@eecs.umich.edu#endif 1165132Sgblack@eecs.umich.edu // IPR memory space not implemented 1175132Sgblack@eecs.umich.edu if (PAddrIprSpace(req->paddr)) { 1184202Sbinkertn@umich.edu if (!req->xc->misspeculating()) { 1195647Sgblack@eecs.umich.edu switch (req->paddr) { 1205299Sgblack@eecs.umich.edu case ULL(0xFFFFF00188): 1215245Sgblack@eecs.umich.edu req->data = 0; 1225132Sgblack@eecs.umich.edu break; 1235086Sgblack@eecs.umich.edu 1245086Sgblack@eecs.umich.edu default: 1254202Sbinkertn@umich.edu panic("IPR memory space not implemented! PA=%x\n", 1264202Sbinkertn@umich.edu req->paddr); 1274120Sgblack@eecs.umich.edu } 1284202Sbinkertn@umich.edu } 1294202Sbinkertn@umich.edu } else { 1304202Sbinkertn@umich.edu // mark request as uncacheable 1314120Sgblack@eecs.umich.edu req->flags |= UNCACHEABLE; 1325069Sgblack@eecs.umich.edu 1335081Sgblack@eecs.umich.edu#if !ALPHA_TLASER 1345081Sgblack@eecs.umich.edu // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 1355081Sgblack@eecs.umich.edu req->paddr &= PAddrUncachedMask; 1365081Sgblack@eecs.umich.edu#endif 1375081Sgblack@eecs.umich.edu } 1385081Sgblack@eecs.umich.edu } 1395081Sgblack@eecs.umich.edu} 1405081Sgblack@eecs.umich.edu 1415081Sgblack@eecs.umich.edu 1425081Sgblack@eecs.umich.edu// insert a new TLB entry 1435081Sgblack@eecs.umich.eduvoid 1445081Sgblack@eecs.umich.eduAlphaTLB::insert(Addr addr, AlphaISA::PTE &pte) 1455081Sgblack@eecs.umich.edu{ 1465081Sgblack@eecs.umich.edu AlphaISA::VAddr vaddr = addr; 1475081Sgblack@eecs.umich.edu if (table[nlu].valid) { 1485081Sgblack@eecs.umich.edu Addr oldvpn = table[nlu].tag; 1495081Sgblack@eecs.umich.edu PageTable::iterator i = lookupTable.find(oldvpn); 1505081Sgblack@eecs.umich.edu 1515081Sgblack@eecs.umich.edu if (i == lookupTable.end()) 1525081Sgblack@eecs.umich.edu panic("TLB entry not found in lookupTable"); 1535081Sgblack@eecs.umich.edu 1545081Sgblack@eecs.umich.edu int index; 1555081Sgblack@eecs.umich.edu while ((index = i->second) != nlu) { 1565081Sgblack@eecs.umich.edu if (table[index].tag != oldvpn) 1575081Sgblack@eecs.umich.edu panic("TLB entry not found in lookupTable"); 1585081Sgblack@eecs.umich.edu 1595081Sgblack@eecs.umich.edu ++i; 1605081Sgblack@eecs.umich.edu } 1615081Sgblack@eecs.umich.edu 1625081Sgblack@eecs.umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 1635081Sgblack@eecs.umich.edu 1645081Sgblack@eecs.umich.edu lookupTable.erase(i); 1655081Sgblack@eecs.umich.edu } 1665081Sgblack@eecs.umich.edu 1675081Sgblack@eecs.umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), pte.ppn); 1685081Sgblack@eecs.umich.edu 1695081Sgblack@eecs.umich.edu table[nlu] = pte; 1705081Sgblack@eecs.umich.edu table[nlu].tag = vaddr.vpn(); 1715081Sgblack@eecs.umich.edu table[nlu].valid = true; 1725081Sgblack@eecs.umich.edu 1735081Sgblack@eecs.umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 1745081Sgblack@eecs.umich.edu nextnlu(); 1755081Sgblack@eecs.umich.edu} 1765081Sgblack@eecs.umich.edu 1775081Sgblack@eecs.umich.eduvoid 1785081Sgblack@eecs.umich.eduAlphaTLB::flushAll() 1795081Sgblack@eecs.umich.edu{ 1805081Sgblack@eecs.umich.edu DPRINTF(TLB, "flushAll\n"); 1815081Sgblack@eecs.umich.edu memset(table, 0, sizeof(AlphaISA::PTE[size])); 1825081Sgblack@eecs.umich.edu lookupTable.clear(); 1835081Sgblack@eecs.umich.edu nlu = 0; 1845081Sgblack@eecs.umich.edu} 1855081Sgblack@eecs.umich.edu 1865081Sgblack@eecs.umich.eduvoid 1875081Sgblack@eecs.umich.eduAlphaTLB::flushProcesses() 1885680Sgblack@eecs.umich.edu{ 1895081Sgblack@eecs.umich.edu PageTable::iterator i = lookupTable.begin(); 1905173Sgblack@eecs.umich.edu PageTable::iterator end = lookupTable.end(); 1915359Sgblack@eecs.umich.edu while (i != end) { 1925081Sgblack@eecs.umich.edu int index = i->second; 1935149Sgblack@eecs.umich.edu AlphaISA::PTE *pte = &table[index]; 1945298Sgblack@eecs.umich.edu assert(pte->valid); 1955081Sgblack@eecs.umich.edu 1965081Sgblack@eecs.umich.edu // we can't increment i after we erase it, so save a copy and 1975081Sgblack@eecs.umich.edu // increment it to get the next entry now 1985081Sgblack@eecs.umich.edu PageTable::iterator cur = i; 1995081Sgblack@eecs.umich.edu ++i; 2005081Sgblack@eecs.umich.edu 2015081Sgblack@eecs.umich.edu if (!pte->asma) { 2025081Sgblack@eecs.umich.edu DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn); 2035081Sgblack@eecs.umich.edu pte->valid = false; 2045081Sgblack@eecs.umich.edu lookupTable.erase(cur); 2055081Sgblack@eecs.umich.edu } 2065081Sgblack@eecs.umich.edu } 2075081Sgblack@eecs.umich.edu} 2085081Sgblack@eecs.umich.edu 2095081Sgblack@eecs.umich.eduvoid 2105081Sgblack@eecs.umich.eduAlphaTLB::flushAddr(Addr addr, uint8_t asn) 2115081Sgblack@eecs.umich.edu{ 2125081Sgblack@eecs.umich.edu AlphaISA::VAddr vaddr = addr; 2135081Sgblack@eecs.umich.edu 2145081Sgblack@eecs.umich.edu PageTable::iterator i = lookupTable.find(vaddr.vpn()); 2155081Sgblack@eecs.umich.edu if (i == lookupTable.end()) 2165081Sgblack@eecs.umich.edu return; 2175081Sgblack@eecs.umich.edu 2185081Sgblack@eecs.umich.edu while (i->first == vaddr.vpn()) { 2195081Sgblack@eecs.umich.edu int index = i->second; 2205081Sgblack@eecs.umich.edu AlphaISA::PTE *pte = &table[index]; 2215081Sgblack@eecs.umich.edu assert(pte->valid); 2225081Sgblack@eecs.umich.edu 2235081Sgblack@eecs.umich.edu if (vaddr.vpn() == pte->tag && (pte->asma || pte->asn == asn)) { 2245081Sgblack@eecs.umich.edu DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 2255081Sgblack@eecs.umich.edu pte->ppn); 2265081Sgblack@eecs.umich.edu 2275081Sgblack@eecs.umich.edu // invalidate this entry 2285081Sgblack@eecs.umich.edu pte->valid = false; 2295081Sgblack@eecs.umich.edu 2305081Sgblack@eecs.umich.edu lookupTable.erase(i); 2315081Sgblack@eecs.umich.edu } 2325081Sgblack@eecs.umich.edu 2335081Sgblack@eecs.umich.edu ++i; 2345081Sgblack@eecs.umich.edu } 2355081Sgblack@eecs.umich.edu} 2365081Sgblack@eecs.umich.edu 2375081Sgblack@eecs.umich.edu 2385081Sgblack@eecs.umich.eduvoid 2395081Sgblack@eecs.umich.eduAlphaTLB::serialize(ostream &os) 2405081Sgblack@eecs.umich.edu{ 2415081Sgblack@eecs.umich.edu SERIALIZE_SCALAR(size); 2425081Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nlu); 2435081Sgblack@eecs.umich.edu 2445081Sgblack@eecs.umich.edu for (int i = 0; i < size; i++) { 2455081Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.PTE%d", name(), i)); 2465081Sgblack@eecs.umich.edu table[i].serialize(os); 2475081Sgblack@eecs.umich.edu } 2485081Sgblack@eecs.umich.edu} 2495081Sgblack@eecs.umich.edu 2505081Sgblack@eecs.umich.eduvoid 2515081Sgblack@eecs.umich.eduAlphaTLB::unserialize(Checkpoint *cp, const string §ion) 2525081Sgblack@eecs.umich.edu{ 2535081Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(size); 2545081Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nlu); 2555081Sgblack@eecs.umich.edu 2565081Sgblack@eecs.umich.edu for (int i = 0; i < size; i++) { 2575081Sgblack@eecs.umich.edu table[i].unserialize(cp, csprintf("%s.PTE%d", section, i)); 2585081Sgblack@eecs.umich.edu if (table[i].valid) { 2595081Sgblack@eecs.umich.edu lookupTable.insert(make_pair(table[i].tag, i)); 2605081Sgblack@eecs.umich.edu } 2615081Sgblack@eecs.umich.edu } 2625081Sgblack@eecs.umich.edu} 2635081Sgblack@eecs.umich.edu 2645081Sgblack@eecs.umich.edu 2655081Sgblack@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 2665081Sgblack@eecs.umich.edu// 2675081Sgblack@eecs.umich.edu// Alpha ITB 2685081Sgblack@eecs.umich.edu// 2695081Sgblack@eecs.umich.eduAlphaITB::AlphaITB(const std::string &name, int size) 2705081Sgblack@eecs.umich.edu : AlphaTLB(name, size) 2715081Sgblack@eecs.umich.edu{} 2725081Sgblack@eecs.umich.edu 2735081Sgblack@eecs.umich.edu 2745081Sgblack@eecs.umich.eduvoid 2755081Sgblack@eecs.umich.eduAlphaITB::regStats() 2765081Sgblack@eecs.umich.edu{ 2775081Sgblack@eecs.umich.edu hits 2785081Sgblack@eecs.umich.edu .name(name() + ".hits") 2795081Sgblack@eecs.umich.edu .desc("ITB hits"); 2805081Sgblack@eecs.umich.edu misses 2815081Sgblack@eecs.umich.edu .name(name() + ".misses") 2825081Sgblack@eecs.umich.edu .desc("ITB misses"); 2835081Sgblack@eecs.umich.edu acv 2845081Sgblack@eecs.umich.edu .name(name() + ".acv") 2855081Sgblack@eecs.umich.edu .desc("ITB acv"); 2865081Sgblack@eecs.umich.edu accesses 2875081Sgblack@eecs.umich.edu .name(name() + ".accesses") 2885081Sgblack@eecs.umich.edu .desc("ITB accesses"); 2895081Sgblack@eecs.umich.edu 2905081Sgblack@eecs.umich.edu accesses = hits + misses; 2915081Sgblack@eecs.umich.edu} 2925081Sgblack@eecs.umich.edu 2935081Sgblack@eecs.umich.eduvoid 2945081Sgblack@eecs.umich.eduAlphaITB::fault(Addr pc, ExecContext *xc) const 2955081Sgblack@eecs.umich.edu{ 2965081Sgblack@eecs.umich.edu uint64_t *ipr = xc->regs.ipr; 2975081Sgblack@eecs.umich.edu 2985081Sgblack@eecs.umich.edu if (!xc->misspeculating()) { 2995081Sgblack@eecs.umich.edu ipr[AlphaISA::IPR_ITB_TAG] = pc; 3005081Sgblack@eecs.umich.edu ipr[AlphaISA::IPR_IFAULT_VA_FORM] = 3015081Sgblack@eecs.umich.edu ipr[AlphaISA::IPR_IVPTBR] | (AlphaISA::VAddr(pc).vpn() << 3); 3025081Sgblack@eecs.umich.edu } 3035081Sgblack@eecs.umich.edu} 3045081Sgblack@eecs.umich.edu 3055081Sgblack@eecs.umich.edu 3065081Sgblack@eecs.umich.eduFault 3075081Sgblack@eecs.umich.eduAlphaITB::translate(MemReqPtr &req) const 3085081Sgblack@eecs.umich.edu{ 3095081Sgblack@eecs.umich.edu InternalProcReg *ipr = req->xc->regs.ipr; 3105081Sgblack@eecs.umich.edu 3115081Sgblack@eecs.umich.edu if (AlphaISA::PcPAL(req->vaddr)) { 3125081Sgblack@eecs.umich.edu // strip off PAL PC marker (lsb is 1) 3135081Sgblack@eecs.umich.edu req->paddr = (req->vaddr & ~3) & PAddrImplMask; 3145081Sgblack@eecs.umich.edu hits++; 3155081Sgblack@eecs.umich.edu return No_Fault; 3165081Sgblack@eecs.umich.edu } 3175081Sgblack@eecs.umich.edu 3185081Sgblack@eecs.umich.edu if (req->flags & PHYSICAL) { 3195081Sgblack@eecs.umich.edu req->paddr = req->vaddr; 3205081Sgblack@eecs.umich.edu } else { 3215081Sgblack@eecs.umich.edu // verify that this is a good virtual address 3225081Sgblack@eecs.umich.edu if (!validVirtualAddress(req->vaddr)) { 3235081Sgblack@eecs.umich.edu fault(req->vaddr, req->xc); 3245081Sgblack@eecs.umich.edu acv++; 3255081Sgblack@eecs.umich.edu return ITB_Acv_Fault; 3265081Sgblack@eecs.umich.edu } 3275081Sgblack@eecs.umich.edu 3285081Sgblack@eecs.umich.edu 3295081Sgblack@eecs.umich.edu // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 3305081Sgblack@eecs.umich.edu // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 3315081Sgblack@eecs.umich.edu#if ALPHA_TLASER 3325081Sgblack@eecs.umich.edu if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && 3335081Sgblack@eecs.umich.edu VAddrSpaceEV5(req->vaddr) == 2) { 3345081Sgblack@eecs.umich.edu#else 3355081Sgblack@eecs.umich.edu if (VAddrSpaceEV6(req->vaddr) == 0x7e) { 3365081Sgblack@eecs.umich.edu#endif 3375081Sgblack@eecs.umich.edu // only valid in kernel mode 3385081Sgblack@eecs.umich.edu if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != 3395081Sgblack@eecs.umich.edu AlphaISA::mode_kernel) { 3405081Sgblack@eecs.umich.edu fault(req->vaddr, req->xc); 3415081Sgblack@eecs.umich.edu acv++; 3425081Sgblack@eecs.umich.edu return ITB_Acv_Fault; 3435081Sgblack@eecs.umich.edu } 3445081Sgblack@eecs.umich.edu 3455081Sgblack@eecs.umich.edu req->paddr = req->vaddr & PAddrImplMask; 3465081Sgblack@eecs.umich.edu 3475081Sgblack@eecs.umich.edu#if !ALPHA_TLASER 3485081Sgblack@eecs.umich.edu // sign extend the physical address properly 3495081Sgblack@eecs.umich.edu if (req->paddr & PAddrUncachedBit40) 3505069Sgblack@eecs.umich.edu req->paddr |= ULL(0xf0000000000); 3514202Sbinkertn@umich.edu else 3524202Sbinkertn@umich.edu req->paddr &= ULL(0xffffffffff); 3534202Sbinkertn@umich.edu#endif 3545069Sgblack@eecs.umich.edu 3555069Sgblack@eecs.umich.edu } else { 3565069Sgblack@eecs.umich.edu // not a physical address: need to look up pte 3575069Sgblack@eecs.umich.edu AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), 3584202Sbinkertn@umich.edu DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 3594202Sbinkertn@umich.edu 3605406Ssaidi@eecs.umich.edu if (!pte) { 3615406Ssaidi@eecs.umich.edu fault(req->vaddr, req->xc); 3625406Ssaidi@eecs.umich.edu misses++; 3635406Ssaidi@eecs.umich.edu return ITB_Fault_Fault; 3645406Ssaidi@eecs.umich.edu } 3655406Ssaidi@eecs.umich.edu 3665406Ssaidi@eecs.umich.edu req->paddr = (pte->ppn << AlphaISA::PageShift) + 3675406Ssaidi@eecs.umich.edu (AlphaISA::VAddr(req->vaddr).offset() & ~3); 3685406Ssaidi@eecs.umich.edu 3695406Ssaidi@eecs.umich.edu // check permissions for this access 3705406Ssaidi@eecs.umich.edu if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) { 3715406Ssaidi@eecs.umich.edu // instruction access fault 3725406Ssaidi@eecs.umich.edu fault(req->vaddr, req->xc); 3735406Ssaidi@eecs.umich.edu acv++; 374 return ITB_Acv_Fault; 375 } 376 377 hits++; 378 } 379 } 380 381 // check that the physical address is ok (catch bad physical addresses) 382 if (req->paddr & ~PAddrImplMask) 383 return Machine_Check_Fault; 384 385 checkCacheability(req); 386 387 return No_Fault; 388} 389 390/////////////////////////////////////////////////////////////////////// 391// 392// Alpha DTB 393// 394AlphaDTB::AlphaDTB(const std::string &name, int size) 395 : AlphaTLB(name, size) 396{} 397 398void 399AlphaDTB::regStats() 400{ 401 read_hits 402 .name(name() + ".read_hits") 403 .desc("DTB read hits") 404 ; 405 406 read_misses 407 .name(name() + ".read_misses") 408 .desc("DTB read misses") 409 ; 410 411 read_acv 412 .name(name() + ".read_acv") 413 .desc("DTB read access violations") 414 ; 415 416 read_accesses 417 .name(name() + ".read_accesses") 418 .desc("DTB read accesses") 419 ; 420 421 write_hits 422 .name(name() + ".write_hits") 423 .desc("DTB write hits") 424 ; 425 426 write_misses 427 .name(name() + ".write_misses") 428 .desc("DTB write misses") 429 ; 430 431 write_acv 432 .name(name() + ".write_acv") 433 .desc("DTB write access violations") 434 ; 435 436 write_accesses 437 .name(name() + ".write_accesses") 438 .desc("DTB write accesses") 439 ; 440 441 hits 442 .name(name() + ".hits") 443 .desc("DTB hits") 444 ; 445 446 misses 447 .name(name() + ".misses") 448 .desc("DTB misses") 449 ; 450 451 acv 452 .name(name() + ".acv") 453 .desc("DTB access violations") 454 ; 455 456 accesses 457 .name(name() + ".accesses") 458 .desc("DTB accesses") 459 ; 460 461 hits = read_hits + write_hits; 462 misses = read_misses + write_misses; 463 acv = read_acv + write_acv; 464 accesses = read_accesses + write_accesses; 465} 466 467void 468AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const 469{ 470 ExecContext *xc = req->xc; 471 AlphaISA::VAddr vaddr = req->vaddr; 472 uint64_t *ipr = xc->regs.ipr; 473 474 // Set fault address and flags. Even though we're modeling an 475 // EV5, we use the EV6 technique of not latching fault registers 476 // on VPTE loads (instead of locking the registers until IPR_VA is 477 // read, like the EV5). The EV6 approach is cleaner and seems to 478 // work with EV5 PAL code, but not the other way around. 479 if (!xc->misspeculating() 480 && !(req->flags & VPTE) && !(req->flags & NO_FAULT)) { 481 // set VA register with faulting address 482 ipr[AlphaISA::IPR_VA] = req->vaddr; 483 484 // set MM_STAT register flags 485 ipr[AlphaISA::IPR_MM_STAT] = 486 (((Opcode(xc->getInst()) & 0x3f) << 11) 487 | ((Ra(xc->getInst()) & 0x1f) << 6) 488 | (flags & 0x3f)); 489 490 // set VA_FORM register with faulting formatted address 491 ipr[AlphaISA::IPR_VA_FORM] = 492 ipr[AlphaISA::IPR_MVPTBR] | (vaddr.vpn() << 3); 493 } 494} 495 496Fault 497AlphaDTB::translate(MemReqPtr &req, bool write) const 498{ 499 RegFile *regs = &req->xc->regs; 500 Addr pc = regs->pc; 501 InternalProcReg *ipr = regs->ipr; 502 503 AlphaISA::mode_type mode = 504 (AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]); 505 506 507 /** 508 * Check for alignment faults 509 */ 510 if (req->vaddr & (req->size - 1)) { 511 fault(req, write ? MM_STAT_WR_MASK : 0); 512 DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr, 513 req->size); 514 return Alignment_Fault; 515 } 516 517 if (pc & 0x1) { 518 mode = (req->flags & ALTMODE) ? 519 (AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE]) 520 : AlphaISA::mode_kernel; 521 } 522 523 if (req->flags & PHYSICAL) { 524 req->paddr = req->vaddr; 525 } else { 526 // verify that this is a good virtual address 527 if (!validVirtualAddress(req->vaddr)) { 528 fault(req, (write ? MM_STAT_WR_MASK : 0) | 529 MM_STAT_BAD_VA_MASK | 530 MM_STAT_ACV_MASK); 531 532 if (write) { write_acv++; } else { read_acv++; } 533 return DTB_Fault_Fault; 534 } 535 536 // Check for "superpage" mapping 537#if ALPHA_TLASER 538 if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) && 539 VAddrSpaceEV5(req->vaddr) == 2) { 540#else 541 if (VAddrSpaceEV6(req->vaddr) == 0x7e) { 542#endif 543 544 // only valid in kernel mode 545 if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) != 546 AlphaISA::mode_kernel) { 547 fault(req, ((write ? MM_STAT_WR_MASK : 0) | 548 MM_STAT_ACV_MASK)); 549 if (write) { write_acv++; } else { read_acv++; } 550 return DTB_Acv_Fault; 551 } 552 553 req->paddr = req->vaddr & PAddrImplMask; 554 555#if !ALPHA_TLASER 556 // sign extend the physical address properly 557 if (req->paddr & PAddrUncachedBit40) 558 req->paddr |= ULL(0xf0000000000); 559 else 560 req->paddr &= ULL(0xffffffffff); 561#endif 562 563 } else { 564 if (write) 565 write_accesses++; 566 else 567 read_accesses++; 568 569 // not a physical address: need to look up pte 570 AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(), 571 DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); 572 573 if (!pte) { 574 // page fault 575 fault(req, (write ? MM_STAT_WR_MASK : 0) | 576 MM_STAT_DTB_MISS_MASK); 577 if (write) { write_misses++; } else { read_misses++; } 578 return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault; 579 } 580 581 req->paddr = (pte->ppn << AlphaISA::PageShift) + 582 AlphaISA::VAddr(req->vaddr).offset(); 583 584 if (write) { 585 if (!(pte->xwe & MODE2MASK(mode))) { 586 // declare the instruction access fault 587 fault(req, MM_STAT_WR_MASK | 588 MM_STAT_ACV_MASK | 589 (pte->fonw ? MM_STAT_FONW_MASK : 0)); 590 write_acv++; 591 return DTB_Fault_Fault; 592 } 593 if (pte->fonw) { 594 fault(req, MM_STAT_WR_MASK | 595 MM_STAT_FONW_MASK); 596 write_acv++; 597 return DTB_Fault_Fault; 598 } 599 } else { 600 if (!(pte->xre & MODE2MASK(mode))) { 601 fault(req, MM_STAT_ACV_MASK | 602 (pte->fonr ? MM_STAT_FONR_MASK : 0)); 603 read_acv++; 604 return DTB_Acv_Fault; 605 } 606 if (pte->fonr) { 607 fault(req, MM_STAT_FONR_MASK); 608 read_acv++; 609 return DTB_Fault_Fault; 610 } 611 } 612 } 613 614 if (write) 615 write_hits++; 616 else 617 read_hits++; 618 } 619 620 // check that the physical address is ok (catch bad physical addresses) 621 if (req->paddr & ~PAddrImplMask) 622 return Machine_Check_Fault; 623 624 checkCacheability(req); 625 626 return No_Fault; 627} 628 629AlphaISA::PTE & 630AlphaTLB::index(bool advance) 631{ 632 AlphaISA::PTE *pte = &table[nlu]; 633 634 if (advance) 635 nextnlu(); 636 637 return *pte; 638} 639 640DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB) 641 642BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) 643 644 Param<int> size; 645 646END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB) 647 648BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB) 649 650 INIT_PARAM_DFLT(size, "TLB size", 48) 651 652END_INIT_SIM_OBJECT_PARAMS(AlphaITB) 653 654 655CREATE_SIM_OBJECT(AlphaITB) 656{ 657 return new AlphaITB(getInstanceName(), size); 658} 659 660REGISTER_SIM_OBJECT("AlphaITB", AlphaITB) 661 662BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) 663 664 Param<int> size; 665 666END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB) 667 668BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB) 669 670 INIT_PARAM_DFLT(size, "TLB size", 64) 671 672END_INIT_SIM_OBJECT_PARAMS(AlphaDTB) 673 674 675CREATE_SIM_OBJECT(AlphaDTB) 676{ 677 return new AlphaDTB(getInstanceName(), size); 678} 679 680REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB) 681 682