tlb.cc revision 9738
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Andrew Schultz 312SN/A */ 322SN/A 332SN/A#include <string> 342SN/A#include <vector> 352SN/A 368229Snate@binkert.org#include "arch/alpha/faults.hh" 372984Sgblack@eecs.umich.edu#include "arch/alpha/pagetable.hh" 382171SN/A#include "arch/alpha/tlb.hh" 398591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 40146SN/A#include "base/inifile.hh" 41146SN/A#include "base/str.hh" 42146SN/A#include "base/trace.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 448232Snate@binkert.org#include "debug/TLB.hh" 458738Sgblack@eecs.umich.edu#include "sim/full_system.hh" 462SN/A 472SN/Ausing namespace std; 482SN/A 494088Sbinkertn@umich.edunamespace AlphaISA { 505569Snate@binkert.org 513838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 523838Shsul@eecs.umich.edu// 533838Shsul@eecs.umich.edu// Alpha TLB 543838Shsul@eecs.umich.edu// 555569Snate@binkert.org 56860SN/A#ifdef DEBUG 573838Shsul@eecs.umich.edubool uncacheBit39 = false; 583838Shsul@eecs.umich.edubool uncacheBit40 = false; 59860SN/A#endif 60860SN/A 615569Snate@binkert.org#define MODE2MASK(X) (1 << (X)) 621147SN/A 635034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 645358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), nlu(0) 653838Shsul@eecs.umich.edu{ 665004Sgblack@eecs.umich.edu table = new TlbEntry[size]; 678737Skoansin.tan@gmail.com memset(table, 0, sizeof(TlbEntry) * size); 684957Sacolyte@umich.edu flushCache(); 693838Shsul@eecs.umich.edu} 702SN/A 713838Shsul@eecs.umich.eduTLB::~TLB() 723838Shsul@eecs.umich.edu{ 733838Shsul@eecs.umich.edu if (table) 743838Shsul@eecs.umich.edu delete [] table; 753838Shsul@eecs.umich.edu} 762SN/A 776022Sgblack@eecs.umich.eduvoid 786022Sgblack@eecs.umich.eduTLB::regStats() 796022Sgblack@eecs.umich.edu{ 806022Sgblack@eecs.umich.edu fetch_hits 816022Sgblack@eecs.umich.edu .name(name() + ".fetch_hits") 826022Sgblack@eecs.umich.edu .desc("ITB hits"); 836022Sgblack@eecs.umich.edu fetch_misses 846022Sgblack@eecs.umich.edu .name(name() + ".fetch_misses") 856022Sgblack@eecs.umich.edu .desc("ITB misses"); 866022Sgblack@eecs.umich.edu fetch_acv 876022Sgblack@eecs.umich.edu .name(name() + ".fetch_acv") 886022Sgblack@eecs.umich.edu .desc("ITB acv"); 896022Sgblack@eecs.umich.edu fetch_accesses 906022Sgblack@eecs.umich.edu .name(name() + ".fetch_accesses") 916022Sgblack@eecs.umich.edu .desc("ITB accesses"); 926022Sgblack@eecs.umich.edu 936022Sgblack@eecs.umich.edu fetch_accesses = fetch_hits + fetch_misses; 946022Sgblack@eecs.umich.edu 956022Sgblack@eecs.umich.edu read_hits 966022Sgblack@eecs.umich.edu .name(name() + ".read_hits") 976022Sgblack@eecs.umich.edu .desc("DTB read hits") 986022Sgblack@eecs.umich.edu ; 996022Sgblack@eecs.umich.edu 1006022Sgblack@eecs.umich.edu read_misses 1016022Sgblack@eecs.umich.edu .name(name() + ".read_misses") 1026022Sgblack@eecs.umich.edu .desc("DTB read misses") 1036022Sgblack@eecs.umich.edu ; 1046022Sgblack@eecs.umich.edu 1056022Sgblack@eecs.umich.edu read_acv 1066022Sgblack@eecs.umich.edu .name(name() + ".read_acv") 1076022Sgblack@eecs.umich.edu .desc("DTB read access violations") 1086022Sgblack@eecs.umich.edu ; 1096022Sgblack@eecs.umich.edu 1106022Sgblack@eecs.umich.edu read_accesses 1116022Sgblack@eecs.umich.edu .name(name() + ".read_accesses") 1126022Sgblack@eecs.umich.edu .desc("DTB read accesses") 1136022Sgblack@eecs.umich.edu ; 1146022Sgblack@eecs.umich.edu 1156022Sgblack@eecs.umich.edu write_hits 1166022Sgblack@eecs.umich.edu .name(name() + ".write_hits") 1176022Sgblack@eecs.umich.edu .desc("DTB write hits") 1186022Sgblack@eecs.umich.edu ; 1196022Sgblack@eecs.umich.edu 1206022Sgblack@eecs.umich.edu write_misses 1216022Sgblack@eecs.umich.edu .name(name() + ".write_misses") 1226022Sgblack@eecs.umich.edu .desc("DTB write misses") 1236022Sgblack@eecs.umich.edu ; 1246022Sgblack@eecs.umich.edu 1256022Sgblack@eecs.umich.edu write_acv 1266022Sgblack@eecs.umich.edu .name(name() + ".write_acv") 1276022Sgblack@eecs.umich.edu .desc("DTB write access violations") 1286022Sgblack@eecs.umich.edu ; 1296022Sgblack@eecs.umich.edu 1306022Sgblack@eecs.umich.edu write_accesses 1316022Sgblack@eecs.umich.edu .name(name() + ".write_accesses") 1326022Sgblack@eecs.umich.edu .desc("DTB write accesses") 1336022Sgblack@eecs.umich.edu ; 1346022Sgblack@eecs.umich.edu 1356022Sgblack@eecs.umich.edu data_hits 1366022Sgblack@eecs.umich.edu .name(name() + ".data_hits") 1376022Sgblack@eecs.umich.edu .desc("DTB hits") 1386022Sgblack@eecs.umich.edu ; 1396022Sgblack@eecs.umich.edu 1406022Sgblack@eecs.umich.edu data_misses 1416022Sgblack@eecs.umich.edu .name(name() + ".data_misses") 1426022Sgblack@eecs.umich.edu .desc("DTB misses") 1436022Sgblack@eecs.umich.edu ; 1446022Sgblack@eecs.umich.edu 1456022Sgblack@eecs.umich.edu data_acv 1466022Sgblack@eecs.umich.edu .name(name() + ".data_acv") 1476022Sgblack@eecs.umich.edu .desc("DTB access violations") 1486022Sgblack@eecs.umich.edu ; 1496022Sgblack@eecs.umich.edu 1506022Sgblack@eecs.umich.edu data_accesses 1516022Sgblack@eecs.umich.edu .name(name() + ".data_accesses") 1526022Sgblack@eecs.umich.edu .desc("DTB accesses") 1536022Sgblack@eecs.umich.edu ; 1546022Sgblack@eecs.umich.edu 1556022Sgblack@eecs.umich.edu data_hits = read_hits + write_hits; 1566022Sgblack@eecs.umich.edu data_misses = read_misses + write_misses; 1576022Sgblack@eecs.umich.edu data_acv = read_acv + write_acv; 1586022Sgblack@eecs.umich.edu data_accesses = read_accesses + write_accesses; 1596022Sgblack@eecs.umich.edu} 1606022Sgblack@eecs.umich.edu 1613838Shsul@eecs.umich.edu// look up an entry in the TLB 1625004Sgblack@eecs.umich.eduTlbEntry * 1634967Sacolyte@umich.eduTLB::lookup(Addr vpn, uint8_t asn) 1643838Shsul@eecs.umich.edu{ 1653838Shsul@eecs.umich.edu // assume not found... 1665004Sgblack@eecs.umich.edu TlbEntry *retval = NULL; 1672SN/A 1685004Sgblack@eecs.umich.edu if (EntryCache[0]) { 1695004Sgblack@eecs.umich.edu if (vpn == EntryCache[0]->tag && 1705004Sgblack@eecs.umich.edu (EntryCache[0]->asma || EntryCache[0]->asn == asn)) 1715004Sgblack@eecs.umich.edu retval = EntryCache[0]; 1725004Sgblack@eecs.umich.edu else if (EntryCache[1]) { 1735004Sgblack@eecs.umich.edu if (vpn == EntryCache[1]->tag && 1745004Sgblack@eecs.umich.edu (EntryCache[1]->asma || EntryCache[1]->asn == asn)) 1755004Sgblack@eecs.umich.edu retval = EntryCache[1]; 1765004Sgblack@eecs.umich.edu else if (EntryCache[2] && vpn == EntryCache[2]->tag && 1775004Sgblack@eecs.umich.edu (EntryCache[2]->asma || EntryCache[2]->asn == asn)) 1785004Sgblack@eecs.umich.edu retval = EntryCache[2]; 1794962Sacolyte@umich.edu } 1804962Sacolyte@umich.edu } 1814962Sacolyte@umich.edu 1824967Sacolyte@umich.edu if (retval == NULL) { 1834957Sacolyte@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 1844957Sacolyte@umich.edu if (i != lookupTable.end()) { 1854957Sacolyte@umich.edu while (i->first == vpn) { 1864957Sacolyte@umich.edu int index = i->second; 1875004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 1885004Sgblack@eecs.umich.edu assert(entry->valid); 1895004Sgblack@eecs.umich.edu if (vpn == entry->tag && (entry->asma || entry->asn == asn)) { 1905004Sgblack@eecs.umich.edu retval = updateCache(entry); 1914957Sacolyte@umich.edu break; 1924957Sacolyte@umich.edu } 1934957Sacolyte@umich.edu 1944957Sacolyte@umich.edu ++i; 1951413SN/A } 1961413SN/A } 1972SN/A } 1982SN/A 1993838Shsul@eecs.umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 2003838Shsul@eecs.umich.edu retval ? "hit" : "miss", retval ? retval->ppn : 0); 2013838Shsul@eecs.umich.edu return retval; 2023838Shsul@eecs.umich.edu} 2032SN/A 2043838Shsul@eecs.umich.eduFault 2055532Ssaidi@eecs.umich.eduTLB::checkCacheability(RequestPtr &req, bool itb) 2063838Shsul@eecs.umich.edu{ 2075569Snate@binkert.org // in Alpha, cacheability is controlled by upper-level bits of the 2085569Snate@binkert.org // physical address 2093838Shsul@eecs.umich.edu 2105569Snate@binkert.org /* 2115569Snate@binkert.org * We support having the uncacheable bit in either bit 39 or bit 2125569Snate@binkert.org * 40. The Turbolaser platform (and EV5) support having the bit 2135569Snate@binkert.org * in 39, but Tsunami (which Linux assumes uses an EV6) generates 2145569Snate@binkert.org * accesses with the bit in 40. So we must check for both, but we 2155569Snate@binkert.org * have debug flags to catch a weird case where both are used, 2165569Snate@binkert.org * which shouldn't happen. 2175569Snate@binkert.org */ 2183838Shsul@eecs.umich.edu 2193838Shsul@eecs.umich.edu 2206025Snate@binkert.org if (req->getPaddr() & PAddrUncachedBit43) { 2213838Shsul@eecs.umich.edu // IPR memory space not implemented 2223838Shsul@eecs.umich.edu if (PAddrIprSpace(req->getPaddr())) { 2233838Shsul@eecs.umich.edu return new UnimpFault("IPR memory space not implemented!"); 2243838Shsul@eecs.umich.edu } else { 2253838Shsul@eecs.umich.edu // mark request as uncacheable 2265736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 2273838Shsul@eecs.umich.edu 2285569Snate@binkert.org // Clear bits 42:35 of the physical address (10-2 in 2295569Snate@binkert.org // Tsunami manual) 2303838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & PAddrUncachedMask); 231924SN/A } 2325532Ssaidi@eecs.umich.edu // We shouldn't be able to read from an uncachable address in Alpha as 2335532Ssaidi@eecs.umich.edu // we don't have a ROM and we don't want to try to fetch from a device 2345532Ssaidi@eecs.umich.edu // register as we destroy any data that is clear-on-read. 2355532Ssaidi@eecs.umich.edu if (req->isUncacheable() && itb) 2365532Ssaidi@eecs.umich.edu return new UnimpFault("CPU trying to fetch from uncached I/O"); 2375532Ssaidi@eecs.umich.edu 2382SN/A } 2393838Shsul@eecs.umich.edu return NoFault; 2403838Shsul@eecs.umich.edu} 2412SN/A 2422SN/A 2433838Shsul@eecs.umich.edu// insert a new TLB entry 2443838Shsul@eecs.umich.eduvoid 2455004Sgblack@eecs.umich.eduTLB::insert(Addr addr, TlbEntry &entry) 2463838Shsul@eecs.umich.edu{ 2474957Sacolyte@umich.edu flushCache(); 2483838Shsul@eecs.umich.edu VAddr vaddr = addr; 2493838Shsul@eecs.umich.edu if (table[nlu].valid) { 2503838Shsul@eecs.umich.edu Addr oldvpn = table[nlu].tag; 2513838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(oldvpn); 2523838Shsul@eecs.umich.edu 2533838Shsul@eecs.umich.edu if (i == lookupTable.end()) 2543838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 2553838Shsul@eecs.umich.edu 2563838Shsul@eecs.umich.edu int index; 2573838Shsul@eecs.umich.edu while ((index = i->second) != nlu) { 2583838Shsul@eecs.umich.edu if (table[index].tag != oldvpn) 2593838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 2603838Shsul@eecs.umich.edu 2613838Shsul@eecs.umich.edu ++i; 2623838Shsul@eecs.umich.edu } 2633838Shsul@eecs.umich.edu 2643838Shsul@eecs.umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 2653838Shsul@eecs.umich.edu 2663838Shsul@eecs.umich.edu lookupTable.erase(i); 2673838Shsul@eecs.umich.edu } 2683838Shsul@eecs.umich.edu 2695004Sgblack@eecs.umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn); 2703838Shsul@eecs.umich.edu 2715004Sgblack@eecs.umich.edu table[nlu] = entry; 2723838Shsul@eecs.umich.edu table[nlu].tag = vaddr.vpn(); 2733838Shsul@eecs.umich.edu table[nlu].valid = true; 2743838Shsul@eecs.umich.edu 2753838Shsul@eecs.umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 2763838Shsul@eecs.umich.edu nextnlu(); 2773838Shsul@eecs.umich.edu} 2783838Shsul@eecs.umich.edu 2793838Shsul@eecs.umich.eduvoid 2803838Shsul@eecs.umich.eduTLB::flushAll() 2813838Shsul@eecs.umich.edu{ 2823838Shsul@eecs.umich.edu DPRINTF(TLB, "flushAll\n"); 2838737Skoansin.tan@gmail.com memset(table, 0, sizeof(TlbEntry) * size); 2844957Sacolyte@umich.edu flushCache(); 2853838Shsul@eecs.umich.edu lookupTable.clear(); 2863838Shsul@eecs.umich.edu nlu = 0; 2873838Shsul@eecs.umich.edu} 2883838Shsul@eecs.umich.edu 2893838Shsul@eecs.umich.eduvoid 2903838Shsul@eecs.umich.eduTLB::flushProcesses() 2913838Shsul@eecs.umich.edu{ 2924957Sacolyte@umich.edu flushCache(); 2933838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.begin(); 2943838Shsul@eecs.umich.edu PageTable::iterator end = lookupTable.end(); 2953838Shsul@eecs.umich.edu while (i != end) { 2963838Shsul@eecs.umich.edu int index = i->second; 2975004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 2985004Sgblack@eecs.umich.edu assert(entry->valid); 2993838Shsul@eecs.umich.edu 3003838Shsul@eecs.umich.edu // we can't increment i after we erase it, so save a copy and 3013838Shsul@eecs.umich.edu // increment it to get the next entry now 3023838Shsul@eecs.umich.edu PageTable::iterator cur = i; 3033838Shsul@eecs.umich.edu ++i; 3043838Shsul@eecs.umich.edu 3055004Sgblack@eecs.umich.edu if (!entry->asma) { 3065569Snate@binkert.org DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, 3075569Snate@binkert.org entry->tag, entry->ppn); 3085004Sgblack@eecs.umich.edu entry->valid = false; 3093838Shsul@eecs.umich.edu lookupTable.erase(cur); 3103453Sgblack@eecs.umich.edu } 3113453Sgblack@eecs.umich.edu } 3123838Shsul@eecs.umich.edu} 3132SN/A 3143838Shsul@eecs.umich.eduvoid 3153838Shsul@eecs.umich.eduTLB::flushAddr(Addr addr, uint8_t asn) 3163838Shsul@eecs.umich.edu{ 3174957Sacolyte@umich.edu flushCache(); 3183838Shsul@eecs.umich.edu VAddr vaddr = addr; 3192SN/A 3203838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(vaddr.vpn()); 3213838Shsul@eecs.umich.edu if (i == lookupTable.end()) 3223838Shsul@eecs.umich.edu return; 3232SN/A 3244428Ssaidi@eecs.umich.edu while (i != lookupTable.end() && i->first == vaddr.vpn()) { 3253838Shsul@eecs.umich.edu int index = i->second; 3265004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 3275004Sgblack@eecs.umich.edu assert(entry->valid); 3283453Sgblack@eecs.umich.edu 3295004Sgblack@eecs.umich.edu if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) { 3303838Shsul@eecs.umich.edu DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 3315004Sgblack@eecs.umich.edu entry->ppn); 3323453Sgblack@eecs.umich.edu 3333838Shsul@eecs.umich.edu // invalidate this entry 3345004Sgblack@eecs.umich.edu entry->valid = false; 3353838Shsul@eecs.umich.edu 3364428Ssaidi@eecs.umich.edu lookupTable.erase(i++); 3374428Ssaidi@eecs.umich.edu } else { 3384428Ssaidi@eecs.umich.edu ++i; 3393838Shsul@eecs.umich.edu } 3403838Shsul@eecs.umich.edu } 3413838Shsul@eecs.umich.edu} 3423838Shsul@eecs.umich.edu 3433838Shsul@eecs.umich.edu 3443838Shsul@eecs.umich.eduvoid 3453838Shsul@eecs.umich.eduTLB::serialize(ostream &os) 3463838Shsul@eecs.umich.edu{ 3473838Shsul@eecs.umich.edu SERIALIZE_SCALAR(size); 3483838Shsul@eecs.umich.edu SERIALIZE_SCALAR(nlu); 3493838Shsul@eecs.umich.edu 3503838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 3515004Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.Entry%d", name(), i)); 3523838Shsul@eecs.umich.edu table[i].serialize(os); 3533838Shsul@eecs.umich.edu } 3543838Shsul@eecs.umich.edu} 3553838Shsul@eecs.umich.edu 3563838Shsul@eecs.umich.eduvoid 3573838Shsul@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const string §ion) 3583838Shsul@eecs.umich.edu{ 3593838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(size); 3603838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(nlu); 3613838Shsul@eecs.umich.edu 3623838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 3635004Sgblack@eecs.umich.edu table[i].unserialize(cp, csprintf("%s.Entry%d", section, i)); 3643838Shsul@eecs.umich.edu if (table[i].valid) { 3653838Shsul@eecs.umich.edu lookupTable.insert(make_pair(table[i].tag, i)); 3663838Shsul@eecs.umich.edu } 3673838Shsul@eecs.umich.edu } 3683838Shsul@eecs.umich.edu} 3693838Shsul@eecs.umich.edu 3703838Shsul@eecs.umich.eduFault 3716022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 3723838Shsul@eecs.umich.edu{ 3734375Sgblack@eecs.umich.edu //If this is a pal pc, then set PHYSICAL 3748738Sgblack@eecs.umich.edu if (FullSystem && PcPAL(req->getPC())) 3755736Snate@binkert.org req->setFlags(Request::PHYSICAL); 3764375Sgblack@eecs.umich.edu 3773838Shsul@eecs.umich.edu if (PcPAL(req->getPC())) { 3783838Shsul@eecs.umich.edu // strip off PAL PC marker (lsb is 1) 3793838Shsul@eecs.umich.edu req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 3806022Sgblack@eecs.umich.edu fetch_hits++; 3813838Shsul@eecs.umich.edu return NoFault; 3823453Sgblack@eecs.umich.edu } 3833453Sgblack@eecs.umich.edu 3845736Snate@binkert.org if (req->getFlags() & Request::PHYSICAL) { 3853838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 3863838Shsul@eecs.umich.edu } else { 3873838Shsul@eecs.umich.edu // verify that this is a good virtual address 3883838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 3896022Sgblack@eecs.umich.edu fetch_acv++; 3903838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 3912SN/A } 3922SN/A 3933838Shsul@eecs.umich.edu 3943838Shsul@eecs.umich.edu // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 3953838Shsul@eecs.umich.edu // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 3966025Snate@binkert.org if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 3973838Shsul@eecs.umich.edu // only valid in kernel mode 3984172Ssaidi@eecs.umich.edu if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 3993838Shsul@eecs.umich.edu mode_kernel) { 4006022Sgblack@eecs.umich.edu fetch_acv++; 4012532SN/A return new ItbAcvFault(req->getVaddr()); 402555SN/A } 4032SN/A 4043838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 405551SN/A 4063838Shsul@eecs.umich.edu // sign extend the physical address properly 4073838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 4083838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 4093838Shsul@eecs.umich.edu else 4103838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 4113838Shsul@eecs.umich.edu } else { 4123838Shsul@eecs.umich.edu // not a physical address: need to look up pte 4134172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 4145004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 4153838Shsul@eecs.umich.edu asn); 4163838Shsul@eecs.umich.edu 4175004Sgblack@eecs.umich.edu if (!entry) { 4186022Sgblack@eecs.umich.edu fetch_misses++; 4193838Shsul@eecs.umich.edu return new ItbPageFault(req->getVaddr()); 4203838Shsul@eecs.umich.edu } 4213838Shsul@eecs.umich.edu 4225004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 4233838Shsul@eecs.umich.edu (VAddr(req->getVaddr()).offset() 4243838Shsul@eecs.umich.edu & ~3)); 4253838Shsul@eecs.umich.edu 4263838Shsul@eecs.umich.edu // check permissions for this access 4275004Sgblack@eecs.umich.edu if (!(entry->xre & 4284172Ssaidi@eecs.umich.edu (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 4293838Shsul@eecs.umich.edu // instruction access fault 4306022Sgblack@eecs.umich.edu fetch_acv++; 4313838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 4323838Shsul@eecs.umich.edu } 4333838Shsul@eecs.umich.edu 4346022Sgblack@eecs.umich.edu fetch_hits++; 4353838Shsul@eecs.umich.edu } 4363838Shsul@eecs.umich.edu } 4373838Shsul@eecs.umich.edu 4383838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 4398591Sgblack@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) { 4408591Sgblack@eecs.umich.edu return new MachineCheckFault(); 4418591Sgblack@eecs.umich.edu } 4423838Shsul@eecs.umich.edu 4435532Ssaidi@eecs.umich.edu return checkCacheability(req, true); 4443838Shsul@eecs.umich.edu 4453838Shsul@eecs.umich.edu} 4463838Shsul@eecs.umich.edu 4473838Shsul@eecs.umich.eduFault 4486022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 4493838Shsul@eecs.umich.edu{ 4503838Shsul@eecs.umich.edu mode_type mode = 4514172Ssaidi@eecs.umich.edu (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 4523838Shsul@eecs.umich.edu 4533838Shsul@eecs.umich.edu /** 4543838Shsul@eecs.umich.edu * Check for alignment faults 4553838Shsul@eecs.umich.edu */ 4563838Shsul@eecs.umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4576185Sksewell@umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(), 4583838Shsul@eecs.umich.edu req->getSize()); 4593838Shsul@eecs.umich.edu uint64_t flags = write ? MM_STAT_WR_MASK : 0; 4603838Shsul@eecs.umich.edu return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 4613838Shsul@eecs.umich.edu } 4623838Shsul@eecs.umich.edu 4638408Sksewell@umich.edu if (PcPAL(req->getPC())) { 4645736Snate@binkert.org mode = (req->getFlags() & Request::ALTMODE) ? 4653838Shsul@eecs.umich.edu (mode_type)ALT_MODE_AM( 4664172Ssaidi@eecs.umich.edu tc->readMiscRegNoEffect(IPR_ALT_MODE)) 4673838Shsul@eecs.umich.edu : mode_kernel; 4683838Shsul@eecs.umich.edu } 4693838Shsul@eecs.umich.edu 4705736Snate@binkert.org if (req->getFlags() & Request::PHYSICAL) { 4713838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 4723838Shsul@eecs.umich.edu } else { 4733838Shsul@eecs.umich.edu // verify that this is a good virtual address 4743838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 4753838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 4763838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 4773838Shsul@eecs.umich.edu MM_STAT_BAD_VA_MASK | 4783838Shsul@eecs.umich.edu MM_STAT_ACV_MASK; 4793838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 4803838Shsul@eecs.umich.edu } 4813838Shsul@eecs.umich.edu 4823838Shsul@eecs.umich.edu // Check for "superpage" mapping 4836025Snate@binkert.org if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 4843838Shsul@eecs.umich.edu // only valid in kernel mode 4854172Ssaidi@eecs.umich.edu if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 4863838Shsul@eecs.umich.edu mode_kernel) { 4873838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 4883838Shsul@eecs.umich.edu uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 4893838Shsul@eecs.umich.edu MM_STAT_ACV_MASK); 4905569Snate@binkert.org 4915569Snate@binkert.org return new DtbAcvFault(req->getVaddr(), req->getFlags(), 4925569Snate@binkert.org flags); 4933838Shsul@eecs.umich.edu } 4943838Shsul@eecs.umich.edu 4953838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 4963838Shsul@eecs.umich.edu 4973838Shsul@eecs.umich.edu // sign extend the physical address properly 4983838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 4993838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 5003838Shsul@eecs.umich.edu else 5013838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 5023838Shsul@eecs.umich.edu } else { 5033838Shsul@eecs.umich.edu if (write) 5043838Shsul@eecs.umich.edu write_accesses++; 5053838Shsul@eecs.umich.edu else 5063838Shsul@eecs.umich.edu read_accesses++; 5073838Shsul@eecs.umich.edu 5084172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 5093838Shsul@eecs.umich.edu 5103838Shsul@eecs.umich.edu // not a physical address: need to look up pte 5115004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn); 5123838Shsul@eecs.umich.edu 5135004Sgblack@eecs.umich.edu if (!entry) { 5143838Shsul@eecs.umich.edu // page fault 5153838Shsul@eecs.umich.edu if (write) { write_misses++; } else { read_misses++; } 5163838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5173838Shsul@eecs.umich.edu MM_STAT_DTB_MISS_MASK; 5185736Snate@binkert.org return (req->getFlags() & Request::VPTE) ? 5193838Shsul@eecs.umich.edu (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 5203838Shsul@eecs.umich.edu flags)) : 5213838Shsul@eecs.umich.edu (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 5223838Shsul@eecs.umich.edu flags)); 5233838Shsul@eecs.umich.edu } 5243838Shsul@eecs.umich.edu 5255004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 5263838Shsul@eecs.umich.edu VAddr(req->getVaddr()).offset()); 5273838Shsul@eecs.umich.edu 5283838Shsul@eecs.umich.edu if (write) { 5295004Sgblack@eecs.umich.edu if (!(entry->xwe & MODE2MASK(mode))) { 5303838Shsul@eecs.umich.edu // declare the instruction access fault 5313838Shsul@eecs.umich.edu write_acv++; 5323838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5333838Shsul@eecs.umich.edu MM_STAT_ACV_MASK | 5345004Sgblack@eecs.umich.edu (entry->fonw ? MM_STAT_FONW_MASK : 0); 5355569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 5365569Snate@binkert.org flags); 5373838Shsul@eecs.umich.edu } 5385004Sgblack@eecs.umich.edu if (entry->fonw) { 5393838Shsul@eecs.umich.edu write_acv++; 5405569Snate@binkert.org uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK; 5415569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 5425569Snate@binkert.org flags); 5433838Shsul@eecs.umich.edu } 5443453Sgblack@eecs.umich.edu } else { 5455004Sgblack@eecs.umich.edu if (!(entry->xre & MODE2MASK(mode))) { 5463838Shsul@eecs.umich.edu read_acv++; 5473838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_ACV_MASK | 5485004Sgblack@eecs.umich.edu (entry->fonr ? MM_STAT_FONR_MASK : 0); 5495569Snate@binkert.org return new DtbAcvFault(req->getVaddr(), req->getFlags(), 5505569Snate@binkert.org flags); 5513453Sgblack@eecs.umich.edu } 5525004Sgblack@eecs.umich.edu if (entry->fonr) { 5533838Shsul@eecs.umich.edu read_acv++; 5543838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_FONR_MASK; 5555569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 5565569Snate@binkert.org flags); 5573453Sgblack@eecs.umich.edu } 5582SN/A } 5592SN/A } 560551SN/A 5613838Shsul@eecs.umich.edu if (write) 5623838Shsul@eecs.umich.edu write_hits++; 5633838Shsul@eecs.umich.edu else 5643838Shsul@eecs.umich.edu read_hits++; 5652SN/A } 5662SN/A 5673838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 5688591Sgblack@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) { 5698591Sgblack@eecs.umich.edu return new MachineCheckFault(); 5708591Sgblack@eecs.umich.edu } 571551SN/A 5723838Shsul@eecs.umich.edu return checkCacheability(req); 5733838Shsul@eecs.umich.edu} 5743453Sgblack@eecs.umich.edu 5755004Sgblack@eecs.umich.eduTlbEntry & 5763838Shsul@eecs.umich.eduTLB::index(bool advance) 5773838Shsul@eecs.umich.edu{ 5785004Sgblack@eecs.umich.edu TlbEntry *entry = &table[nlu]; 5793453Sgblack@eecs.umich.edu 5803838Shsul@eecs.umich.edu if (advance) 5813838Shsul@eecs.umich.edu nextnlu(); 5823453Sgblack@eecs.umich.edu 5835004Sgblack@eecs.umich.edu return *entry; 5843838Shsul@eecs.umich.edu} 5853453Sgblack@eecs.umich.edu 5866022Sgblack@eecs.umich.eduFault 5876023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 5886022Sgblack@eecs.umich.edu{ 5896023Snate@binkert.org if (mode == Execute) 5906022Sgblack@eecs.umich.edu return translateInst(req, tc); 5916022Sgblack@eecs.umich.edu else 5926023Snate@binkert.org return translateData(req, tc, mode == Write); 5936022Sgblack@eecs.umich.edu} 5946022Sgblack@eecs.umich.edu 5956022Sgblack@eecs.umich.eduvoid 5966022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 5976023Snate@binkert.org Translation *translation, Mode mode) 5986022Sgblack@eecs.umich.edu{ 5996022Sgblack@eecs.umich.edu assert(translation); 6006023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 6016022Sgblack@eecs.umich.edu} 6026022Sgblack@eecs.umich.edu 6038888Sgeoffrey.blake@arm.comFault 6048888Sgeoffrey.blake@arm.comTLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 6058888Sgeoffrey.blake@arm.com{ 6068888Sgeoffrey.blake@arm.com panic("Not implemented\n"); 6078888Sgeoffrey.blake@arm.com return NoFault; 6088888Sgeoffrey.blake@arm.com} 6098888Sgeoffrey.blake@arm.com 6109738Sandreas@sandberg.pp.seFault 6119738Sandreas@sandberg.pp.seTLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 6129738Sandreas@sandberg.pp.se{ 6139738Sandreas@sandberg.pp.se return NoFault; 6149738Sandreas@sandberg.pp.se} 6159738Sandreas@sandberg.pp.se 6167811Ssteve.reinhardt@amd.com} // namespace AlphaISA 6174088Sbinkertn@umich.edu 6186022Sgblack@eecs.umich.eduAlphaISA::TLB * 6196022Sgblack@eecs.umich.eduAlphaTLBParams::create() 6203838Shsul@eecs.umich.edu{ 6216022Sgblack@eecs.umich.edu return new AlphaISA::TLB(this); 6223838Shsul@eecs.umich.edu} 623