tlb.cc revision 8232
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Andrew Schultz 312SN/A */ 322SN/A 332SN/A#include <string> 342SN/A#include <vector> 352SN/A 368229Snate@binkert.org#include "arch/alpha/faults.hh" 372984Sgblack@eecs.umich.edu#include "arch/alpha/pagetable.hh" 382171SN/A#include "arch/alpha/tlb.hh" 39146SN/A#include "base/inifile.hh" 40146SN/A#include "base/str.hh" 41146SN/A#include "base/trace.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 438232Snate@binkert.org#include "debug/TLB.hh" 442SN/A 452SN/Ausing namespace std; 462SN/A 474088Sbinkertn@umich.edunamespace AlphaISA { 485569Snate@binkert.org 493838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 503838Shsul@eecs.umich.edu// 513838Shsul@eecs.umich.edu// Alpha TLB 523838Shsul@eecs.umich.edu// 535569Snate@binkert.org 54860SN/A#ifdef DEBUG 553838Shsul@eecs.umich.edubool uncacheBit39 = false; 563838Shsul@eecs.umich.edubool uncacheBit40 = false; 57860SN/A#endif 58860SN/A 595569Snate@binkert.org#define MODE2MASK(X) (1 << (X)) 601147SN/A 615034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 625358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), nlu(0) 633838Shsul@eecs.umich.edu{ 645004Sgblack@eecs.umich.edu table = new TlbEntry[size]; 655004Sgblack@eecs.umich.edu memset(table, 0, sizeof(TlbEntry[size])); 664957Sacolyte@umich.edu flushCache(); 673838Shsul@eecs.umich.edu} 682SN/A 693838Shsul@eecs.umich.eduTLB::~TLB() 703838Shsul@eecs.umich.edu{ 713838Shsul@eecs.umich.edu if (table) 723838Shsul@eecs.umich.edu delete [] table; 733838Shsul@eecs.umich.edu} 742SN/A 756022Sgblack@eecs.umich.eduvoid 766022Sgblack@eecs.umich.eduTLB::regStats() 776022Sgblack@eecs.umich.edu{ 786022Sgblack@eecs.umich.edu fetch_hits 796022Sgblack@eecs.umich.edu .name(name() + ".fetch_hits") 806022Sgblack@eecs.umich.edu .desc("ITB hits"); 816022Sgblack@eecs.umich.edu fetch_misses 826022Sgblack@eecs.umich.edu .name(name() + ".fetch_misses") 836022Sgblack@eecs.umich.edu .desc("ITB misses"); 846022Sgblack@eecs.umich.edu fetch_acv 856022Sgblack@eecs.umich.edu .name(name() + ".fetch_acv") 866022Sgblack@eecs.umich.edu .desc("ITB acv"); 876022Sgblack@eecs.umich.edu fetch_accesses 886022Sgblack@eecs.umich.edu .name(name() + ".fetch_accesses") 896022Sgblack@eecs.umich.edu .desc("ITB accesses"); 906022Sgblack@eecs.umich.edu 916022Sgblack@eecs.umich.edu fetch_accesses = fetch_hits + fetch_misses; 926022Sgblack@eecs.umich.edu 936022Sgblack@eecs.umich.edu read_hits 946022Sgblack@eecs.umich.edu .name(name() + ".read_hits") 956022Sgblack@eecs.umich.edu .desc("DTB read hits") 966022Sgblack@eecs.umich.edu ; 976022Sgblack@eecs.umich.edu 986022Sgblack@eecs.umich.edu read_misses 996022Sgblack@eecs.umich.edu .name(name() + ".read_misses") 1006022Sgblack@eecs.umich.edu .desc("DTB read misses") 1016022Sgblack@eecs.umich.edu ; 1026022Sgblack@eecs.umich.edu 1036022Sgblack@eecs.umich.edu read_acv 1046022Sgblack@eecs.umich.edu .name(name() + ".read_acv") 1056022Sgblack@eecs.umich.edu .desc("DTB read access violations") 1066022Sgblack@eecs.umich.edu ; 1076022Sgblack@eecs.umich.edu 1086022Sgblack@eecs.umich.edu read_accesses 1096022Sgblack@eecs.umich.edu .name(name() + ".read_accesses") 1106022Sgblack@eecs.umich.edu .desc("DTB read accesses") 1116022Sgblack@eecs.umich.edu ; 1126022Sgblack@eecs.umich.edu 1136022Sgblack@eecs.umich.edu write_hits 1146022Sgblack@eecs.umich.edu .name(name() + ".write_hits") 1156022Sgblack@eecs.umich.edu .desc("DTB write hits") 1166022Sgblack@eecs.umich.edu ; 1176022Sgblack@eecs.umich.edu 1186022Sgblack@eecs.umich.edu write_misses 1196022Sgblack@eecs.umich.edu .name(name() + ".write_misses") 1206022Sgblack@eecs.umich.edu .desc("DTB write misses") 1216022Sgblack@eecs.umich.edu ; 1226022Sgblack@eecs.umich.edu 1236022Sgblack@eecs.umich.edu write_acv 1246022Sgblack@eecs.umich.edu .name(name() + ".write_acv") 1256022Sgblack@eecs.umich.edu .desc("DTB write access violations") 1266022Sgblack@eecs.umich.edu ; 1276022Sgblack@eecs.umich.edu 1286022Sgblack@eecs.umich.edu write_accesses 1296022Sgblack@eecs.umich.edu .name(name() + ".write_accesses") 1306022Sgblack@eecs.umich.edu .desc("DTB write accesses") 1316022Sgblack@eecs.umich.edu ; 1326022Sgblack@eecs.umich.edu 1336022Sgblack@eecs.umich.edu data_hits 1346022Sgblack@eecs.umich.edu .name(name() + ".data_hits") 1356022Sgblack@eecs.umich.edu .desc("DTB hits") 1366022Sgblack@eecs.umich.edu ; 1376022Sgblack@eecs.umich.edu 1386022Sgblack@eecs.umich.edu data_misses 1396022Sgblack@eecs.umich.edu .name(name() + ".data_misses") 1406022Sgblack@eecs.umich.edu .desc("DTB misses") 1416022Sgblack@eecs.umich.edu ; 1426022Sgblack@eecs.umich.edu 1436022Sgblack@eecs.umich.edu data_acv 1446022Sgblack@eecs.umich.edu .name(name() + ".data_acv") 1456022Sgblack@eecs.umich.edu .desc("DTB access violations") 1466022Sgblack@eecs.umich.edu ; 1476022Sgblack@eecs.umich.edu 1486022Sgblack@eecs.umich.edu data_accesses 1496022Sgblack@eecs.umich.edu .name(name() + ".data_accesses") 1506022Sgblack@eecs.umich.edu .desc("DTB accesses") 1516022Sgblack@eecs.umich.edu ; 1526022Sgblack@eecs.umich.edu 1536022Sgblack@eecs.umich.edu data_hits = read_hits + write_hits; 1546022Sgblack@eecs.umich.edu data_misses = read_misses + write_misses; 1556022Sgblack@eecs.umich.edu data_acv = read_acv + write_acv; 1566022Sgblack@eecs.umich.edu data_accesses = read_accesses + write_accesses; 1576022Sgblack@eecs.umich.edu} 1586022Sgblack@eecs.umich.edu 1593838Shsul@eecs.umich.edu// look up an entry in the TLB 1605004Sgblack@eecs.umich.eduTlbEntry * 1614967Sacolyte@umich.eduTLB::lookup(Addr vpn, uint8_t asn) 1623838Shsul@eecs.umich.edu{ 1633838Shsul@eecs.umich.edu // assume not found... 1645004Sgblack@eecs.umich.edu TlbEntry *retval = NULL; 1652SN/A 1665004Sgblack@eecs.umich.edu if (EntryCache[0]) { 1675004Sgblack@eecs.umich.edu if (vpn == EntryCache[0]->tag && 1685004Sgblack@eecs.umich.edu (EntryCache[0]->asma || EntryCache[0]->asn == asn)) 1695004Sgblack@eecs.umich.edu retval = EntryCache[0]; 1705004Sgblack@eecs.umich.edu else if (EntryCache[1]) { 1715004Sgblack@eecs.umich.edu if (vpn == EntryCache[1]->tag && 1725004Sgblack@eecs.umich.edu (EntryCache[1]->asma || EntryCache[1]->asn == asn)) 1735004Sgblack@eecs.umich.edu retval = EntryCache[1]; 1745004Sgblack@eecs.umich.edu else if (EntryCache[2] && vpn == EntryCache[2]->tag && 1755004Sgblack@eecs.umich.edu (EntryCache[2]->asma || EntryCache[2]->asn == asn)) 1765004Sgblack@eecs.umich.edu retval = EntryCache[2]; 1774962Sacolyte@umich.edu } 1784962Sacolyte@umich.edu } 1794962Sacolyte@umich.edu 1804967Sacolyte@umich.edu if (retval == NULL) { 1814957Sacolyte@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 1824957Sacolyte@umich.edu if (i != lookupTable.end()) { 1834957Sacolyte@umich.edu while (i->first == vpn) { 1844957Sacolyte@umich.edu int index = i->second; 1855004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 1865004Sgblack@eecs.umich.edu assert(entry->valid); 1875004Sgblack@eecs.umich.edu if (vpn == entry->tag && (entry->asma || entry->asn == asn)) { 1885004Sgblack@eecs.umich.edu retval = updateCache(entry); 1894957Sacolyte@umich.edu break; 1904957Sacolyte@umich.edu } 1914957Sacolyte@umich.edu 1924957Sacolyte@umich.edu ++i; 1931413SN/A } 1941413SN/A } 1952SN/A } 1962SN/A 1973838Shsul@eecs.umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1983838Shsul@eecs.umich.edu retval ? "hit" : "miss", retval ? retval->ppn : 0); 1993838Shsul@eecs.umich.edu return retval; 2003838Shsul@eecs.umich.edu} 2012SN/A 2023838Shsul@eecs.umich.eduFault 2035532Ssaidi@eecs.umich.eduTLB::checkCacheability(RequestPtr &req, bool itb) 2043838Shsul@eecs.umich.edu{ 2055569Snate@binkert.org // in Alpha, cacheability is controlled by upper-level bits of the 2065569Snate@binkert.org // physical address 2073838Shsul@eecs.umich.edu 2085569Snate@binkert.org /* 2095569Snate@binkert.org * We support having the uncacheable bit in either bit 39 or bit 2105569Snate@binkert.org * 40. The Turbolaser platform (and EV5) support having the bit 2115569Snate@binkert.org * in 39, but Tsunami (which Linux assumes uses an EV6) generates 2125569Snate@binkert.org * accesses with the bit in 40. So we must check for both, but we 2135569Snate@binkert.org * have debug flags to catch a weird case where both are used, 2145569Snate@binkert.org * which shouldn't happen. 2155569Snate@binkert.org */ 2163838Shsul@eecs.umich.edu 2173838Shsul@eecs.umich.edu 2186025Snate@binkert.org if (req->getPaddr() & PAddrUncachedBit43) { 2193838Shsul@eecs.umich.edu // IPR memory space not implemented 2203838Shsul@eecs.umich.edu if (PAddrIprSpace(req->getPaddr())) { 2213838Shsul@eecs.umich.edu return new UnimpFault("IPR memory space not implemented!"); 2223838Shsul@eecs.umich.edu } else { 2233838Shsul@eecs.umich.edu // mark request as uncacheable 2245736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 2253838Shsul@eecs.umich.edu 2265569Snate@binkert.org // Clear bits 42:35 of the physical address (10-2 in 2275569Snate@binkert.org // Tsunami manual) 2283838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & PAddrUncachedMask); 229924SN/A } 2305532Ssaidi@eecs.umich.edu // We shouldn't be able to read from an uncachable address in Alpha as 2315532Ssaidi@eecs.umich.edu // we don't have a ROM and we don't want to try to fetch from a device 2325532Ssaidi@eecs.umich.edu // register as we destroy any data that is clear-on-read. 2335532Ssaidi@eecs.umich.edu if (req->isUncacheable() && itb) 2345532Ssaidi@eecs.umich.edu return new UnimpFault("CPU trying to fetch from uncached I/O"); 2355532Ssaidi@eecs.umich.edu 2362SN/A } 2373838Shsul@eecs.umich.edu return NoFault; 2383838Shsul@eecs.umich.edu} 2392SN/A 2402SN/A 2413838Shsul@eecs.umich.edu// insert a new TLB entry 2423838Shsul@eecs.umich.eduvoid 2435004Sgblack@eecs.umich.eduTLB::insert(Addr addr, TlbEntry &entry) 2443838Shsul@eecs.umich.edu{ 2454957Sacolyte@umich.edu flushCache(); 2463838Shsul@eecs.umich.edu VAddr vaddr = addr; 2473838Shsul@eecs.umich.edu if (table[nlu].valid) { 2483838Shsul@eecs.umich.edu Addr oldvpn = table[nlu].tag; 2493838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(oldvpn); 2503838Shsul@eecs.umich.edu 2513838Shsul@eecs.umich.edu if (i == lookupTable.end()) 2523838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 2533838Shsul@eecs.umich.edu 2543838Shsul@eecs.umich.edu int index; 2553838Shsul@eecs.umich.edu while ((index = i->second) != nlu) { 2563838Shsul@eecs.umich.edu if (table[index].tag != oldvpn) 2573838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 2583838Shsul@eecs.umich.edu 2593838Shsul@eecs.umich.edu ++i; 2603838Shsul@eecs.umich.edu } 2613838Shsul@eecs.umich.edu 2623838Shsul@eecs.umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 2633838Shsul@eecs.umich.edu 2643838Shsul@eecs.umich.edu lookupTable.erase(i); 2653838Shsul@eecs.umich.edu } 2663838Shsul@eecs.umich.edu 2675004Sgblack@eecs.umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn); 2683838Shsul@eecs.umich.edu 2695004Sgblack@eecs.umich.edu table[nlu] = entry; 2703838Shsul@eecs.umich.edu table[nlu].tag = vaddr.vpn(); 2713838Shsul@eecs.umich.edu table[nlu].valid = true; 2723838Shsul@eecs.umich.edu 2733838Shsul@eecs.umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 2743838Shsul@eecs.umich.edu nextnlu(); 2753838Shsul@eecs.umich.edu} 2763838Shsul@eecs.umich.edu 2773838Shsul@eecs.umich.eduvoid 2783838Shsul@eecs.umich.eduTLB::flushAll() 2793838Shsul@eecs.umich.edu{ 2803838Shsul@eecs.umich.edu DPRINTF(TLB, "flushAll\n"); 2815004Sgblack@eecs.umich.edu memset(table, 0, sizeof(TlbEntry[size])); 2824957Sacolyte@umich.edu flushCache(); 2833838Shsul@eecs.umich.edu lookupTable.clear(); 2843838Shsul@eecs.umich.edu nlu = 0; 2853838Shsul@eecs.umich.edu} 2863838Shsul@eecs.umich.edu 2873838Shsul@eecs.umich.eduvoid 2883838Shsul@eecs.umich.eduTLB::flushProcesses() 2893838Shsul@eecs.umich.edu{ 2904957Sacolyte@umich.edu flushCache(); 2913838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.begin(); 2923838Shsul@eecs.umich.edu PageTable::iterator end = lookupTable.end(); 2933838Shsul@eecs.umich.edu while (i != end) { 2943838Shsul@eecs.umich.edu int index = i->second; 2955004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 2965004Sgblack@eecs.umich.edu assert(entry->valid); 2973838Shsul@eecs.umich.edu 2983838Shsul@eecs.umich.edu // we can't increment i after we erase it, so save a copy and 2993838Shsul@eecs.umich.edu // increment it to get the next entry now 3003838Shsul@eecs.umich.edu PageTable::iterator cur = i; 3013838Shsul@eecs.umich.edu ++i; 3023838Shsul@eecs.umich.edu 3035004Sgblack@eecs.umich.edu if (!entry->asma) { 3045569Snate@binkert.org DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, 3055569Snate@binkert.org entry->tag, entry->ppn); 3065004Sgblack@eecs.umich.edu entry->valid = false; 3073838Shsul@eecs.umich.edu lookupTable.erase(cur); 3083453Sgblack@eecs.umich.edu } 3093453Sgblack@eecs.umich.edu } 3103838Shsul@eecs.umich.edu} 3112SN/A 3123838Shsul@eecs.umich.eduvoid 3133838Shsul@eecs.umich.eduTLB::flushAddr(Addr addr, uint8_t asn) 3143838Shsul@eecs.umich.edu{ 3154957Sacolyte@umich.edu flushCache(); 3163838Shsul@eecs.umich.edu VAddr vaddr = addr; 3172SN/A 3183838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(vaddr.vpn()); 3193838Shsul@eecs.umich.edu if (i == lookupTable.end()) 3203838Shsul@eecs.umich.edu return; 3212SN/A 3224428Ssaidi@eecs.umich.edu while (i != lookupTable.end() && i->first == vaddr.vpn()) { 3233838Shsul@eecs.umich.edu int index = i->second; 3245004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 3255004Sgblack@eecs.umich.edu assert(entry->valid); 3263453Sgblack@eecs.umich.edu 3275004Sgblack@eecs.umich.edu if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) { 3283838Shsul@eecs.umich.edu DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 3295004Sgblack@eecs.umich.edu entry->ppn); 3303453Sgblack@eecs.umich.edu 3313838Shsul@eecs.umich.edu // invalidate this entry 3325004Sgblack@eecs.umich.edu entry->valid = false; 3333838Shsul@eecs.umich.edu 3344428Ssaidi@eecs.umich.edu lookupTable.erase(i++); 3354428Ssaidi@eecs.umich.edu } else { 3364428Ssaidi@eecs.umich.edu ++i; 3373838Shsul@eecs.umich.edu } 3383838Shsul@eecs.umich.edu } 3393838Shsul@eecs.umich.edu} 3403838Shsul@eecs.umich.edu 3413838Shsul@eecs.umich.edu 3423838Shsul@eecs.umich.eduvoid 3433838Shsul@eecs.umich.eduTLB::serialize(ostream &os) 3443838Shsul@eecs.umich.edu{ 3453838Shsul@eecs.umich.edu SERIALIZE_SCALAR(size); 3463838Shsul@eecs.umich.edu SERIALIZE_SCALAR(nlu); 3473838Shsul@eecs.umich.edu 3483838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 3495004Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.Entry%d", name(), i)); 3503838Shsul@eecs.umich.edu table[i].serialize(os); 3513838Shsul@eecs.umich.edu } 3523838Shsul@eecs.umich.edu} 3533838Shsul@eecs.umich.edu 3543838Shsul@eecs.umich.eduvoid 3553838Shsul@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const string §ion) 3563838Shsul@eecs.umich.edu{ 3573838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(size); 3583838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(nlu); 3593838Shsul@eecs.umich.edu 3603838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 3615004Sgblack@eecs.umich.edu table[i].unserialize(cp, csprintf("%s.Entry%d", section, i)); 3623838Shsul@eecs.umich.edu if (table[i].valid) { 3633838Shsul@eecs.umich.edu lookupTable.insert(make_pair(table[i].tag, i)); 3643838Shsul@eecs.umich.edu } 3653838Shsul@eecs.umich.edu } 3663838Shsul@eecs.umich.edu} 3673838Shsul@eecs.umich.edu 3683838Shsul@eecs.umich.eduFault 3696022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 3703838Shsul@eecs.umich.edu{ 3714375Sgblack@eecs.umich.edu //If this is a pal pc, then set PHYSICAL 3725569Snate@binkert.org if (FULL_SYSTEM && PcPAL(req->getPC())) 3735736Snate@binkert.org req->setFlags(Request::PHYSICAL); 3744375Sgblack@eecs.umich.edu 3753838Shsul@eecs.umich.edu if (PcPAL(req->getPC())) { 3763838Shsul@eecs.umich.edu // strip off PAL PC marker (lsb is 1) 3773838Shsul@eecs.umich.edu req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 3786022Sgblack@eecs.umich.edu fetch_hits++; 3793838Shsul@eecs.umich.edu return NoFault; 3803453Sgblack@eecs.umich.edu } 3813453Sgblack@eecs.umich.edu 3825736Snate@binkert.org if (req->getFlags() & Request::PHYSICAL) { 3833838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 3843838Shsul@eecs.umich.edu } else { 3853838Shsul@eecs.umich.edu // verify that this is a good virtual address 3863838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 3876022Sgblack@eecs.umich.edu fetch_acv++; 3883838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 3892SN/A } 3902SN/A 3913838Shsul@eecs.umich.edu 3923838Shsul@eecs.umich.edu // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 3933838Shsul@eecs.umich.edu // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 3946025Snate@binkert.org if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 3953838Shsul@eecs.umich.edu // only valid in kernel mode 3964172Ssaidi@eecs.umich.edu if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 3973838Shsul@eecs.umich.edu mode_kernel) { 3986022Sgblack@eecs.umich.edu fetch_acv++; 3992532SN/A return new ItbAcvFault(req->getVaddr()); 400555SN/A } 4012SN/A 4023838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 403551SN/A 4043838Shsul@eecs.umich.edu // sign extend the physical address properly 4053838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 4063838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 4073838Shsul@eecs.umich.edu else 4083838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 4093838Shsul@eecs.umich.edu } else { 4103838Shsul@eecs.umich.edu // not a physical address: need to look up pte 4114172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 4125004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 4133838Shsul@eecs.umich.edu asn); 4143838Shsul@eecs.umich.edu 4155004Sgblack@eecs.umich.edu if (!entry) { 4166022Sgblack@eecs.umich.edu fetch_misses++; 4173838Shsul@eecs.umich.edu return new ItbPageFault(req->getVaddr()); 4183838Shsul@eecs.umich.edu } 4193838Shsul@eecs.umich.edu 4205004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 4213838Shsul@eecs.umich.edu (VAddr(req->getVaddr()).offset() 4223838Shsul@eecs.umich.edu & ~3)); 4233838Shsul@eecs.umich.edu 4243838Shsul@eecs.umich.edu // check permissions for this access 4255004Sgblack@eecs.umich.edu if (!(entry->xre & 4264172Ssaidi@eecs.umich.edu (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 4273838Shsul@eecs.umich.edu // instruction access fault 4286022Sgblack@eecs.umich.edu fetch_acv++; 4293838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 4303838Shsul@eecs.umich.edu } 4313838Shsul@eecs.umich.edu 4326022Sgblack@eecs.umich.edu fetch_hits++; 4333838Shsul@eecs.umich.edu } 4343838Shsul@eecs.umich.edu } 4353838Shsul@eecs.umich.edu 4363838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 4373838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 4383838Shsul@eecs.umich.edu return genMachineCheckFault(); 4393838Shsul@eecs.umich.edu 4405532Ssaidi@eecs.umich.edu return checkCacheability(req, true); 4413838Shsul@eecs.umich.edu 4423838Shsul@eecs.umich.edu} 4433838Shsul@eecs.umich.edu 4443838Shsul@eecs.umich.eduFault 4456022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 4463838Shsul@eecs.umich.edu{ 4473838Shsul@eecs.umich.edu mode_type mode = 4484172Ssaidi@eecs.umich.edu (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 4493838Shsul@eecs.umich.edu 4503838Shsul@eecs.umich.edu /** 4513838Shsul@eecs.umich.edu * Check for alignment faults 4523838Shsul@eecs.umich.edu */ 4533838Shsul@eecs.umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4546185Sksewell@umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(), 4553838Shsul@eecs.umich.edu req->getSize()); 4563838Shsul@eecs.umich.edu uint64_t flags = write ? MM_STAT_WR_MASK : 0; 4573838Shsul@eecs.umich.edu return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 4583838Shsul@eecs.umich.edu } 4593838Shsul@eecs.umich.edu 4607720Sgblack@eecs.umich.edu if (PcPAL(tc->pcState().pc())) { 4615736Snate@binkert.org mode = (req->getFlags() & Request::ALTMODE) ? 4623838Shsul@eecs.umich.edu (mode_type)ALT_MODE_AM( 4634172Ssaidi@eecs.umich.edu tc->readMiscRegNoEffect(IPR_ALT_MODE)) 4643838Shsul@eecs.umich.edu : mode_kernel; 4653838Shsul@eecs.umich.edu } 4663838Shsul@eecs.umich.edu 4675736Snate@binkert.org if (req->getFlags() & Request::PHYSICAL) { 4683838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 4693838Shsul@eecs.umich.edu } else { 4703838Shsul@eecs.umich.edu // verify that this is a good virtual address 4713838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 4723838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 4733838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 4743838Shsul@eecs.umich.edu MM_STAT_BAD_VA_MASK | 4753838Shsul@eecs.umich.edu MM_STAT_ACV_MASK; 4763838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 4773838Shsul@eecs.umich.edu } 4783838Shsul@eecs.umich.edu 4793838Shsul@eecs.umich.edu // Check for "superpage" mapping 4806025Snate@binkert.org if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { 4813838Shsul@eecs.umich.edu // only valid in kernel mode 4824172Ssaidi@eecs.umich.edu if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 4833838Shsul@eecs.umich.edu mode_kernel) { 4843838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 4853838Shsul@eecs.umich.edu uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 4863838Shsul@eecs.umich.edu MM_STAT_ACV_MASK); 4875569Snate@binkert.org 4885569Snate@binkert.org return new DtbAcvFault(req->getVaddr(), req->getFlags(), 4895569Snate@binkert.org flags); 4903838Shsul@eecs.umich.edu } 4913838Shsul@eecs.umich.edu 4923838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 4933838Shsul@eecs.umich.edu 4943838Shsul@eecs.umich.edu // sign extend the physical address properly 4953838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 4963838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 4973838Shsul@eecs.umich.edu else 4983838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 4993838Shsul@eecs.umich.edu } else { 5003838Shsul@eecs.umich.edu if (write) 5013838Shsul@eecs.umich.edu write_accesses++; 5023838Shsul@eecs.umich.edu else 5033838Shsul@eecs.umich.edu read_accesses++; 5043838Shsul@eecs.umich.edu 5054172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 5063838Shsul@eecs.umich.edu 5073838Shsul@eecs.umich.edu // not a physical address: need to look up pte 5085004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn); 5093838Shsul@eecs.umich.edu 5105004Sgblack@eecs.umich.edu if (!entry) { 5113838Shsul@eecs.umich.edu // page fault 5123838Shsul@eecs.umich.edu if (write) { write_misses++; } else { read_misses++; } 5133838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5143838Shsul@eecs.umich.edu MM_STAT_DTB_MISS_MASK; 5155736Snate@binkert.org return (req->getFlags() & Request::VPTE) ? 5163838Shsul@eecs.umich.edu (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 5173838Shsul@eecs.umich.edu flags)) : 5183838Shsul@eecs.umich.edu (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 5193838Shsul@eecs.umich.edu flags)); 5203838Shsul@eecs.umich.edu } 5213838Shsul@eecs.umich.edu 5225004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 5233838Shsul@eecs.umich.edu VAddr(req->getVaddr()).offset()); 5243838Shsul@eecs.umich.edu 5253838Shsul@eecs.umich.edu if (write) { 5265004Sgblack@eecs.umich.edu if (!(entry->xwe & MODE2MASK(mode))) { 5273838Shsul@eecs.umich.edu // declare the instruction access fault 5283838Shsul@eecs.umich.edu write_acv++; 5293838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5303838Shsul@eecs.umich.edu MM_STAT_ACV_MASK | 5315004Sgblack@eecs.umich.edu (entry->fonw ? MM_STAT_FONW_MASK : 0); 5325569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 5335569Snate@binkert.org flags); 5343838Shsul@eecs.umich.edu } 5355004Sgblack@eecs.umich.edu if (entry->fonw) { 5363838Shsul@eecs.umich.edu write_acv++; 5375569Snate@binkert.org uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK; 5385569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 5395569Snate@binkert.org flags); 5403838Shsul@eecs.umich.edu } 5413453Sgblack@eecs.umich.edu } else { 5425004Sgblack@eecs.umich.edu if (!(entry->xre & MODE2MASK(mode))) { 5433838Shsul@eecs.umich.edu read_acv++; 5443838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_ACV_MASK | 5455004Sgblack@eecs.umich.edu (entry->fonr ? MM_STAT_FONR_MASK : 0); 5465569Snate@binkert.org return new DtbAcvFault(req->getVaddr(), req->getFlags(), 5475569Snate@binkert.org flags); 5483453Sgblack@eecs.umich.edu } 5495004Sgblack@eecs.umich.edu if (entry->fonr) { 5503838Shsul@eecs.umich.edu read_acv++; 5513838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_FONR_MASK; 5525569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 5535569Snate@binkert.org flags); 5543453Sgblack@eecs.umich.edu } 5552SN/A } 5562SN/A } 557551SN/A 5583838Shsul@eecs.umich.edu if (write) 5593838Shsul@eecs.umich.edu write_hits++; 5603838Shsul@eecs.umich.edu else 5613838Shsul@eecs.umich.edu read_hits++; 5622SN/A } 5632SN/A 5643838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 5653838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 5663838Shsul@eecs.umich.edu return genMachineCheckFault(); 567551SN/A 5683838Shsul@eecs.umich.edu return checkCacheability(req); 5693838Shsul@eecs.umich.edu} 5703453Sgblack@eecs.umich.edu 5715004Sgblack@eecs.umich.eduTlbEntry & 5723838Shsul@eecs.umich.eduTLB::index(bool advance) 5733838Shsul@eecs.umich.edu{ 5745004Sgblack@eecs.umich.edu TlbEntry *entry = &table[nlu]; 5753453Sgblack@eecs.umich.edu 5763838Shsul@eecs.umich.edu if (advance) 5773838Shsul@eecs.umich.edu nextnlu(); 5783453Sgblack@eecs.umich.edu 5795004Sgblack@eecs.umich.edu return *entry; 5803838Shsul@eecs.umich.edu} 5813453Sgblack@eecs.umich.edu 5826022Sgblack@eecs.umich.eduFault 5836023Snate@binkert.orgTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 5846022Sgblack@eecs.umich.edu{ 5856023Snate@binkert.org if (mode == Execute) 5866022Sgblack@eecs.umich.edu return translateInst(req, tc); 5876022Sgblack@eecs.umich.edu else 5886023Snate@binkert.org return translateData(req, tc, mode == Write); 5896022Sgblack@eecs.umich.edu} 5906022Sgblack@eecs.umich.edu 5916022Sgblack@eecs.umich.eduvoid 5926022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 5936023Snate@binkert.org Translation *translation, Mode mode) 5946022Sgblack@eecs.umich.edu{ 5956022Sgblack@eecs.umich.edu assert(translation); 5966023Snate@binkert.org translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 5976022Sgblack@eecs.umich.edu} 5986022Sgblack@eecs.umich.edu 5997811Ssteve.reinhardt@amd.com} // namespace AlphaISA 6004088Sbinkertn@umich.edu 6016022Sgblack@eecs.umich.eduAlphaISA::TLB * 6026022Sgblack@eecs.umich.eduAlphaTLBParams::create() 6033838Shsul@eecs.umich.edu{ 6046022Sgblack@eecs.umich.edu return new AlphaISA::TLB(this); 6053838Shsul@eecs.umich.edu} 606