tlb.cc revision 6022
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Andrew Schultz 312SN/A */ 322SN/A 332SN/A#include <string> 342SN/A#include <vector> 352SN/A 362984Sgblack@eecs.umich.edu#include "arch/alpha/pagetable.hh" 372171SN/A#include "arch/alpha/tlb.hh" 382984Sgblack@eecs.umich.edu#include "arch/alpha/faults.hh" 39146SN/A#include "base/inifile.hh" 40146SN/A#include "base/str.hh" 41146SN/A#include "base/trace.hh" 421858SN/A#include "config/alpha_tlaser.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 442SN/A 452SN/Ausing namespace std; 462SN/A 474088Sbinkertn@umich.edunamespace AlphaISA { 485569Snate@binkert.org 493838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 503838Shsul@eecs.umich.edu// 513838Shsul@eecs.umich.edu// Alpha TLB 523838Shsul@eecs.umich.edu// 535569Snate@binkert.org 54860SN/A#ifdef DEBUG 553838Shsul@eecs.umich.edubool uncacheBit39 = false; 563838Shsul@eecs.umich.edubool uncacheBit40 = false; 57860SN/A#endif 58860SN/A 595569Snate@binkert.org#define MODE2MASK(X) (1 << (X)) 601147SN/A 615034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 625358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), nlu(0) 633838Shsul@eecs.umich.edu{ 645004Sgblack@eecs.umich.edu table = new TlbEntry[size]; 655004Sgblack@eecs.umich.edu memset(table, 0, sizeof(TlbEntry[size])); 664957Sacolyte@umich.edu flushCache(); 673838Shsul@eecs.umich.edu} 682SN/A 693838Shsul@eecs.umich.eduTLB::~TLB() 703838Shsul@eecs.umich.edu{ 713838Shsul@eecs.umich.edu if (table) 723838Shsul@eecs.umich.edu delete [] table; 733838Shsul@eecs.umich.edu} 742SN/A 756022Sgblack@eecs.umich.eduvoid 766022Sgblack@eecs.umich.eduTLB::regStats() 776022Sgblack@eecs.umich.edu{ 786022Sgblack@eecs.umich.edu fetch_hits 796022Sgblack@eecs.umich.edu .name(name() + ".fetch_hits") 806022Sgblack@eecs.umich.edu .desc("ITB hits"); 816022Sgblack@eecs.umich.edu fetch_misses 826022Sgblack@eecs.umich.edu .name(name() + ".fetch_misses") 836022Sgblack@eecs.umich.edu .desc("ITB misses"); 846022Sgblack@eecs.umich.edu fetch_acv 856022Sgblack@eecs.umich.edu .name(name() + ".fetch_acv") 866022Sgblack@eecs.umich.edu .desc("ITB acv"); 876022Sgblack@eecs.umich.edu fetch_accesses 886022Sgblack@eecs.umich.edu .name(name() + ".fetch_accesses") 896022Sgblack@eecs.umich.edu .desc("ITB accesses"); 906022Sgblack@eecs.umich.edu 916022Sgblack@eecs.umich.edu fetch_accesses = fetch_hits + fetch_misses; 926022Sgblack@eecs.umich.edu 936022Sgblack@eecs.umich.edu read_hits 946022Sgblack@eecs.umich.edu .name(name() + ".read_hits") 956022Sgblack@eecs.umich.edu .desc("DTB read hits") 966022Sgblack@eecs.umich.edu ; 976022Sgblack@eecs.umich.edu 986022Sgblack@eecs.umich.edu read_misses 996022Sgblack@eecs.umich.edu .name(name() + ".read_misses") 1006022Sgblack@eecs.umich.edu .desc("DTB read misses") 1016022Sgblack@eecs.umich.edu ; 1026022Sgblack@eecs.umich.edu 1036022Sgblack@eecs.umich.edu read_acv 1046022Sgblack@eecs.umich.edu .name(name() + ".read_acv") 1056022Sgblack@eecs.umich.edu .desc("DTB read access violations") 1066022Sgblack@eecs.umich.edu ; 1076022Sgblack@eecs.umich.edu 1086022Sgblack@eecs.umich.edu read_accesses 1096022Sgblack@eecs.umich.edu .name(name() + ".read_accesses") 1106022Sgblack@eecs.umich.edu .desc("DTB read accesses") 1116022Sgblack@eecs.umich.edu ; 1126022Sgblack@eecs.umich.edu 1136022Sgblack@eecs.umich.edu write_hits 1146022Sgblack@eecs.umich.edu .name(name() + ".write_hits") 1156022Sgblack@eecs.umich.edu .desc("DTB write hits") 1166022Sgblack@eecs.umich.edu ; 1176022Sgblack@eecs.umich.edu 1186022Sgblack@eecs.umich.edu write_misses 1196022Sgblack@eecs.umich.edu .name(name() + ".write_misses") 1206022Sgblack@eecs.umich.edu .desc("DTB write misses") 1216022Sgblack@eecs.umich.edu ; 1226022Sgblack@eecs.umich.edu 1236022Sgblack@eecs.umich.edu write_acv 1246022Sgblack@eecs.umich.edu .name(name() + ".write_acv") 1256022Sgblack@eecs.umich.edu .desc("DTB write access violations") 1266022Sgblack@eecs.umich.edu ; 1276022Sgblack@eecs.umich.edu 1286022Sgblack@eecs.umich.edu write_accesses 1296022Sgblack@eecs.umich.edu .name(name() + ".write_accesses") 1306022Sgblack@eecs.umich.edu .desc("DTB write accesses") 1316022Sgblack@eecs.umich.edu ; 1326022Sgblack@eecs.umich.edu 1336022Sgblack@eecs.umich.edu data_hits 1346022Sgblack@eecs.umich.edu .name(name() + ".data_hits") 1356022Sgblack@eecs.umich.edu .desc("DTB hits") 1366022Sgblack@eecs.umich.edu ; 1376022Sgblack@eecs.umich.edu 1386022Sgblack@eecs.umich.edu data_misses 1396022Sgblack@eecs.umich.edu .name(name() + ".data_misses") 1406022Sgblack@eecs.umich.edu .desc("DTB misses") 1416022Sgblack@eecs.umich.edu ; 1426022Sgblack@eecs.umich.edu 1436022Sgblack@eecs.umich.edu data_acv 1446022Sgblack@eecs.umich.edu .name(name() + ".data_acv") 1456022Sgblack@eecs.umich.edu .desc("DTB access violations") 1466022Sgblack@eecs.umich.edu ; 1476022Sgblack@eecs.umich.edu 1486022Sgblack@eecs.umich.edu data_accesses 1496022Sgblack@eecs.umich.edu .name(name() + ".data_accesses") 1506022Sgblack@eecs.umich.edu .desc("DTB accesses") 1516022Sgblack@eecs.umich.edu ; 1526022Sgblack@eecs.umich.edu 1536022Sgblack@eecs.umich.edu data_hits = read_hits + write_hits; 1546022Sgblack@eecs.umich.edu data_misses = read_misses + write_misses; 1556022Sgblack@eecs.umich.edu data_acv = read_acv + write_acv; 1566022Sgblack@eecs.umich.edu data_accesses = read_accesses + write_accesses; 1576022Sgblack@eecs.umich.edu} 1586022Sgblack@eecs.umich.edu 1593838Shsul@eecs.umich.edu// look up an entry in the TLB 1605004Sgblack@eecs.umich.eduTlbEntry * 1614967Sacolyte@umich.eduTLB::lookup(Addr vpn, uint8_t asn) 1623838Shsul@eecs.umich.edu{ 1633838Shsul@eecs.umich.edu // assume not found... 1645004Sgblack@eecs.umich.edu TlbEntry *retval = NULL; 1652SN/A 1665004Sgblack@eecs.umich.edu if (EntryCache[0]) { 1675004Sgblack@eecs.umich.edu if (vpn == EntryCache[0]->tag && 1685004Sgblack@eecs.umich.edu (EntryCache[0]->asma || EntryCache[0]->asn == asn)) 1695004Sgblack@eecs.umich.edu retval = EntryCache[0]; 1705004Sgblack@eecs.umich.edu else if (EntryCache[1]) { 1715004Sgblack@eecs.umich.edu if (vpn == EntryCache[1]->tag && 1725004Sgblack@eecs.umich.edu (EntryCache[1]->asma || EntryCache[1]->asn == asn)) 1735004Sgblack@eecs.umich.edu retval = EntryCache[1]; 1745004Sgblack@eecs.umich.edu else if (EntryCache[2] && vpn == EntryCache[2]->tag && 1755004Sgblack@eecs.umich.edu (EntryCache[2]->asma || EntryCache[2]->asn == asn)) 1765004Sgblack@eecs.umich.edu retval = EntryCache[2]; 1774962Sacolyte@umich.edu } 1784962Sacolyte@umich.edu } 1794962Sacolyte@umich.edu 1804967Sacolyte@umich.edu if (retval == NULL) { 1814957Sacolyte@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 1824957Sacolyte@umich.edu if (i != lookupTable.end()) { 1834957Sacolyte@umich.edu while (i->first == vpn) { 1844957Sacolyte@umich.edu int index = i->second; 1855004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 1865004Sgblack@eecs.umich.edu assert(entry->valid); 1875004Sgblack@eecs.umich.edu if (vpn == entry->tag && (entry->asma || entry->asn == asn)) { 1885004Sgblack@eecs.umich.edu retval = updateCache(entry); 1894957Sacolyte@umich.edu break; 1904957Sacolyte@umich.edu } 1914957Sacolyte@umich.edu 1924957Sacolyte@umich.edu ++i; 1931413SN/A } 1941413SN/A } 1952SN/A } 1962SN/A 1973838Shsul@eecs.umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1983838Shsul@eecs.umich.edu retval ? "hit" : "miss", retval ? retval->ppn : 0); 1993838Shsul@eecs.umich.edu return retval; 2003838Shsul@eecs.umich.edu} 2012SN/A 2023838Shsul@eecs.umich.eduFault 2035532Ssaidi@eecs.umich.eduTLB::checkCacheability(RequestPtr &req, bool itb) 2043838Shsul@eecs.umich.edu{ 2055569Snate@binkert.org // in Alpha, cacheability is controlled by upper-level bits of the 2065569Snate@binkert.org // physical address 2073838Shsul@eecs.umich.edu 2085569Snate@binkert.org /* 2095569Snate@binkert.org * We support having the uncacheable bit in either bit 39 or bit 2105569Snate@binkert.org * 40. The Turbolaser platform (and EV5) support having the bit 2115569Snate@binkert.org * in 39, but Tsunami (which Linux assumes uses an EV6) generates 2125569Snate@binkert.org * accesses with the bit in 40. So we must check for both, but we 2135569Snate@binkert.org * have debug flags to catch a weird case where both are used, 2145569Snate@binkert.org * which shouldn't happen. 2155569Snate@binkert.org */ 2163838Shsul@eecs.umich.edu 2173838Shsul@eecs.umich.edu 2183838Shsul@eecs.umich.edu#if ALPHA_TLASER 2194088Sbinkertn@umich.edu if (req->getPaddr() & PAddrUncachedBit39) 2203838Shsul@eecs.umich.edu#else 2214088Sbinkertn@umich.edu if (req->getPaddr() & PAddrUncachedBit43) 2223838Shsul@eecs.umich.edu#endif 2234088Sbinkertn@umich.edu { 2243838Shsul@eecs.umich.edu // IPR memory space not implemented 2253838Shsul@eecs.umich.edu if (PAddrIprSpace(req->getPaddr())) { 2263838Shsul@eecs.umich.edu return new UnimpFault("IPR memory space not implemented!"); 2273838Shsul@eecs.umich.edu } else { 2283838Shsul@eecs.umich.edu // mark request as uncacheable 2295736Snate@binkert.org req->setFlags(Request::UNCACHEABLE); 2303838Shsul@eecs.umich.edu 2313838Shsul@eecs.umich.edu#if !ALPHA_TLASER 2325569Snate@binkert.org // Clear bits 42:35 of the physical address (10-2 in 2335569Snate@binkert.org // Tsunami manual) 2343838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & PAddrUncachedMask); 2353838Shsul@eecs.umich.edu#endif 236924SN/A } 2375532Ssaidi@eecs.umich.edu // We shouldn't be able to read from an uncachable address in Alpha as 2385532Ssaidi@eecs.umich.edu // we don't have a ROM and we don't want to try to fetch from a device 2395532Ssaidi@eecs.umich.edu // register as we destroy any data that is clear-on-read. 2405532Ssaidi@eecs.umich.edu if (req->isUncacheable() && itb) 2415532Ssaidi@eecs.umich.edu return new UnimpFault("CPU trying to fetch from uncached I/O"); 2425532Ssaidi@eecs.umich.edu 2432SN/A } 2443838Shsul@eecs.umich.edu return NoFault; 2453838Shsul@eecs.umich.edu} 2462SN/A 2472SN/A 2483838Shsul@eecs.umich.edu// insert a new TLB entry 2493838Shsul@eecs.umich.eduvoid 2505004Sgblack@eecs.umich.eduTLB::insert(Addr addr, TlbEntry &entry) 2513838Shsul@eecs.umich.edu{ 2524957Sacolyte@umich.edu flushCache(); 2533838Shsul@eecs.umich.edu VAddr vaddr = addr; 2543838Shsul@eecs.umich.edu if (table[nlu].valid) { 2553838Shsul@eecs.umich.edu Addr oldvpn = table[nlu].tag; 2563838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(oldvpn); 2573838Shsul@eecs.umich.edu 2583838Shsul@eecs.umich.edu if (i == lookupTable.end()) 2593838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 2603838Shsul@eecs.umich.edu 2613838Shsul@eecs.umich.edu int index; 2623838Shsul@eecs.umich.edu while ((index = i->second) != nlu) { 2633838Shsul@eecs.umich.edu if (table[index].tag != oldvpn) 2643838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 2653838Shsul@eecs.umich.edu 2663838Shsul@eecs.umich.edu ++i; 2673838Shsul@eecs.umich.edu } 2683838Shsul@eecs.umich.edu 2693838Shsul@eecs.umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 2703838Shsul@eecs.umich.edu 2713838Shsul@eecs.umich.edu lookupTable.erase(i); 2723838Shsul@eecs.umich.edu } 2733838Shsul@eecs.umich.edu 2745004Sgblack@eecs.umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn); 2753838Shsul@eecs.umich.edu 2765004Sgblack@eecs.umich.edu table[nlu] = entry; 2773838Shsul@eecs.umich.edu table[nlu].tag = vaddr.vpn(); 2783838Shsul@eecs.umich.edu table[nlu].valid = true; 2793838Shsul@eecs.umich.edu 2803838Shsul@eecs.umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 2813838Shsul@eecs.umich.edu nextnlu(); 2823838Shsul@eecs.umich.edu} 2833838Shsul@eecs.umich.edu 2843838Shsul@eecs.umich.eduvoid 2853838Shsul@eecs.umich.eduTLB::flushAll() 2863838Shsul@eecs.umich.edu{ 2873838Shsul@eecs.umich.edu DPRINTF(TLB, "flushAll\n"); 2885004Sgblack@eecs.umich.edu memset(table, 0, sizeof(TlbEntry[size])); 2894957Sacolyte@umich.edu flushCache(); 2903838Shsul@eecs.umich.edu lookupTable.clear(); 2913838Shsul@eecs.umich.edu nlu = 0; 2923838Shsul@eecs.umich.edu} 2933838Shsul@eecs.umich.edu 2943838Shsul@eecs.umich.eduvoid 2953838Shsul@eecs.umich.eduTLB::flushProcesses() 2963838Shsul@eecs.umich.edu{ 2974957Sacolyte@umich.edu flushCache(); 2983838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.begin(); 2993838Shsul@eecs.umich.edu PageTable::iterator end = lookupTable.end(); 3003838Shsul@eecs.umich.edu while (i != end) { 3013838Shsul@eecs.umich.edu int index = i->second; 3025004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 3035004Sgblack@eecs.umich.edu assert(entry->valid); 3043838Shsul@eecs.umich.edu 3053838Shsul@eecs.umich.edu // we can't increment i after we erase it, so save a copy and 3063838Shsul@eecs.umich.edu // increment it to get the next entry now 3073838Shsul@eecs.umich.edu PageTable::iterator cur = i; 3083838Shsul@eecs.umich.edu ++i; 3093838Shsul@eecs.umich.edu 3105004Sgblack@eecs.umich.edu if (!entry->asma) { 3115569Snate@binkert.org DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, 3125569Snate@binkert.org entry->tag, entry->ppn); 3135004Sgblack@eecs.umich.edu entry->valid = false; 3143838Shsul@eecs.umich.edu lookupTable.erase(cur); 3153453Sgblack@eecs.umich.edu } 3163453Sgblack@eecs.umich.edu } 3173838Shsul@eecs.umich.edu} 3182SN/A 3193838Shsul@eecs.umich.eduvoid 3203838Shsul@eecs.umich.eduTLB::flushAddr(Addr addr, uint8_t asn) 3213838Shsul@eecs.umich.edu{ 3224957Sacolyte@umich.edu flushCache(); 3233838Shsul@eecs.umich.edu VAddr vaddr = addr; 3242SN/A 3253838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(vaddr.vpn()); 3263838Shsul@eecs.umich.edu if (i == lookupTable.end()) 3273838Shsul@eecs.umich.edu return; 3282SN/A 3294428Ssaidi@eecs.umich.edu while (i != lookupTable.end() && i->first == vaddr.vpn()) { 3303838Shsul@eecs.umich.edu int index = i->second; 3315004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 3325004Sgblack@eecs.umich.edu assert(entry->valid); 3333453Sgblack@eecs.umich.edu 3345004Sgblack@eecs.umich.edu if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) { 3353838Shsul@eecs.umich.edu DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 3365004Sgblack@eecs.umich.edu entry->ppn); 3373453Sgblack@eecs.umich.edu 3383838Shsul@eecs.umich.edu // invalidate this entry 3395004Sgblack@eecs.umich.edu entry->valid = false; 3403838Shsul@eecs.umich.edu 3414428Ssaidi@eecs.umich.edu lookupTable.erase(i++); 3424428Ssaidi@eecs.umich.edu } else { 3434428Ssaidi@eecs.umich.edu ++i; 3443838Shsul@eecs.umich.edu } 3453838Shsul@eecs.umich.edu } 3463838Shsul@eecs.umich.edu} 3473838Shsul@eecs.umich.edu 3483838Shsul@eecs.umich.edu 3493838Shsul@eecs.umich.eduvoid 3503838Shsul@eecs.umich.eduTLB::serialize(ostream &os) 3513838Shsul@eecs.umich.edu{ 3523838Shsul@eecs.umich.edu SERIALIZE_SCALAR(size); 3533838Shsul@eecs.umich.edu SERIALIZE_SCALAR(nlu); 3543838Shsul@eecs.umich.edu 3553838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 3565004Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.Entry%d", name(), i)); 3573838Shsul@eecs.umich.edu table[i].serialize(os); 3583838Shsul@eecs.umich.edu } 3593838Shsul@eecs.umich.edu} 3603838Shsul@eecs.umich.edu 3613838Shsul@eecs.umich.eduvoid 3623838Shsul@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const string §ion) 3633838Shsul@eecs.umich.edu{ 3643838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(size); 3653838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(nlu); 3663838Shsul@eecs.umich.edu 3673838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 3685004Sgblack@eecs.umich.edu table[i].unserialize(cp, csprintf("%s.Entry%d", section, i)); 3693838Shsul@eecs.umich.edu if (table[i].valid) { 3703838Shsul@eecs.umich.edu lookupTable.insert(make_pair(table[i].tag, i)); 3713838Shsul@eecs.umich.edu } 3723838Shsul@eecs.umich.edu } 3733838Shsul@eecs.umich.edu} 3743838Shsul@eecs.umich.edu 3753838Shsul@eecs.umich.eduFault 3766022Sgblack@eecs.umich.eduTLB::translateInst(RequestPtr req, ThreadContext *tc) 3773838Shsul@eecs.umich.edu{ 3784375Sgblack@eecs.umich.edu //If this is a pal pc, then set PHYSICAL 3795569Snate@binkert.org if (FULL_SYSTEM && PcPAL(req->getPC())) 3805736Snate@binkert.org req->setFlags(Request::PHYSICAL); 3814375Sgblack@eecs.umich.edu 3823838Shsul@eecs.umich.edu if (PcPAL(req->getPC())) { 3833838Shsul@eecs.umich.edu // strip off PAL PC marker (lsb is 1) 3843838Shsul@eecs.umich.edu req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 3856022Sgblack@eecs.umich.edu fetch_hits++; 3863838Shsul@eecs.umich.edu return NoFault; 3873453Sgblack@eecs.umich.edu } 3883453Sgblack@eecs.umich.edu 3895736Snate@binkert.org if (req->getFlags() & Request::PHYSICAL) { 3903838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 3913838Shsul@eecs.umich.edu } else { 3923838Shsul@eecs.umich.edu // verify that this is a good virtual address 3933838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 3946022Sgblack@eecs.umich.edu fetch_acv++; 3953838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 3962SN/A } 3972SN/A 3983838Shsul@eecs.umich.edu 3993838Shsul@eecs.umich.edu // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 4003838Shsul@eecs.umich.edu // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 4013838Shsul@eecs.umich.edu#if ALPHA_TLASER 4024172Ssaidi@eecs.umich.edu if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 4034088Sbinkertn@umich.edu VAddrSpaceEV5(req->getVaddr()) == 2) 4043838Shsul@eecs.umich.edu#else 4054088Sbinkertn@umich.edu if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 4063838Shsul@eecs.umich.edu#endif 4074088Sbinkertn@umich.edu { 4083838Shsul@eecs.umich.edu // only valid in kernel mode 4094172Ssaidi@eecs.umich.edu if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 4103838Shsul@eecs.umich.edu mode_kernel) { 4116022Sgblack@eecs.umich.edu fetch_acv++; 4122532SN/A return new ItbAcvFault(req->getVaddr()); 413555SN/A } 4142SN/A 4153838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 416551SN/A 4171858SN/A#if !ALPHA_TLASER 4183838Shsul@eecs.umich.edu // sign extend the physical address properly 4193838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 4203838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 4213838Shsul@eecs.umich.edu else 4223838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 423924SN/A#endif 424828SN/A 4253838Shsul@eecs.umich.edu } else { 4263838Shsul@eecs.umich.edu // not a physical address: need to look up pte 4274172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 4285004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 4293838Shsul@eecs.umich.edu asn); 4303838Shsul@eecs.umich.edu 4315004Sgblack@eecs.umich.edu if (!entry) { 4326022Sgblack@eecs.umich.edu fetch_misses++; 4333838Shsul@eecs.umich.edu return new ItbPageFault(req->getVaddr()); 4343838Shsul@eecs.umich.edu } 4353838Shsul@eecs.umich.edu 4365004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 4373838Shsul@eecs.umich.edu (VAddr(req->getVaddr()).offset() 4383838Shsul@eecs.umich.edu & ~3)); 4393838Shsul@eecs.umich.edu 4403838Shsul@eecs.umich.edu // check permissions for this access 4415004Sgblack@eecs.umich.edu if (!(entry->xre & 4424172Ssaidi@eecs.umich.edu (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 4433838Shsul@eecs.umich.edu // instruction access fault 4446022Sgblack@eecs.umich.edu fetch_acv++; 4453838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 4463838Shsul@eecs.umich.edu } 4473838Shsul@eecs.umich.edu 4486022Sgblack@eecs.umich.edu fetch_hits++; 4493838Shsul@eecs.umich.edu } 4503838Shsul@eecs.umich.edu } 4513838Shsul@eecs.umich.edu 4523838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 4533838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 4543838Shsul@eecs.umich.edu return genMachineCheckFault(); 4553838Shsul@eecs.umich.edu 4565532Ssaidi@eecs.umich.edu return checkCacheability(req, true); 4573838Shsul@eecs.umich.edu 4583838Shsul@eecs.umich.edu} 4593838Shsul@eecs.umich.edu 4603838Shsul@eecs.umich.eduFault 4616022Sgblack@eecs.umich.eduTLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 4623838Shsul@eecs.umich.edu{ 4633838Shsul@eecs.umich.edu Addr pc = tc->readPC(); 4643838Shsul@eecs.umich.edu 4653838Shsul@eecs.umich.edu mode_type mode = 4664172Ssaidi@eecs.umich.edu (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 4673838Shsul@eecs.umich.edu 4683838Shsul@eecs.umich.edu /** 4693838Shsul@eecs.umich.edu * Check for alignment faults 4703838Shsul@eecs.umich.edu */ 4713838Shsul@eecs.umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4723838Shsul@eecs.umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 4733838Shsul@eecs.umich.edu req->getSize()); 4743838Shsul@eecs.umich.edu uint64_t flags = write ? MM_STAT_WR_MASK : 0; 4753838Shsul@eecs.umich.edu return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 4763838Shsul@eecs.umich.edu } 4773838Shsul@eecs.umich.edu 4783838Shsul@eecs.umich.edu if (PcPAL(pc)) { 4795736Snate@binkert.org mode = (req->getFlags() & Request::ALTMODE) ? 4803838Shsul@eecs.umich.edu (mode_type)ALT_MODE_AM( 4814172Ssaidi@eecs.umich.edu tc->readMiscRegNoEffect(IPR_ALT_MODE)) 4823838Shsul@eecs.umich.edu : mode_kernel; 4833838Shsul@eecs.umich.edu } 4843838Shsul@eecs.umich.edu 4855736Snate@binkert.org if (req->getFlags() & Request::PHYSICAL) { 4863838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 4873838Shsul@eecs.umich.edu } else { 4883838Shsul@eecs.umich.edu // verify that this is a good virtual address 4893838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 4903838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 4913838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 4923838Shsul@eecs.umich.edu MM_STAT_BAD_VA_MASK | 4933838Shsul@eecs.umich.edu MM_STAT_ACV_MASK; 4943838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 4953838Shsul@eecs.umich.edu } 4963838Shsul@eecs.umich.edu 4973838Shsul@eecs.umich.edu // Check for "superpage" mapping 4983838Shsul@eecs.umich.edu#if ALPHA_TLASER 4994172Ssaidi@eecs.umich.edu if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 5004088Sbinkertn@umich.edu VAddrSpaceEV5(req->getVaddr()) == 2) 5013838Shsul@eecs.umich.edu#else 5024088Sbinkertn@umich.edu if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 5033838Shsul@eecs.umich.edu#endif 5044088Sbinkertn@umich.edu { 5053838Shsul@eecs.umich.edu // only valid in kernel mode 5064172Ssaidi@eecs.umich.edu if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 5073838Shsul@eecs.umich.edu mode_kernel) { 5083838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 5093838Shsul@eecs.umich.edu uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 5103838Shsul@eecs.umich.edu MM_STAT_ACV_MASK); 5115569Snate@binkert.org 5125569Snate@binkert.org return new DtbAcvFault(req->getVaddr(), req->getFlags(), 5135569Snate@binkert.org flags); 5143838Shsul@eecs.umich.edu } 5153838Shsul@eecs.umich.edu 5163838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 5173838Shsul@eecs.umich.edu 5183838Shsul@eecs.umich.edu#if !ALPHA_TLASER 5193838Shsul@eecs.umich.edu // sign extend the physical address properly 5203838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 5213838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 5223838Shsul@eecs.umich.edu else 5233838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 5243838Shsul@eecs.umich.edu#endif 5253838Shsul@eecs.umich.edu 5263838Shsul@eecs.umich.edu } else { 5273838Shsul@eecs.umich.edu if (write) 5283838Shsul@eecs.umich.edu write_accesses++; 5293838Shsul@eecs.umich.edu else 5303838Shsul@eecs.umich.edu read_accesses++; 5313838Shsul@eecs.umich.edu 5324172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 5333838Shsul@eecs.umich.edu 5343838Shsul@eecs.umich.edu // not a physical address: need to look up pte 5355004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn); 5363838Shsul@eecs.umich.edu 5375004Sgblack@eecs.umich.edu if (!entry) { 5383838Shsul@eecs.umich.edu // page fault 5393838Shsul@eecs.umich.edu if (write) { write_misses++; } else { read_misses++; } 5403838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5413838Shsul@eecs.umich.edu MM_STAT_DTB_MISS_MASK; 5425736Snate@binkert.org return (req->getFlags() & Request::VPTE) ? 5433838Shsul@eecs.umich.edu (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 5443838Shsul@eecs.umich.edu flags)) : 5453838Shsul@eecs.umich.edu (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 5463838Shsul@eecs.umich.edu flags)); 5473838Shsul@eecs.umich.edu } 5483838Shsul@eecs.umich.edu 5495004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 5503838Shsul@eecs.umich.edu VAddr(req->getVaddr()).offset()); 5513838Shsul@eecs.umich.edu 5523838Shsul@eecs.umich.edu if (write) { 5535004Sgblack@eecs.umich.edu if (!(entry->xwe & MODE2MASK(mode))) { 5543838Shsul@eecs.umich.edu // declare the instruction access fault 5553838Shsul@eecs.umich.edu write_acv++; 5563838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5573838Shsul@eecs.umich.edu MM_STAT_ACV_MASK | 5585004Sgblack@eecs.umich.edu (entry->fonw ? MM_STAT_FONW_MASK : 0); 5595569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 5605569Snate@binkert.org flags); 5613838Shsul@eecs.umich.edu } 5625004Sgblack@eecs.umich.edu if (entry->fonw) { 5633838Shsul@eecs.umich.edu write_acv++; 5645569Snate@binkert.org uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK; 5655569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 5665569Snate@binkert.org flags); 5673838Shsul@eecs.umich.edu } 5683453Sgblack@eecs.umich.edu } else { 5695004Sgblack@eecs.umich.edu if (!(entry->xre & MODE2MASK(mode))) { 5703838Shsul@eecs.umich.edu read_acv++; 5713838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_ACV_MASK | 5725004Sgblack@eecs.umich.edu (entry->fonr ? MM_STAT_FONR_MASK : 0); 5735569Snate@binkert.org return new DtbAcvFault(req->getVaddr(), req->getFlags(), 5745569Snate@binkert.org flags); 5753453Sgblack@eecs.umich.edu } 5765004Sgblack@eecs.umich.edu if (entry->fonr) { 5773838Shsul@eecs.umich.edu read_acv++; 5783838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_FONR_MASK; 5795569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 5805569Snate@binkert.org flags); 5813453Sgblack@eecs.umich.edu } 5822SN/A } 5832SN/A } 584551SN/A 5853838Shsul@eecs.umich.edu if (write) 5863838Shsul@eecs.umich.edu write_hits++; 5873838Shsul@eecs.umich.edu else 5883838Shsul@eecs.umich.edu read_hits++; 5892SN/A } 5902SN/A 5913838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 5923838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 5933838Shsul@eecs.umich.edu return genMachineCheckFault(); 594551SN/A 5953838Shsul@eecs.umich.edu return checkCacheability(req); 5963838Shsul@eecs.umich.edu} 5973453Sgblack@eecs.umich.edu 5985004Sgblack@eecs.umich.eduTlbEntry & 5993838Shsul@eecs.umich.eduTLB::index(bool advance) 6003838Shsul@eecs.umich.edu{ 6015004Sgblack@eecs.umich.edu TlbEntry *entry = &table[nlu]; 6023453Sgblack@eecs.umich.edu 6033838Shsul@eecs.umich.edu if (advance) 6043838Shsul@eecs.umich.edu nextnlu(); 6053453Sgblack@eecs.umich.edu 6065004Sgblack@eecs.umich.edu return *entry; 6073838Shsul@eecs.umich.edu} 6083453Sgblack@eecs.umich.edu 6096022Sgblack@eecs.umich.eduFault 6106022Sgblack@eecs.umich.eduTLB::translateAtomic(RequestPtr req, ThreadContext *tc, 6116022Sgblack@eecs.umich.edu bool write, bool execute) 6126022Sgblack@eecs.umich.edu{ 6136022Sgblack@eecs.umich.edu if (execute) 6146022Sgblack@eecs.umich.edu return translateInst(req, tc); 6156022Sgblack@eecs.umich.edu else 6166022Sgblack@eecs.umich.edu return translateData(req, tc, write); 6176022Sgblack@eecs.umich.edu} 6186022Sgblack@eecs.umich.edu 6196022Sgblack@eecs.umich.eduvoid 6206022Sgblack@eecs.umich.eduTLB::translateTiming(RequestPtr req, ThreadContext *tc, 6216022Sgblack@eecs.umich.edu Translation *translation, 6226022Sgblack@eecs.umich.edu bool write, bool execute) 6236022Sgblack@eecs.umich.edu{ 6246022Sgblack@eecs.umich.edu assert(translation); 6256022Sgblack@eecs.umich.edu translation->finish(translateAtomic(req, tc, write, execute), 6266022Sgblack@eecs.umich.edu req, tc, write, execute); 6276022Sgblack@eecs.umich.edu} 6286022Sgblack@eecs.umich.edu 6295569Snate@binkert.org/* end namespace AlphaISA */ } 6304088Sbinkertn@umich.edu 6316022Sgblack@eecs.umich.eduAlphaISA::TLB * 6326022Sgblack@eecs.umich.eduAlphaTLBParams::create() 6333838Shsul@eecs.umich.edu{ 6346022Sgblack@eecs.umich.edu return new AlphaISA::TLB(this); 6353838Shsul@eecs.umich.edu} 636