tlb.cc revision 5569
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Andrew Schultz 312SN/A */ 322SN/A 332SN/A#include <string> 342SN/A#include <vector> 352SN/A 362984Sgblack@eecs.umich.edu#include "arch/alpha/pagetable.hh" 372171SN/A#include "arch/alpha/tlb.hh" 382984Sgblack@eecs.umich.edu#include "arch/alpha/faults.hh" 39146SN/A#include "base/inifile.hh" 40146SN/A#include "base/str.hh" 41146SN/A#include "base/trace.hh" 421858SN/A#include "config/alpha_tlaser.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 442SN/A 452SN/Ausing namespace std; 462SN/A 474088Sbinkertn@umich.edunamespace AlphaISA { 485569Snate@binkert.org 493838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 503838Shsul@eecs.umich.edu// 513838Shsul@eecs.umich.edu// Alpha TLB 523838Shsul@eecs.umich.edu// 535569Snate@binkert.org 54860SN/A#ifdef DEBUG 553838Shsul@eecs.umich.edubool uncacheBit39 = false; 563838Shsul@eecs.umich.edubool uncacheBit40 = false; 57860SN/A#endif 58860SN/A 595569Snate@binkert.org#define MODE2MASK(X) (1 << (X)) 601147SN/A 615034Smilesck@eecs.umich.eduTLB::TLB(const Params *p) 625358Sgblack@eecs.umich.edu : BaseTLB(p), size(p->size), nlu(0) 633838Shsul@eecs.umich.edu{ 645004Sgblack@eecs.umich.edu table = new TlbEntry[size]; 655004Sgblack@eecs.umich.edu memset(table, 0, sizeof(TlbEntry[size])); 664957Sacolyte@umich.edu flushCache(); 673838Shsul@eecs.umich.edu} 682SN/A 693838Shsul@eecs.umich.eduTLB::~TLB() 703838Shsul@eecs.umich.edu{ 713838Shsul@eecs.umich.edu if (table) 723838Shsul@eecs.umich.edu delete [] table; 733838Shsul@eecs.umich.edu} 742SN/A 753838Shsul@eecs.umich.edu// look up an entry in the TLB 765004Sgblack@eecs.umich.eduTlbEntry * 774967Sacolyte@umich.eduTLB::lookup(Addr vpn, uint8_t asn) 783838Shsul@eecs.umich.edu{ 793838Shsul@eecs.umich.edu // assume not found... 805004Sgblack@eecs.umich.edu TlbEntry *retval = NULL; 812SN/A 825004Sgblack@eecs.umich.edu if (EntryCache[0]) { 835004Sgblack@eecs.umich.edu if (vpn == EntryCache[0]->tag && 845004Sgblack@eecs.umich.edu (EntryCache[0]->asma || EntryCache[0]->asn == asn)) 855004Sgblack@eecs.umich.edu retval = EntryCache[0]; 865004Sgblack@eecs.umich.edu else if (EntryCache[1]) { 875004Sgblack@eecs.umich.edu if (vpn == EntryCache[1]->tag && 885004Sgblack@eecs.umich.edu (EntryCache[1]->asma || EntryCache[1]->asn == asn)) 895004Sgblack@eecs.umich.edu retval = EntryCache[1]; 905004Sgblack@eecs.umich.edu else if (EntryCache[2] && vpn == EntryCache[2]->tag && 915004Sgblack@eecs.umich.edu (EntryCache[2]->asma || EntryCache[2]->asn == asn)) 925004Sgblack@eecs.umich.edu retval = EntryCache[2]; 934962Sacolyte@umich.edu } 944962Sacolyte@umich.edu } 954962Sacolyte@umich.edu 964967Sacolyte@umich.edu if (retval == NULL) { 974957Sacolyte@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 984957Sacolyte@umich.edu if (i != lookupTable.end()) { 994957Sacolyte@umich.edu while (i->first == vpn) { 1004957Sacolyte@umich.edu int index = i->second; 1015004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 1025004Sgblack@eecs.umich.edu assert(entry->valid); 1035004Sgblack@eecs.umich.edu if (vpn == entry->tag && (entry->asma || entry->asn == asn)) { 1045004Sgblack@eecs.umich.edu retval = updateCache(entry); 1054957Sacolyte@umich.edu break; 1064957Sacolyte@umich.edu } 1074957Sacolyte@umich.edu 1084957Sacolyte@umich.edu ++i; 1091413SN/A } 1101413SN/A } 1112SN/A } 1122SN/A 1133838Shsul@eecs.umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1143838Shsul@eecs.umich.edu retval ? "hit" : "miss", retval ? retval->ppn : 0); 1153838Shsul@eecs.umich.edu return retval; 1163838Shsul@eecs.umich.edu} 1172SN/A 1183838Shsul@eecs.umich.eduFault 1195532Ssaidi@eecs.umich.eduTLB::checkCacheability(RequestPtr &req, bool itb) 1203838Shsul@eecs.umich.edu{ 1215569Snate@binkert.org // in Alpha, cacheability is controlled by upper-level bits of the 1225569Snate@binkert.org // physical address 1233838Shsul@eecs.umich.edu 1245569Snate@binkert.org /* 1255569Snate@binkert.org * We support having the uncacheable bit in either bit 39 or bit 1265569Snate@binkert.org * 40. The Turbolaser platform (and EV5) support having the bit 1275569Snate@binkert.org * in 39, but Tsunami (which Linux assumes uses an EV6) generates 1285569Snate@binkert.org * accesses with the bit in 40. So we must check for both, but we 1295569Snate@binkert.org * have debug flags to catch a weird case where both are used, 1305569Snate@binkert.org * which shouldn't happen. 1315569Snate@binkert.org */ 1323838Shsul@eecs.umich.edu 1333838Shsul@eecs.umich.edu 1343838Shsul@eecs.umich.edu#if ALPHA_TLASER 1354088Sbinkertn@umich.edu if (req->getPaddr() & PAddrUncachedBit39) 1363838Shsul@eecs.umich.edu#else 1374088Sbinkertn@umich.edu if (req->getPaddr() & PAddrUncachedBit43) 1383838Shsul@eecs.umich.edu#endif 1394088Sbinkertn@umich.edu { 1403838Shsul@eecs.umich.edu // IPR memory space not implemented 1413838Shsul@eecs.umich.edu if (PAddrIprSpace(req->getPaddr())) { 1423838Shsul@eecs.umich.edu return new UnimpFault("IPR memory space not implemented!"); 1433838Shsul@eecs.umich.edu } else { 1443838Shsul@eecs.umich.edu // mark request as uncacheable 1453838Shsul@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 1463838Shsul@eecs.umich.edu 1473838Shsul@eecs.umich.edu#if !ALPHA_TLASER 1485569Snate@binkert.org // Clear bits 42:35 of the physical address (10-2 in 1495569Snate@binkert.org // Tsunami manual) 1503838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & PAddrUncachedMask); 1513838Shsul@eecs.umich.edu#endif 152924SN/A } 1535532Ssaidi@eecs.umich.edu // We shouldn't be able to read from an uncachable address in Alpha as 1545532Ssaidi@eecs.umich.edu // we don't have a ROM and we don't want to try to fetch from a device 1555532Ssaidi@eecs.umich.edu // register as we destroy any data that is clear-on-read. 1565532Ssaidi@eecs.umich.edu if (req->isUncacheable() && itb) 1575532Ssaidi@eecs.umich.edu return new UnimpFault("CPU trying to fetch from uncached I/O"); 1585532Ssaidi@eecs.umich.edu 1592SN/A } 1603838Shsul@eecs.umich.edu return NoFault; 1613838Shsul@eecs.umich.edu} 1622SN/A 1632SN/A 1643838Shsul@eecs.umich.edu// insert a new TLB entry 1653838Shsul@eecs.umich.eduvoid 1665004Sgblack@eecs.umich.eduTLB::insert(Addr addr, TlbEntry &entry) 1673838Shsul@eecs.umich.edu{ 1684957Sacolyte@umich.edu flushCache(); 1693838Shsul@eecs.umich.edu VAddr vaddr = addr; 1703838Shsul@eecs.umich.edu if (table[nlu].valid) { 1713838Shsul@eecs.umich.edu Addr oldvpn = table[nlu].tag; 1723838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(oldvpn); 1733838Shsul@eecs.umich.edu 1743838Shsul@eecs.umich.edu if (i == lookupTable.end()) 1753838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 1763838Shsul@eecs.umich.edu 1773838Shsul@eecs.umich.edu int index; 1783838Shsul@eecs.umich.edu while ((index = i->second) != nlu) { 1793838Shsul@eecs.umich.edu if (table[index].tag != oldvpn) 1803838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 1813838Shsul@eecs.umich.edu 1823838Shsul@eecs.umich.edu ++i; 1833838Shsul@eecs.umich.edu } 1843838Shsul@eecs.umich.edu 1853838Shsul@eecs.umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 1863838Shsul@eecs.umich.edu 1873838Shsul@eecs.umich.edu lookupTable.erase(i); 1883838Shsul@eecs.umich.edu } 1893838Shsul@eecs.umich.edu 1905004Sgblack@eecs.umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn); 1913838Shsul@eecs.umich.edu 1925004Sgblack@eecs.umich.edu table[nlu] = entry; 1933838Shsul@eecs.umich.edu table[nlu].tag = vaddr.vpn(); 1943838Shsul@eecs.umich.edu table[nlu].valid = true; 1953838Shsul@eecs.umich.edu 1963838Shsul@eecs.umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 1973838Shsul@eecs.umich.edu nextnlu(); 1983838Shsul@eecs.umich.edu} 1993838Shsul@eecs.umich.edu 2003838Shsul@eecs.umich.eduvoid 2013838Shsul@eecs.umich.eduTLB::flushAll() 2023838Shsul@eecs.umich.edu{ 2033838Shsul@eecs.umich.edu DPRINTF(TLB, "flushAll\n"); 2045004Sgblack@eecs.umich.edu memset(table, 0, sizeof(TlbEntry[size])); 2054957Sacolyte@umich.edu flushCache(); 2063838Shsul@eecs.umich.edu lookupTable.clear(); 2073838Shsul@eecs.umich.edu nlu = 0; 2083838Shsul@eecs.umich.edu} 2093838Shsul@eecs.umich.edu 2103838Shsul@eecs.umich.eduvoid 2113838Shsul@eecs.umich.eduTLB::flushProcesses() 2123838Shsul@eecs.umich.edu{ 2134957Sacolyte@umich.edu flushCache(); 2143838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.begin(); 2153838Shsul@eecs.umich.edu PageTable::iterator end = lookupTable.end(); 2163838Shsul@eecs.umich.edu while (i != end) { 2173838Shsul@eecs.umich.edu int index = i->second; 2185004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 2195004Sgblack@eecs.umich.edu assert(entry->valid); 2203838Shsul@eecs.umich.edu 2213838Shsul@eecs.umich.edu // we can't increment i after we erase it, so save a copy and 2223838Shsul@eecs.umich.edu // increment it to get the next entry now 2233838Shsul@eecs.umich.edu PageTable::iterator cur = i; 2243838Shsul@eecs.umich.edu ++i; 2253838Shsul@eecs.umich.edu 2265004Sgblack@eecs.umich.edu if (!entry->asma) { 2275569Snate@binkert.org DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, 2285569Snate@binkert.org entry->tag, entry->ppn); 2295004Sgblack@eecs.umich.edu entry->valid = false; 2303838Shsul@eecs.umich.edu lookupTable.erase(cur); 2313453Sgblack@eecs.umich.edu } 2323453Sgblack@eecs.umich.edu } 2333838Shsul@eecs.umich.edu} 2342SN/A 2353838Shsul@eecs.umich.eduvoid 2363838Shsul@eecs.umich.eduTLB::flushAddr(Addr addr, uint8_t asn) 2373838Shsul@eecs.umich.edu{ 2384957Sacolyte@umich.edu flushCache(); 2393838Shsul@eecs.umich.edu VAddr vaddr = addr; 2402SN/A 2413838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(vaddr.vpn()); 2423838Shsul@eecs.umich.edu if (i == lookupTable.end()) 2433838Shsul@eecs.umich.edu return; 2442SN/A 2454428Ssaidi@eecs.umich.edu while (i != lookupTable.end() && i->first == vaddr.vpn()) { 2463838Shsul@eecs.umich.edu int index = i->second; 2475004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 2485004Sgblack@eecs.umich.edu assert(entry->valid); 2493453Sgblack@eecs.umich.edu 2505004Sgblack@eecs.umich.edu if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) { 2513838Shsul@eecs.umich.edu DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 2525004Sgblack@eecs.umich.edu entry->ppn); 2533453Sgblack@eecs.umich.edu 2543838Shsul@eecs.umich.edu // invalidate this entry 2555004Sgblack@eecs.umich.edu entry->valid = false; 2563838Shsul@eecs.umich.edu 2574428Ssaidi@eecs.umich.edu lookupTable.erase(i++); 2584428Ssaidi@eecs.umich.edu } else { 2594428Ssaidi@eecs.umich.edu ++i; 2603838Shsul@eecs.umich.edu } 2613838Shsul@eecs.umich.edu } 2623838Shsul@eecs.umich.edu} 2633838Shsul@eecs.umich.edu 2643838Shsul@eecs.umich.edu 2653838Shsul@eecs.umich.eduvoid 2663838Shsul@eecs.umich.eduTLB::serialize(ostream &os) 2673838Shsul@eecs.umich.edu{ 2683838Shsul@eecs.umich.edu SERIALIZE_SCALAR(size); 2693838Shsul@eecs.umich.edu SERIALIZE_SCALAR(nlu); 2703838Shsul@eecs.umich.edu 2713838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 2725004Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.Entry%d", name(), i)); 2733838Shsul@eecs.umich.edu table[i].serialize(os); 2743838Shsul@eecs.umich.edu } 2753838Shsul@eecs.umich.edu} 2763838Shsul@eecs.umich.edu 2773838Shsul@eecs.umich.eduvoid 2783838Shsul@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2793838Shsul@eecs.umich.edu{ 2803838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(size); 2813838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(nlu); 2823838Shsul@eecs.umich.edu 2833838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 2845004Sgblack@eecs.umich.edu table[i].unserialize(cp, csprintf("%s.Entry%d", section, i)); 2853838Shsul@eecs.umich.edu if (table[i].valid) { 2863838Shsul@eecs.umich.edu lookupTable.insert(make_pair(table[i].tag, i)); 2873838Shsul@eecs.umich.edu } 2883838Shsul@eecs.umich.edu } 2893838Shsul@eecs.umich.edu} 2903838Shsul@eecs.umich.edu 2913838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 2923838Shsul@eecs.umich.edu// 2933838Shsul@eecs.umich.edu// Alpha ITB 2943838Shsul@eecs.umich.edu// 2955034Smilesck@eecs.umich.eduITB::ITB(const Params *p) 2965034Smilesck@eecs.umich.edu : TLB(p) 2973838Shsul@eecs.umich.edu{} 2983838Shsul@eecs.umich.edu 2993838Shsul@eecs.umich.edu 3003838Shsul@eecs.umich.eduvoid 3013838Shsul@eecs.umich.eduITB::regStats() 3023838Shsul@eecs.umich.edu{ 3033838Shsul@eecs.umich.edu hits 3043838Shsul@eecs.umich.edu .name(name() + ".hits") 3053838Shsul@eecs.umich.edu .desc("ITB hits"); 3063838Shsul@eecs.umich.edu misses 3073838Shsul@eecs.umich.edu .name(name() + ".misses") 3083838Shsul@eecs.umich.edu .desc("ITB misses"); 3093838Shsul@eecs.umich.edu acv 3103838Shsul@eecs.umich.edu .name(name() + ".acv") 3113838Shsul@eecs.umich.edu .desc("ITB acv"); 3123838Shsul@eecs.umich.edu accesses 3133838Shsul@eecs.umich.edu .name(name() + ".accesses") 3143838Shsul@eecs.umich.edu .desc("ITB accesses"); 3153838Shsul@eecs.umich.edu 3163838Shsul@eecs.umich.edu accesses = hits + misses; 3173838Shsul@eecs.umich.edu} 3183838Shsul@eecs.umich.edu 3193838Shsul@eecs.umich.eduFault 3204967Sacolyte@umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 3213838Shsul@eecs.umich.edu{ 3224375Sgblack@eecs.umich.edu //If this is a pal pc, then set PHYSICAL 3235569Snate@binkert.org if (FULL_SYSTEM && PcPAL(req->getPC())) 3244375Sgblack@eecs.umich.edu req->setFlags(req->getFlags() | PHYSICAL); 3254375Sgblack@eecs.umich.edu 3263838Shsul@eecs.umich.edu if (PcPAL(req->getPC())) { 3273838Shsul@eecs.umich.edu // strip off PAL PC marker (lsb is 1) 3283838Shsul@eecs.umich.edu req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 3293838Shsul@eecs.umich.edu hits++; 3303838Shsul@eecs.umich.edu return NoFault; 3313453Sgblack@eecs.umich.edu } 3323453Sgblack@eecs.umich.edu 3333838Shsul@eecs.umich.edu if (req->getFlags() & PHYSICAL) { 3343838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 3353838Shsul@eecs.umich.edu } else { 3363838Shsul@eecs.umich.edu // verify that this is a good virtual address 3373838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 3383838Shsul@eecs.umich.edu acv++; 3393838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 3402SN/A } 3412SN/A 3423838Shsul@eecs.umich.edu 3433838Shsul@eecs.umich.edu // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 3443838Shsul@eecs.umich.edu // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 3453838Shsul@eecs.umich.edu#if ALPHA_TLASER 3464172Ssaidi@eecs.umich.edu if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 3474088Sbinkertn@umich.edu VAddrSpaceEV5(req->getVaddr()) == 2) 3483838Shsul@eecs.umich.edu#else 3494088Sbinkertn@umich.edu if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 3503838Shsul@eecs.umich.edu#endif 3514088Sbinkertn@umich.edu { 3523838Shsul@eecs.umich.edu // only valid in kernel mode 3534172Ssaidi@eecs.umich.edu if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 3543838Shsul@eecs.umich.edu mode_kernel) { 355555SN/A acv++; 3562532SN/A return new ItbAcvFault(req->getVaddr()); 357555SN/A } 3582SN/A 3593838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 360551SN/A 3611858SN/A#if !ALPHA_TLASER 3623838Shsul@eecs.umich.edu // sign extend the physical address properly 3633838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 3643838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 3653838Shsul@eecs.umich.edu else 3663838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 367924SN/A#endif 368828SN/A 3693838Shsul@eecs.umich.edu } else { 3703838Shsul@eecs.umich.edu // not a physical address: need to look up pte 3714172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 3725004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 3733838Shsul@eecs.umich.edu asn); 3743838Shsul@eecs.umich.edu 3755004Sgblack@eecs.umich.edu if (!entry) { 3763838Shsul@eecs.umich.edu misses++; 3773838Shsul@eecs.umich.edu return new ItbPageFault(req->getVaddr()); 3783838Shsul@eecs.umich.edu } 3793838Shsul@eecs.umich.edu 3805004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 3813838Shsul@eecs.umich.edu (VAddr(req->getVaddr()).offset() 3823838Shsul@eecs.umich.edu & ~3)); 3833838Shsul@eecs.umich.edu 3843838Shsul@eecs.umich.edu // check permissions for this access 3855004Sgblack@eecs.umich.edu if (!(entry->xre & 3864172Ssaidi@eecs.umich.edu (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 3873838Shsul@eecs.umich.edu // instruction access fault 3883838Shsul@eecs.umich.edu acv++; 3893838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 3903838Shsul@eecs.umich.edu } 3913838Shsul@eecs.umich.edu 3923838Shsul@eecs.umich.edu hits++; 3933838Shsul@eecs.umich.edu } 3943838Shsul@eecs.umich.edu } 3953838Shsul@eecs.umich.edu 3963838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 3973838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 3983838Shsul@eecs.umich.edu return genMachineCheckFault(); 3993838Shsul@eecs.umich.edu 4005532Ssaidi@eecs.umich.edu return checkCacheability(req, true); 4013838Shsul@eecs.umich.edu 4023838Shsul@eecs.umich.edu} 4033838Shsul@eecs.umich.edu 4043838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 4053838Shsul@eecs.umich.edu// 4063838Shsul@eecs.umich.edu// Alpha DTB 4073838Shsul@eecs.umich.edu// 4085569Snate@binkert.orgDTB::DTB(const Params *p) 4095034Smilesck@eecs.umich.edu : TLB(p) 4103838Shsul@eecs.umich.edu{} 4113838Shsul@eecs.umich.edu 4123838Shsul@eecs.umich.eduvoid 4133838Shsul@eecs.umich.eduDTB::regStats() 4143838Shsul@eecs.umich.edu{ 4153838Shsul@eecs.umich.edu read_hits 4163838Shsul@eecs.umich.edu .name(name() + ".read_hits") 4173838Shsul@eecs.umich.edu .desc("DTB read hits") 4183838Shsul@eecs.umich.edu ; 4193838Shsul@eecs.umich.edu 4203838Shsul@eecs.umich.edu read_misses 4213838Shsul@eecs.umich.edu .name(name() + ".read_misses") 4223838Shsul@eecs.umich.edu .desc("DTB read misses") 4233838Shsul@eecs.umich.edu ; 4243838Shsul@eecs.umich.edu 4253838Shsul@eecs.umich.edu read_acv 4263838Shsul@eecs.umich.edu .name(name() + ".read_acv") 4273838Shsul@eecs.umich.edu .desc("DTB read access violations") 4283838Shsul@eecs.umich.edu ; 4293838Shsul@eecs.umich.edu 4303838Shsul@eecs.umich.edu read_accesses 4313838Shsul@eecs.umich.edu .name(name() + ".read_accesses") 4323838Shsul@eecs.umich.edu .desc("DTB read accesses") 4333838Shsul@eecs.umich.edu ; 4343838Shsul@eecs.umich.edu 4353838Shsul@eecs.umich.edu write_hits 4363838Shsul@eecs.umich.edu .name(name() + ".write_hits") 4373838Shsul@eecs.umich.edu .desc("DTB write hits") 4383838Shsul@eecs.umich.edu ; 4393838Shsul@eecs.umich.edu 4403838Shsul@eecs.umich.edu write_misses 4413838Shsul@eecs.umich.edu .name(name() + ".write_misses") 4423838Shsul@eecs.umich.edu .desc("DTB write misses") 4433838Shsul@eecs.umich.edu ; 4443838Shsul@eecs.umich.edu 4453838Shsul@eecs.umich.edu write_acv 4463838Shsul@eecs.umich.edu .name(name() + ".write_acv") 4473838Shsul@eecs.umich.edu .desc("DTB write access violations") 4483838Shsul@eecs.umich.edu ; 4493838Shsul@eecs.umich.edu 4503838Shsul@eecs.umich.edu write_accesses 4513838Shsul@eecs.umich.edu .name(name() + ".write_accesses") 4523838Shsul@eecs.umich.edu .desc("DTB write accesses") 4533838Shsul@eecs.umich.edu ; 4543838Shsul@eecs.umich.edu 4553838Shsul@eecs.umich.edu hits 4563838Shsul@eecs.umich.edu .name(name() + ".hits") 4573838Shsul@eecs.umich.edu .desc("DTB hits") 4583838Shsul@eecs.umich.edu ; 4593838Shsul@eecs.umich.edu 4603838Shsul@eecs.umich.edu misses 4613838Shsul@eecs.umich.edu .name(name() + ".misses") 4623838Shsul@eecs.umich.edu .desc("DTB misses") 4633838Shsul@eecs.umich.edu ; 4643838Shsul@eecs.umich.edu 4653838Shsul@eecs.umich.edu acv 4663838Shsul@eecs.umich.edu .name(name() + ".acv") 4673838Shsul@eecs.umich.edu .desc("DTB access violations") 4683838Shsul@eecs.umich.edu ; 4693838Shsul@eecs.umich.edu 4703838Shsul@eecs.umich.edu accesses 4713838Shsul@eecs.umich.edu .name(name() + ".accesses") 4723838Shsul@eecs.umich.edu .desc("DTB accesses") 4733838Shsul@eecs.umich.edu ; 4743838Shsul@eecs.umich.edu 4753838Shsul@eecs.umich.edu hits = read_hits + write_hits; 4763838Shsul@eecs.umich.edu misses = read_misses + write_misses; 4773838Shsul@eecs.umich.edu acv = read_acv + write_acv; 4783838Shsul@eecs.umich.edu accesses = read_accesses + write_accesses; 4793838Shsul@eecs.umich.edu} 4803838Shsul@eecs.umich.edu 4813838Shsul@eecs.umich.eduFault 4824967Sacolyte@umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 4833838Shsul@eecs.umich.edu{ 4843838Shsul@eecs.umich.edu Addr pc = tc->readPC(); 4853838Shsul@eecs.umich.edu 4863838Shsul@eecs.umich.edu mode_type mode = 4874172Ssaidi@eecs.umich.edu (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 4883838Shsul@eecs.umich.edu 4893838Shsul@eecs.umich.edu /** 4903838Shsul@eecs.umich.edu * Check for alignment faults 4913838Shsul@eecs.umich.edu */ 4923838Shsul@eecs.umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4933838Shsul@eecs.umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 4943838Shsul@eecs.umich.edu req->getSize()); 4953838Shsul@eecs.umich.edu uint64_t flags = write ? MM_STAT_WR_MASK : 0; 4963838Shsul@eecs.umich.edu return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 4973838Shsul@eecs.umich.edu } 4983838Shsul@eecs.umich.edu 4993838Shsul@eecs.umich.edu if (PcPAL(pc)) { 5003838Shsul@eecs.umich.edu mode = (req->getFlags() & ALTMODE) ? 5013838Shsul@eecs.umich.edu (mode_type)ALT_MODE_AM( 5024172Ssaidi@eecs.umich.edu tc->readMiscRegNoEffect(IPR_ALT_MODE)) 5033838Shsul@eecs.umich.edu : mode_kernel; 5043838Shsul@eecs.umich.edu } 5053838Shsul@eecs.umich.edu 5063838Shsul@eecs.umich.edu if (req->getFlags() & PHYSICAL) { 5073838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 5083838Shsul@eecs.umich.edu } else { 5093838Shsul@eecs.umich.edu // verify that this is a good virtual address 5103838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 5113838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 5123838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5133838Shsul@eecs.umich.edu MM_STAT_BAD_VA_MASK | 5143838Shsul@eecs.umich.edu MM_STAT_ACV_MASK; 5153838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5163838Shsul@eecs.umich.edu } 5173838Shsul@eecs.umich.edu 5183838Shsul@eecs.umich.edu // Check for "superpage" mapping 5193838Shsul@eecs.umich.edu#if ALPHA_TLASER 5204172Ssaidi@eecs.umich.edu if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 5214088Sbinkertn@umich.edu VAddrSpaceEV5(req->getVaddr()) == 2) 5223838Shsul@eecs.umich.edu#else 5234088Sbinkertn@umich.edu if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 5243838Shsul@eecs.umich.edu#endif 5254088Sbinkertn@umich.edu { 5263838Shsul@eecs.umich.edu // only valid in kernel mode 5274172Ssaidi@eecs.umich.edu if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 5283838Shsul@eecs.umich.edu mode_kernel) { 5293838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 5303838Shsul@eecs.umich.edu uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 5313838Shsul@eecs.umich.edu MM_STAT_ACV_MASK); 5325569Snate@binkert.org 5335569Snate@binkert.org return new DtbAcvFault(req->getVaddr(), req->getFlags(), 5345569Snate@binkert.org flags); 5353838Shsul@eecs.umich.edu } 5363838Shsul@eecs.umich.edu 5373838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 5383838Shsul@eecs.umich.edu 5393838Shsul@eecs.umich.edu#if !ALPHA_TLASER 5403838Shsul@eecs.umich.edu // sign extend the physical address properly 5413838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 5423838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 5433838Shsul@eecs.umich.edu else 5443838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 5453838Shsul@eecs.umich.edu#endif 5463838Shsul@eecs.umich.edu 5473838Shsul@eecs.umich.edu } else { 5483838Shsul@eecs.umich.edu if (write) 5493838Shsul@eecs.umich.edu write_accesses++; 5503838Shsul@eecs.umich.edu else 5513838Shsul@eecs.umich.edu read_accesses++; 5523838Shsul@eecs.umich.edu 5534172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 5543838Shsul@eecs.umich.edu 5553838Shsul@eecs.umich.edu // not a physical address: need to look up pte 5565004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn); 5573838Shsul@eecs.umich.edu 5585004Sgblack@eecs.umich.edu if (!entry) { 5593838Shsul@eecs.umich.edu // page fault 5603838Shsul@eecs.umich.edu if (write) { write_misses++; } else { read_misses++; } 5613838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5623838Shsul@eecs.umich.edu MM_STAT_DTB_MISS_MASK; 5633838Shsul@eecs.umich.edu return (req->getFlags() & VPTE) ? 5643838Shsul@eecs.umich.edu (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 5653838Shsul@eecs.umich.edu flags)) : 5663838Shsul@eecs.umich.edu (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 5673838Shsul@eecs.umich.edu flags)); 5683838Shsul@eecs.umich.edu } 5693838Shsul@eecs.umich.edu 5705004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 5713838Shsul@eecs.umich.edu VAddr(req->getVaddr()).offset()); 5723838Shsul@eecs.umich.edu 5733838Shsul@eecs.umich.edu if (write) { 5745004Sgblack@eecs.umich.edu if (!(entry->xwe & MODE2MASK(mode))) { 5753838Shsul@eecs.umich.edu // declare the instruction access fault 5763838Shsul@eecs.umich.edu write_acv++; 5773838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5783838Shsul@eecs.umich.edu MM_STAT_ACV_MASK | 5795004Sgblack@eecs.umich.edu (entry->fonw ? MM_STAT_FONW_MASK : 0); 5805569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 5815569Snate@binkert.org flags); 5823838Shsul@eecs.umich.edu } 5835004Sgblack@eecs.umich.edu if (entry->fonw) { 5843838Shsul@eecs.umich.edu write_acv++; 5855569Snate@binkert.org uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK; 5865569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 5875569Snate@binkert.org flags); 5883838Shsul@eecs.umich.edu } 5893453Sgblack@eecs.umich.edu } else { 5905004Sgblack@eecs.umich.edu if (!(entry->xre & MODE2MASK(mode))) { 5913838Shsul@eecs.umich.edu read_acv++; 5923838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_ACV_MASK | 5935004Sgblack@eecs.umich.edu (entry->fonr ? MM_STAT_FONR_MASK : 0); 5945569Snate@binkert.org return new DtbAcvFault(req->getVaddr(), req->getFlags(), 5955569Snate@binkert.org flags); 5963453Sgblack@eecs.umich.edu } 5975004Sgblack@eecs.umich.edu if (entry->fonr) { 5983838Shsul@eecs.umich.edu read_acv++; 5993838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_FONR_MASK; 6005569Snate@binkert.org return new DtbPageFault(req->getVaddr(), req->getFlags(), 6015569Snate@binkert.org flags); 6023453Sgblack@eecs.umich.edu } 6032SN/A } 6042SN/A } 605551SN/A 6063838Shsul@eecs.umich.edu if (write) 6073838Shsul@eecs.umich.edu write_hits++; 6083838Shsul@eecs.umich.edu else 6093838Shsul@eecs.umich.edu read_hits++; 6102SN/A } 6112SN/A 6123838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 6133838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 6143838Shsul@eecs.umich.edu return genMachineCheckFault(); 615551SN/A 6163838Shsul@eecs.umich.edu return checkCacheability(req); 6173838Shsul@eecs.umich.edu} 6183453Sgblack@eecs.umich.edu 6195004Sgblack@eecs.umich.eduTlbEntry & 6203838Shsul@eecs.umich.eduTLB::index(bool advance) 6213838Shsul@eecs.umich.edu{ 6225004Sgblack@eecs.umich.edu TlbEntry *entry = &table[nlu]; 6233453Sgblack@eecs.umich.edu 6243838Shsul@eecs.umich.edu if (advance) 6253838Shsul@eecs.umich.edu nextnlu(); 6263453Sgblack@eecs.umich.edu 6275004Sgblack@eecs.umich.edu return *entry; 6283838Shsul@eecs.umich.edu} 6293453Sgblack@eecs.umich.edu 6305569Snate@binkert.org/* end namespace AlphaISA */ } 6314088Sbinkertn@umich.edu 6324762Snate@binkert.orgAlphaISA::ITB * 6334762Snate@binkert.orgAlphaITBParams::create() 6343838Shsul@eecs.umich.edu{ 6355034Smilesck@eecs.umich.edu return new AlphaISA::ITB(this); 6363838Shsul@eecs.umich.edu} 6373453Sgblack@eecs.umich.edu 6384762Snate@binkert.orgAlphaISA::DTB * 6394762Snate@binkert.orgAlphaDTBParams::create() 6403838Shsul@eecs.umich.edu{ 6415034Smilesck@eecs.umich.edu return new AlphaISA::DTB(this); 6423838Shsul@eecs.umich.edu} 643