tlb.cc revision 5004
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Andrew Schultz 312SN/A */ 322SN/A 332SN/A#include <string> 342SN/A#include <vector> 352SN/A 362984Sgblack@eecs.umich.edu#include "arch/alpha/pagetable.hh" 372171SN/A#include "arch/alpha/tlb.hh" 382984Sgblack@eecs.umich.edu#include "arch/alpha/faults.hh" 39146SN/A#include "base/inifile.hh" 40146SN/A#include "base/str.hh" 41146SN/A#include "base/trace.hh" 421858SN/A#include "config/alpha_tlaser.hh" 432680Sktlim@umich.edu#include "cpu/thread_context.hh" 444762Snate@binkert.org#include "params/AlphaDTB.hh" 454762Snate@binkert.org#include "params/AlphaITB.hh" 462SN/A 472SN/Ausing namespace std; 481147SN/Ausing namespace EV5; 492SN/A 504088Sbinkertn@umich.edunamespace AlphaISA { 513838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 523838Shsul@eecs.umich.edu// 533838Shsul@eecs.umich.edu// Alpha TLB 543838Shsul@eecs.umich.edu// 55860SN/A#ifdef DEBUG 563838Shsul@eecs.umich.edubool uncacheBit39 = false; 573838Shsul@eecs.umich.edubool uncacheBit40 = false; 58860SN/A#endif 59860SN/A 601147SN/A#define MODE2MASK(X) (1 << (X)) 611147SN/A 623838Shsul@eecs.umich.eduTLB::TLB(const string &name, int s) 633838Shsul@eecs.umich.edu : SimObject(name), size(s), nlu(0) 643838Shsul@eecs.umich.edu{ 655004Sgblack@eecs.umich.edu table = new TlbEntry[size]; 665004Sgblack@eecs.umich.edu memset(table, 0, sizeof(TlbEntry[size])); 674957Sacolyte@umich.edu flushCache(); 683838Shsul@eecs.umich.edu} 692SN/A 703838Shsul@eecs.umich.eduTLB::~TLB() 713838Shsul@eecs.umich.edu{ 723838Shsul@eecs.umich.edu if (table) 733838Shsul@eecs.umich.edu delete [] table; 743838Shsul@eecs.umich.edu} 752SN/A 763838Shsul@eecs.umich.edu// look up an entry in the TLB 775004Sgblack@eecs.umich.eduTlbEntry * 784967Sacolyte@umich.eduTLB::lookup(Addr vpn, uint8_t asn) 793838Shsul@eecs.umich.edu{ 803838Shsul@eecs.umich.edu // assume not found... 815004Sgblack@eecs.umich.edu TlbEntry *retval = NULL; 822SN/A 835004Sgblack@eecs.umich.edu if (EntryCache[0]) { 845004Sgblack@eecs.umich.edu if (vpn == EntryCache[0]->tag && 855004Sgblack@eecs.umich.edu (EntryCache[0]->asma || EntryCache[0]->asn == asn)) 865004Sgblack@eecs.umich.edu retval = EntryCache[0]; 875004Sgblack@eecs.umich.edu else if (EntryCache[1]) { 885004Sgblack@eecs.umich.edu if (vpn == EntryCache[1]->tag && 895004Sgblack@eecs.umich.edu (EntryCache[1]->asma || EntryCache[1]->asn == asn)) 905004Sgblack@eecs.umich.edu retval = EntryCache[1]; 915004Sgblack@eecs.umich.edu else if (EntryCache[2] && vpn == EntryCache[2]->tag && 925004Sgblack@eecs.umich.edu (EntryCache[2]->asma || EntryCache[2]->asn == asn)) 935004Sgblack@eecs.umich.edu retval = EntryCache[2]; 944962Sacolyte@umich.edu } 954962Sacolyte@umich.edu } 964962Sacolyte@umich.edu 974967Sacolyte@umich.edu if (retval == NULL) { 984957Sacolyte@umich.edu PageTable::const_iterator i = lookupTable.find(vpn); 994957Sacolyte@umich.edu if (i != lookupTable.end()) { 1004957Sacolyte@umich.edu while (i->first == vpn) { 1014957Sacolyte@umich.edu int index = i->second; 1025004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 1035004Sgblack@eecs.umich.edu assert(entry->valid); 1045004Sgblack@eecs.umich.edu if (vpn == entry->tag && (entry->asma || entry->asn == asn)) { 1055004Sgblack@eecs.umich.edu retval = updateCache(entry); 1064957Sacolyte@umich.edu break; 1074957Sacolyte@umich.edu } 1084957Sacolyte@umich.edu 1094957Sacolyte@umich.edu ++i; 1101413SN/A } 1111413SN/A } 1122SN/A } 1132SN/A 1143838Shsul@eecs.umich.edu DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, 1153838Shsul@eecs.umich.edu retval ? "hit" : "miss", retval ? retval->ppn : 0); 1163838Shsul@eecs.umich.edu return retval; 1173838Shsul@eecs.umich.edu} 1182SN/A 1192SN/A 1203838Shsul@eecs.umich.eduFault 1213838Shsul@eecs.umich.eduTLB::checkCacheability(RequestPtr &req) 1223838Shsul@eecs.umich.edu{ 1233838Shsul@eecs.umich.edu// in Alpha, cacheability is controlled by upper-level bits of the 1243838Shsul@eecs.umich.edu// physical address 1253838Shsul@eecs.umich.edu 1263838Shsul@eecs.umich.edu/* 1273838Shsul@eecs.umich.edu * We support having the uncacheable bit in either bit 39 or bit 40. 1283838Shsul@eecs.umich.edu * The Turbolaser platform (and EV5) support having the bit in 39, but 1293838Shsul@eecs.umich.edu * Tsunami (which Linux assumes uses an EV6) generates accesses with 1303838Shsul@eecs.umich.edu * the bit in 40. So we must check for both, but we have debug flags 1313838Shsul@eecs.umich.edu * to catch a weird case where both are used, which shouldn't happen. 1323838Shsul@eecs.umich.edu */ 1333838Shsul@eecs.umich.edu 1343838Shsul@eecs.umich.edu 1353838Shsul@eecs.umich.edu#if ALPHA_TLASER 1364088Sbinkertn@umich.edu if (req->getPaddr() & PAddrUncachedBit39) 1373838Shsul@eecs.umich.edu#else 1384088Sbinkertn@umich.edu if (req->getPaddr() & PAddrUncachedBit43) 1393838Shsul@eecs.umich.edu#endif 1404088Sbinkertn@umich.edu { 1413838Shsul@eecs.umich.edu // IPR memory space not implemented 1423838Shsul@eecs.umich.edu if (PAddrIprSpace(req->getPaddr())) { 1433838Shsul@eecs.umich.edu return new UnimpFault("IPR memory space not implemented!"); 1443838Shsul@eecs.umich.edu } else { 1453838Shsul@eecs.umich.edu // mark request as uncacheable 1463838Shsul@eecs.umich.edu req->setFlags(req->getFlags() | UNCACHEABLE); 1473838Shsul@eecs.umich.edu 1483838Shsul@eecs.umich.edu#if !ALPHA_TLASER 1493838Shsul@eecs.umich.edu // Clear bits 42:35 of the physical address (10-2 in Tsunami manual) 1503838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & PAddrUncachedMask); 1513838Shsul@eecs.umich.edu#endif 152924SN/A } 1532SN/A } 1543838Shsul@eecs.umich.edu return NoFault; 1553838Shsul@eecs.umich.edu} 1562SN/A 1572SN/A 1583838Shsul@eecs.umich.edu// insert a new TLB entry 1593838Shsul@eecs.umich.eduvoid 1605004Sgblack@eecs.umich.eduTLB::insert(Addr addr, TlbEntry &entry) 1613838Shsul@eecs.umich.edu{ 1624957Sacolyte@umich.edu flushCache(); 1633838Shsul@eecs.umich.edu VAddr vaddr = addr; 1643838Shsul@eecs.umich.edu if (table[nlu].valid) { 1653838Shsul@eecs.umich.edu Addr oldvpn = table[nlu].tag; 1663838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(oldvpn); 1673838Shsul@eecs.umich.edu 1683838Shsul@eecs.umich.edu if (i == lookupTable.end()) 1693838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 1703838Shsul@eecs.umich.edu 1713838Shsul@eecs.umich.edu int index; 1723838Shsul@eecs.umich.edu while ((index = i->second) != nlu) { 1733838Shsul@eecs.umich.edu if (table[index].tag != oldvpn) 1743838Shsul@eecs.umich.edu panic("TLB entry not found in lookupTable"); 1753838Shsul@eecs.umich.edu 1763838Shsul@eecs.umich.edu ++i; 1773838Shsul@eecs.umich.edu } 1783838Shsul@eecs.umich.edu 1793838Shsul@eecs.umich.edu DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); 1803838Shsul@eecs.umich.edu 1813838Shsul@eecs.umich.edu lookupTable.erase(i); 1823838Shsul@eecs.umich.edu } 1833838Shsul@eecs.umich.edu 1845004Sgblack@eecs.umich.edu DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn); 1853838Shsul@eecs.umich.edu 1865004Sgblack@eecs.umich.edu table[nlu] = entry; 1873838Shsul@eecs.umich.edu table[nlu].tag = vaddr.vpn(); 1883838Shsul@eecs.umich.edu table[nlu].valid = true; 1893838Shsul@eecs.umich.edu 1903838Shsul@eecs.umich.edu lookupTable.insert(make_pair(vaddr.vpn(), nlu)); 1913838Shsul@eecs.umich.edu nextnlu(); 1923838Shsul@eecs.umich.edu} 1933838Shsul@eecs.umich.edu 1943838Shsul@eecs.umich.eduvoid 1953838Shsul@eecs.umich.eduTLB::flushAll() 1963838Shsul@eecs.umich.edu{ 1973838Shsul@eecs.umich.edu DPRINTF(TLB, "flushAll\n"); 1985004Sgblack@eecs.umich.edu memset(table, 0, sizeof(TlbEntry[size])); 1994957Sacolyte@umich.edu flushCache(); 2003838Shsul@eecs.umich.edu lookupTable.clear(); 2013838Shsul@eecs.umich.edu nlu = 0; 2023838Shsul@eecs.umich.edu} 2033838Shsul@eecs.umich.edu 2043838Shsul@eecs.umich.eduvoid 2053838Shsul@eecs.umich.eduTLB::flushProcesses() 2063838Shsul@eecs.umich.edu{ 2074957Sacolyte@umich.edu flushCache(); 2083838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.begin(); 2093838Shsul@eecs.umich.edu PageTable::iterator end = lookupTable.end(); 2103838Shsul@eecs.umich.edu while (i != end) { 2113838Shsul@eecs.umich.edu int index = i->second; 2125004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 2135004Sgblack@eecs.umich.edu assert(entry->valid); 2143838Shsul@eecs.umich.edu 2153838Shsul@eecs.umich.edu // we can't increment i after we erase it, so save a copy and 2163838Shsul@eecs.umich.edu // increment it to get the next entry now 2173838Shsul@eecs.umich.edu PageTable::iterator cur = i; 2183838Shsul@eecs.umich.edu ++i; 2193838Shsul@eecs.umich.edu 2205004Sgblack@eecs.umich.edu if (!entry->asma) { 2215004Sgblack@eecs.umich.edu DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, entry->tag, entry->ppn); 2225004Sgblack@eecs.umich.edu entry->valid = false; 2233838Shsul@eecs.umich.edu lookupTable.erase(cur); 2243453Sgblack@eecs.umich.edu } 2253453Sgblack@eecs.umich.edu } 2263838Shsul@eecs.umich.edu} 2272SN/A 2283838Shsul@eecs.umich.eduvoid 2293838Shsul@eecs.umich.eduTLB::flushAddr(Addr addr, uint8_t asn) 2303838Shsul@eecs.umich.edu{ 2314957Sacolyte@umich.edu flushCache(); 2323838Shsul@eecs.umich.edu VAddr vaddr = addr; 2332SN/A 2343838Shsul@eecs.umich.edu PageTable::iterator i = lookupTable.find(vaddr.vpn()); 2353838Shsul@eecs.umich.edu if (i == lookupTable.end()) 2363838Shsul@eecs.umich.edu return; 2372SN/A 2384428Ssaidi@eecs.umich.edu while (i != lookupTable.end() && i->first == vaddr.vpn()) { 2393838Shsul@eecs.umich.edu int index = i->second; 2405004Sgblack@eecs.umich.edu TlbEntry *entry = &table[index]; 2415004Sgblack@eecs.umich.edu assert(entry->valid); 2423453Sgblack@eecs.umich.edu 2435004Sgblack@eecs.umich.edu if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) { 2443838Shsul@eecs.umich.edu DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), 2455004Sgblack@eecs.umich.edu entry->ppn); 2463453Sgblack@eecs.umich.edu 2473838Shsul@eecs.umich.edu // invalidate this entry 2485004Sgblack@eecs.umich.edu entry->valid = false; 2493838Shsul@eecs.umich.edu 2504428Ssaidi@eecs.umich.edu lookupTable.erase(i++); 2514428Ssaidi@eecs.umich.edu } else { 2524428Ssaidi@eecs.umich.edu ++i; 2533838Shsul@eecs.umich.edu } 2543838Shsul@eecs.umich.edu } 2553838Shsul@eecs.umich.edu} 2563838Shsul@eecs.umich.edu 2573838Shsul@eecs.umich.edu 2583838Shsul@eecs.umich.eduvoid 2593838Shsul@eecs.umich.eduTLB::serialize(ostream &os) 2603838Shsul@eecs.umich.edu{ 2613838Shsul@eecs.umich.edu SERIALIZE_SCALAR(size); 2623838Shsul@eecs.umich.edu SERIALIZE_SCALAR(nlu); 2633838Shsul@eecs.umich.edu 2643838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 2655004Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.Entry%d", name(), i)); 2663838Shsul@eecs.umich.edu table[i].serialize(os); 2673838Shsul@eecs.umich.edu } 2683838Shsul@eecs.umich.edu} 2693838Shsul@eecs.umich.edu 2703838Shsul@eecs.umich.eduvoid 2713838Shsul@eecs.umich.eduTLB::unserialize(Checkpoint *cp, const string §ion) 2723838Shsul@eecs.umich.edu{ 2733838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(size); 2743838Shsul@eecs.umich.edu UNSERIALIZE_SCALAR(nlu); 2753838Shsul@eecs.umich.edu 2763838Shsul@eecs.umich.edu for (int i = 0; i < size; i++) { 2775004Sgblack@eecs.umich.edu table[i].unserialize(cp, csprintf("%s.Entry%d", section, i)); 2783838Shsul@eecs.umich.edu if (table[i].valid) { 2793838Shsul@eecs.umich.edu lookupTable.insert(make_pair(table[i].tag, i)); 2803838Shsul@eecs.umich.edu } 2813838Shsul@eecs.umich.edu } 2823838Shsul@eecs.umich.edu} 2833838Shsul@eecs.umich.edu 2843838Shsul@eecs.umich.edu 2853838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 2863838Shsul@eecs.umich.edu// 2873838Shsul@eecs.umich.edu// Alpha ITB 2883838Shsul@eecs.umich.edu// 2893838Shsul@eecs.umich.eduITB::ITB(const std::string &name, int size) 2903838Shsul@eecs.umich.edu : TLB(name, size) 2913838Shsul@eecs.umich.edu{} 2923838Shsul@eecs.umich.edu 2933838Shsul@eecs.umich.edu 2943838Shsul@eecs.umich.eduvoid 2953838Shsul@eecs.umich.eduITB::regStats() 2963838Shsul@eecs.umich.edu{ 2973838Shsul@eecs.umich.edu hits 2983838Shsul@eecs.umich.edu .name(name() + ".hits") 2993838Shsul@eecs.umich.edu .desc("ITB hits"); 3003838Shsul@eecs.umich.edu misses 3013838Shsul@eecs.umich.edu .name(name() + ".misses") 3023838Shsul@eecs.umich.edu .desc("ITB misses"); 3033838Shsul@eecs.umich.edu acv 3043838Shsul@eecs.umich.edu .name(name() + ".acv") 3053838Shsul@eecs.umich.edu .desc("ITB acv"); 3063838Shsul@eecs.umich.edu accesses 3073838Shsul@eecs.umich.edu .name(name() + ".accesses") 3083838Shsul@eecs.umich.edu .desc("ITB accesses"); 3093838Shsul@eecs.umich.edu 3103838Shsul@eecs.umich.edu accesses = hits + misses; 3113838Shsul@eecs.umich.edu} 3123838Shsul@eecs.umich.edu 3133838Shsul@eecs.umich.edu 3143838Shsul@eecs.umich.eduFault 3154967Sacolyte@umich.eduITB::translate(RequestPtr &req, ThreadContext *tc) 3163838Shsul@eecs.umich.edu{ 3174375Sgblack@eecs.umich.edu //If this is a pal pc, then set PHYSICAL 3184375Sgblack@eecs.umich.edu if(FULL_SYSTEM && PcPAL(req->getPC())) 3194375Sgblack@eecs.umich.edu req->setFlags(req->getFlags() | PHYSICAL); 3204375Sgblack@eecs.umich.edu 3213838Shsul@eecs.umich.edu if (PcPAL(req->getPC())) { 3223838Shsul@eecs.umich.edu // strip off PAL PC marker (lsb is 1) 3233838Shsul@eecs.umich.edu req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); 3243838Shsul@eecs.umich.edu hits++; 3253838Shsul@eecs.umich.edu return NoFault; 3263453Sgblack@eecs.umich.edu } 3273453Sgblack@eecs.umich.edu 3283838Shsul@eecs.umich.edu if (req->getFlags() & PHYSICAL) { 3293838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 3303838Shsul@eecs.umich.edu } else { 3313838Shsul@eecs.umich.edu // verify that this is a good virtual address 3323838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 3333838Shsul@eecs.umich.edu acv++; 3343838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 3352SN/A } 3362SN/A 3373838Shsul@eecs.umich.edu 3383838Shsul@eecs.umich.edu // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 3393838Shsul@eecs.umich.edu // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 3403838Shsul@eecs.umich.edu#if ALPHA_TLASER 3414172Ssaidi@eecs.umich.edu if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 3424088Sbinkertn@umich.edu VAddrSpaceEV5(req->getVaddr()) == 2) 3433838Shsul@eecs.umich.edu#else 3444088Sbinkertn@umich.edu if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 3453838Shsul@eecs.umich.edu#endif 3464088Sbinkertn@umich.edu { 3473838Shsul@eecs.umich.edu // only valid in kernel mode 3484172Ssaidi@eecs.umich.edu if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != 3493838Shsul@eecs.umich.edu mode_kernel) { 350555SN/A acv++; 3512532SN/A return new ItbAcvFault(req->getVaddr()); 352555SN/A } 3532SN/A 3543838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 355551SN/A 3561858SN/A#if !ALPHA_TLASER 3573838Shsul@eecs.umich.edu // sign extend the physical address properly 3583838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 3593838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 3603838Shsul@eecs.umich.edu else 3613838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 362924SN/A#endif 363828SN/A 3643838Shsul@eecs.umich.edu } else { 3653838Shsul@eecs.umich.edu // not a physical address: need to look up pte 3664172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 3675004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), 3683838Shsul@eecs.umich.edu asn); 3693838Shsul@eecs.umich.edu 3705004Sgblack@eecs.umich.edu if (!entry) { 3713838Shsul@eecs.umich.edu misses++; 3723838Shsul@eecs.umich.edu return new ItbPageFault(req->getVaddr()); 3733838Shsul@eecs.umich.edu } 3743838Shsul@eecs.umich.edu 3755004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 3763838Shsul@eecs.umich.edu (VAddr(req->getVaddr()).offset() 3773838Shsul@eecs.umich.edu & ~3)); 3783838Shsul@eecs.umich.edu 3793838Shsul@eecs.umich.edu // check permissions for this access 3805004Sgblack@eecs.umich.edu if (!(entry->xre & 3814172Ssaidi@eecs.umich.edu (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { 3823838Shsul@eecs.umich.edu // instruction access fault 3833838Shsul@eecs.umich.edu acv++; 3843838Shsul@eecs.umich.edu return new ItbAcvFault(req->getVaddr()); 3853838Shsul@eecs.umich.edu } 3863838Shsul@eecs.umich.edu 3873838Shsul@eecs.umich.edu hits++; 3883838Shsul@eecs.umich.edu } 3893838Shsul@eecs.umich.edu } 3903838Shsul@eecs.umich.edu 3913838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 3923838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 3933838Shsul@eecs.umich.edu return genMachineCheckFault(); 3943838Shsul@eecs.umich.edu 3953838Shsul@eecs.umich.edu return checkCacheability(req); 3963838Shsul@eecs.umich.edu 3973838Shsul@eecs.umich.edu} 3983838Shsul@eecs.umich.edu 3993838Shsul@eecs.umich.edu/////////////////////////////////////////////////////////////////////// 4003838Shsul@eecs.umich.edu// 4013838Shsul@eecs.umich.edu// Alpha DTB 4023838Shsul@eecs.umich.edu// 4033838Shsul@eecs.umich.edu DTB::DTB(const std::string &name, int size) 4043838Shsul@eecs.umich.edu : TLB(name, size) 4053838Shsul@eecs.umich.edu{} 4063838Shsul@eecs.umich.edu 4073838Shsul@eecs.umich.eduvoid 4083838Shsul@eecs.umich.eduDTB::regStats() 4093838Shsul@eecs.umich.edu{ 4103838Shsul@eecs.umich.edu read_hits 4113838Shsul@eecs.umich.edu .name(name() + ".read_hits") 4123838Shsul@eecs.umich.edu .desc("DTB read hits") 4133838Shsul@eecs.umich.edu ; 4143838Shsul@eecs.umich.edu 4153838Shsul@eecs.umich.edu read_misses 4163838Shsul@eecs.umich.edu .name(name() + ".read_misses") 4173838Shsul@eecs.umich.edu .desc("DTB read misses") 4183838Shsul@eecs.umich.edu ; 4193838Shsul@eecs.umich.edu 4203838Shsul@eecs.umich.edu read_acv 4213838Shsul@eecs.umich.edu .name(name() + ".read_acv") 4223838Shsul@eecs.umich.edu .desc("DTB read access violations") 4233838Shsul@eecs.umich.edu ; 4243838Shsul@eecs.umich.edu 4253838Shsul@eecs.umich.edu read_accesses 4263838Shsul@eecs.umich.edu .name(name() + ".read_accesses") 4273838Shsul@eecs.umich.edu .desc("DTB read accesses") 4283838Shsul@eecs.umich.edu ; 4293838Shsul@eecs.umich.edu 4303838Shsul@eecs.umich.edu write_hits 4313838Shsul@eecs.umich.edu .name(name() + ".write_hits") 4323838Shsul@eecs.umich.edu .desc("DTB write hits") 4333838Shsul@eecs.umich.edu ; 4343838Shsul@eecs.umich.edu 4353838Shsul@eecs.umich.edu write_misses 4363838Shsul@eecs.umich.edu .name(name() + ".write_misses") 4373838Shsul@eecs.umich.edu .desc("DTB write misses") 4383838Shsul@eecs.umich.edu ; 4393838Shsul@eecs.umich.edu 4403838Shsul@eecs.umich.edu write_acv 4413838Shsul@eecs.umich.edu .name(name() + ".write_acv") 4423838Shsul@eecs.umich.edu .desc("DTB write access violations") 4433838Shsul@eecs.umich.edu ; 4443838Shsul@eecs.umich.edu 4453838Shsul@eecs.umich.edu write_accesses 4463838Shsul@eecs.umich.edu .name(name() + ".write_accesses") 4473838Shsul@eecs.umich.edu .desc("DTB write accesses") 4483838Shsul@eecs.umich.edu ; 4493838Shsul@eecs.umich.edu 4503838Shsul@eecs.umich.edu hits 4513838Shsul@eecs.umich.edu .name(name() + ".hits") 4523838Shsul@eecs.umich.edu .desc("DTB hits") 4533838Shsul@eecs.umich.edu ; 4543838Shsul@eecs.umich.edu 4553838Shsul@eecs.umich.edu misses 4563838Shsul@eecs.umich.edu .name(name() + ".misses") 4573838Shsul@eecs.umich.edu .desc("DTB misses") 4583838Shsul@eecs.umich.edu ; 4593838Shsul@eecs.umich.edu 4603838Shsul@eecs.umich.edu acv 4613838Shsul@eecs.umich.edu .name(name() + ".acv") 4623838Shsul@eecs.umich.edu .desc("DTB access violations") 4633838Shsul@eecs.umich.edu ; 4643838Shsul@eecs.umich.edu 4653838Shsul@eecs.umich.edu accesses 4663838Shsul@eecs.umich.edu .name(name() + ".accesses") 4673838Shsul@eecs.umich.edu .desc("DTB accesses") 4683838Shsul@eecs.umich.edu ; 4693838Shsul@eecs.umich.edu 4703838Shsul@eecs.umich.edu hits = read_hits + write_hits; 4713838Shsul@eecs.umich.edu misses = read_misses + write_misses; 4723838Shsul@eecs.umich.edu acv = read_acv + write_acv; 4733838Shsul@eecs.umich.edu accesses = read_accesses + write_accesses; 4743838Shsul@eecs.umich.edu} 4753838Shsul@eecs.umich.edu 4763838Shsul@eecs.umich.eduFault 4774967Sacolyte@umich.eduDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 4783838Shsul@eecs.umich.edu{ 4793838Shsul@eecs.umich.edu Addr pc = tc->readPC(); 4803838Shsul@eecs.umich.edu 4813838Shsul@eecs.umich.edu mode_type mode = 4824172Ssaidi@eecs.umich.edu (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); 4833838Shsul@eecs.umich.edu 4843838Shsul@eecs.umich.edu 4853838Shsul@eecs.umich.edu /** 4863838Shsul@eecs.umich.edu * Check for alignment faults 4873838Shsul@eecs.umich.edu */ 4883838Shsul@eecs.umich.edu if (req->getVaddr() & (req->getSize() - 1)) { 4893838Shsul@eecs.umich.edu DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(), 4903838Shsul@eecs.umich.edu req->getSize()); 4913838Shsul@eecs.umich.edu uint64_t flags = write ? MM_STAT_WR_MASK : 0; 4923838Shsul@eecs.umich.edu return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags); 4933838Shsul@eecs.umich.edu } 4943838Shsul@eecs.umich.edu 4953838Shsul@eecs.umich.edu if (PcPAL(pc)) { 4963838Shsul@eecs.umich.edu mode = (req->getFlags() & ALTMODE) ? 4973838Shsul@eecs.umich.edu (mode_type)ALT_MODE_AM( 4984172Ssaidi@eecs.umich.edu tc->readMiscRegNoEffect(IPR_ALT_MODE)) 4993838Shsul@eecs.umich.edu : mode_kernel; 5003838Shsul@eecs.umich.edu } 5013838Shsul@eecs.umich.edu 5023838Shsul@eecs.umich.edu if (req->getFlags() & PHYSICAL) { 5033838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr()); 5043838Shsul@eecs.umich.edu } else { 5053838Shsul@eecs.umich.edu // verify that this is a good virtual address 5063838Shsul@eecs.umich.edu if (!validVirtualAddress(req->getVaddr())) { 5073838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 5083838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5093838Shsul@eecs.umich.edu MM_STAT_BAD_VA_MASK | 5103838Shsul@eecs.umich.edu MM_STAT_ACV_MASK; 5113838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5123838Shsul@eecs.umich.edu } 5133838Shsul@eecs.umich.edu 5143838Shsul@eecs.umich.edu // Check for "superpage" mapping 5153838Shsul@eecs.umich.edu#if ALPHA_TLASER 5164172Ssaidi@eecs.umich.edu if ((MCSR_SP(tc->readMiscRegNoEffect(IPR_MCSR)) & 2) && 5174088Sbinkertn@umich.edu VAddrSpaceEV5(req->getVaddr()) == 2) 5183838Shsul@eecs.umich.edu#else 5194088Sbinkertn@umich.edu if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) 5203838Shsul@eecs.umich.edu#endif 5214088Sbinkertn@umich.edu { 5223838Shsul@eecs.umich.edu 5233838Shsul@eecs.umich.edu // only valid in kernel mode 5244172Ssaidi@eecs.umich.edu if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != 5253838Shsul@eecs.umich.edu mode_kernel) { 5263838Shsul@eecs.umich.edu if (write) { write_acv++; } else { read_acv++; } 5273838Shsul@eecs.umich.edu uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | 5283838Shsul@eecs.umich.edu MM_STAT_ACV_MASK); 5293838Shsul@eecs.umich.edu return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 5303838Shsul@eecs.umich.edu } 5313838Shsul@eecs.umich.edu 5323838Shsul@eecs.umich.edu req->setPaddr(req->getVaddr() & PAddrImplMask); 5333838Shsul@eecs.umich.edu 5343838Shsul@eecs.umich.edu#if !ALPHA_TLASER 5353838Shsul@eecs.umich.edu // sign extend the physical address properly 5363838Shsul@eecs.umich.edu if (req->getPaddr() & PAddrUncachedBit40) 5373838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); 5383838Shsul@eecs.umich.edu else 5393838Shsul@eecs.umich.edu req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); 5403838Shsul@eecs.umich.edu#endif 5413838Shsul@eecs.umich.edu 5423838Shsul@eecs.umich.edu } else { 5433838Shsul@eecs.umich.edu if (write) 5443838Shsul@eecs.umich.edu write_accesses++; 5453838Shsul@eecs.umich.edu else 5463838Shsul@eecs.umich.edu read_accesses++; 5473838Shsul@eecs.umich.edu 5484172Ssaidi@eecs.umich.edu int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 5493838Shsul@eecs.umich.edu 5503838Shsul@eecs.umich.edu // not a physical address: need to look up pte 5515004Sgblack@eecs.umich.edu TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn); 5523838Shsul@eecs.umich.edu 5535004Sgblack@eecs.umich.edu if (!entry) { 5543838Shsul@eecs.umich.edu // page fault 5553838Shsul@eecs.umich.edu if (write) { write_misses++; } else { read_misses++; } 5563838Shsul@eecs.umich.edu uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | 5573838Shsul@eecs.umich.edu MM_STAT_DTB_MISS_MASK; 5583838Shsul@eecs.umich.edu return (req->getFlags() & VPTE) ? 5593838Shsul@eecs.umich.edu (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(), 5603838Shsul@eecs.umich.edu flags)) : 5613838Shsul@eecs.umich.edu (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(), 5623838Shsul@eecs.umich.edu flags)); 5633838Shsul@eecs.umich.edu } 5643838Shsul@eecs.umich.edu 5655004Sgblack@eecs.umich.edu req->setPaddr((entry->ppn << PageShift) + 5663838Shsul@eecs.umich.edu VAddr(req->getVaddr()).offset()); 5673838Shsul@eecs.umich.edu 5683838Shsul@eecs.umich.edu if (write) { 5695004Sgblack@eecs.umich.edu if (!(entry->xwe & MODE2MASK(mode))) { 5703838Shsul@eecs.umich.edu // declare the instruction access fault 5713838Shsul@eecs.umich.edu write_acv++; 5723838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5733838Shsul@eecs.umich.edu MM_STAT_ACV_MASK | 5745004Sgblack@eecs.umich.edu (entry->fonw ? MM_STAT_FONW_MASK : 0); 5753838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5763838Shsul@eecs.umich.edu } 5775004Sgblack@eecs.umich.edu if (entry->fonw) { 5783838Shsul@eecs.umich.edu write_acv++; 5793838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_WR_MASK | 5803838Shsul@eecs.umich.edu MM_STAT_FONW_MASK; 5813838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5823838Shsul@eecs.umich.edu } 5833453Sgblack@eecs.umich.edu } else { 5845004Sgblack@eecs.umich.edu if (!(entry->xre & MODE2MASK(mode))) { 5853838Shsul@eecs.umich.edu read_acv++; 5863838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_ACV_MASK | 5875004Sgblack@eecs.umich.edu (entry->fonr ? MM_STAT_FONR_MASK : 0); 5883838Shsul@eecs.umich.edu return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags); 5893453Sgblack@eecs.umich.edu } 5905004Sgblack@eecs.umich.edu if (entry->fonr) { 5913838Shsul@eecs.umich.edu read_acv++; 5923838Shsul@eecs.umich.edu uint64_t flags = MM_STAT_FONR_MASK; 5933838Shsul@eecs.umich.edu return new DtbPageFault(req->getVaddr(), req->getFlags(), flags); 5943453Sgblack@eecs.umich.edu } 5952SN/A } 5962SN/A } 597551SN/A 5983838Shsul@eecs.umich.edu if (write) 5993838Shsul@eecs.umich.edu write_hits++; 6003838Shsul@eecs.umich.edu else 6013838Shsul@eecs.umich.edu read_hits++; 6022SN/A } 6032SN/A 6043838Shsul@eecs.umich.edu // check that the physical address is ok (catch bad physical addresses) 6053838Shsul@eecs.umich.edu if (req->getPaddr() & ~PAddrImplMask) 6063838Shsul@eecs.umich.edu return genMachineCheckFault(); 607551SN/A 6083838Shsul@eecs.umich.edu return checkCacheability(req); 6093838Shsul@eecs.umich.edu} 6103453Sgblack@eecs.umich.edu 6115004Sgblack@eecs.umich.eduTlbEntry & 6123838Shsul@eecs.umich.eduTLB::index(bool advance) 6133838Shsul@eecs.umich.edu{ 6145004Sgblack@eecs.umich.edu TlbEntry *entry = &table[nlu]; 6153453Sgblack@eecs.umich.edu 6163838Shsul@eecs.umich.edu if (advance) 6173838Shsul@eecs.umich.edu nextnlu(); 6183453Sgblack@eecs.umich.edu 6195004Sgblack@eecs.umich.edu return *entry; 6203838Shsul@eecs.umich.edu} 6213453Sgblack@eecs.umich.edu 6224088Sbinkertn@umich.edu/* end namespace AlphaISA */ } 6234088Sbinkertn@umich.edu 6244762Snate@binkert.orgAlphaISA::ITB * 6254762Snate@binkert.orgAlphaITBParams::create() 6263838Shsul@eecs.umich.edu{ 6274762Snate@binkert.org return new AlphaISA::ITB(name, size); 6283838Shsul@eecs.umich.edu} 6293453Sgblack@eecs.umich.edu 6304762Snate@binkert.orgAlphaISA::DTB * 6314762Snate@binkert.orgAlphaDTBParams::create() 6323838Shsul@eecs.umich.edu{ 6334762Snate@binkert.org return new AlphaISA::DTB(name, size); 6343838Shsul@eecs.umich.edu} 635