registers.hh revision 6019 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ALPHA_REGFILE_HH__
32#define __ARCH_ALPHA_REGFILE_HH__
33
34#include "arch/alpha/isa_traits.hh"
35#include "arch/alpha/floatregfile.hh"
36#include "arch/alpha/intregfile.hh"
37#include "arch/alpha/miscregfile.hh"
38#include "arch/alpha/types.hh"
39#include "sim/faults.hh"
40
41#include <string>
42
43//XXX These should be implemented by someone who knows the alpha stuff better
44
45class Checkpoint;
46class ThreadContext;
47
48namespace AlphaISA
49{
50
51    class RegFile {
52
53      protected:
54        Addr pc;			// program counter
55        Addr npc;			// next-cycle program counter
56        Addr nnpc;
57
58      public:
59        Addr readPC()
60        {
61            return pc;
62        }
63
64        void setPC(Addr val)
65        {
66            pc = val;
67        }
68
69        Addr readNextPC()
70        {
71            return npc;
72        }
73
74        void setNextPC(Addr val)
75        {
76            npc = val;
77        }
78
79        Addr readNextNPC()
80        {
81            return npc + sizeof(MachInst);
82        }
83
84        void setNextNPC(Addr val)
85        { }
86
87      protected:
88        IntRegFile intRegFile;		// (signed) integer register file
89        FloatRegFile floatRegFile;	// floating point register file
90        MiscRegFile miscRegFile;	// control register file
91
92      public:
93
94#if FULL_SYSTEM
95        int intrflag;			// interrupt flag
96        inline int instAsid()
97        { return miscRegFile.getInstAsid(); }
98        inline int dataAsid()
99        { return miscRegFile.getDataAsid(); }
100#endif // FULL_SYSTEM
101
102        void clear()
103        {
104            intRegFile.clear();
105            floatRegFile.clear();
106            miscRegFile.clear();
107        }
108
109        MiscReg readMiscRegNoEffect(int miscReg)
110        {
111            return miscRegFile.readRegNoEffect(miscReg);
112        }
113
114        MiscReg readMiscReg(int miscReg, ThreadContext *tc)
115        {
116            return miscRegFile.readReg(miscReg, tc);
117        }
118
119        void setMiscRegNoEffect(int miscReg, const MiscReg &val)
120        {
121            miscRegFile.setRegNoEffect(miscReg, val);
122        }
123
124        void setMiscReg(int miscReg, const MiscReg &val,
125                ThreadContext * tc)
126        {
127            miscRegFile.setReg(miscReg, val, tc);
128        }
129
130        FloatReg readFloatReg(int floatReg)
131        {
132            return floatRegFile.d[floatReg];
133        }
134
135        FloatReg readFloatReg(int floatReg, int width)
136        {
137            return readFloatReg(floatReg);
138        }
139
140        FloatRegBits readFloatRegBits(int floatReg)
141        {
142            return floatRegFile.q[floatReg];
143        }
144
145        FloatRegBits readFloatRegBits(int floatReg, int width)
146        {
147            return readFloatRegBits(floatReg);
148        }
149
150        void setFloatReg(int floatReg, const FloatReg &val)
151        {
152            floatRegFile.d[floatReg] = val;
153        }
154
155        void setFloatReg(int floatReg, const FloatReg &val, int width)
156        {
157            setFloatReg(floatReg, val);
158        }
159
160        void setFloatRegBits(int floatReg, const FloatRegBits &val)
161        {
162            floatRegFile.q[floatReg] = val;
163        }
164
165        void setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
166        {
167            setFloatRegBits(floatReg, val);
168        }
169
170        IntReg readIntReg(int intReg)
171        {
172            return intRegFile.readReg(intReg);
173        }
174
175        void setIntReg(int intReg, const IntReg &val)
176        {
177            intRegFile.setReg(intReg, val);
178        }
179
180        void serialize(std::ostream &os);
181        void unserialize(Checkpoint *cp, const std::string &section);
182
183        void changeContext(RegContextParam param, RegContextVal val)
184        {
185            //This would be an alternative place to call/implement
186            //the swapPALShadow function
187        }
188    };
189
190    static inline int flattenIntIndex(ThreadContext * tc, int reg)
191    {
192        return reg;
193    }
194
195    static inline int flattenFloatIndex(ThreadContext * tc, int reg)
196    {
197        return reg;
198    }
199
200    void copyRegs(ThreadContext *src, ThreadContext *dest);
201
202    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
203} // namespace AlphaISA
204
205#endif
206