registers.hh revision 9046
12440SN/A/* 22440SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32440SN/A * All rights reserved. 42440SN/A * 52440SN/A * Redistribution and use in source and binary forms, with or without 62440SN/A * modification, are permitted provided that the following conditions are 72440SN/A * met: redistributions of source code must retain the above copyright 82440SN/A * notice, this list of conditions and the following disclaimer; 92440SN/A * redistributions in binary form must reproduce the above copyright 102440SN/A * notice, this list of conditions and the following disclaimer in the 112440SN/A * documentation and/or other materials provided with the distribution; 122440SN/A * neither the name of the copyright holders nor the names of its 132440SN/A * contributors may be used to endorse or promote products derived from 142440SN/A * this software without specific prior written permission. 152440SN/A * 162440SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172440SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182440SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192440SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202440SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212440SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222440SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232440SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242440SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252440SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262440SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Gabe Black 292440SN/A */ 302440SN/A 316329Sgblack@eecs.umich.edu#ifndef __ARCH_ALPHA_REGISTERS_HH__ 326329Sgblack@eecs.umich.edu#define __ARCH_ALPHA_REGISTERS_HH__ 332440SN/A 348961Sgblack@eecs.umich.edu#include "arch/alpha/generated/max_inst_regs.hh" 356327SN/A#include "arch/alpha/ipr.hh" 366329Sgblack@eecs.umich.edu#include "base/types.hh" 372440SN/A 385569SN/Anamespace AlphaISA { 392972SN/A 406329Sgblack@eecs.umich.eduusing AlphaISAInst::MaxInstSrcRegs; 416329Sgblack@eecs.umich.eduusing AlphaISAInst::MaxInstDestRegs; 426327SN/A 439046SAli.Saidi@ARM.com// Locked read/write flags are can't be detected by the ISA parser 449046SAli.Saidi@ARM.comconst int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1; 459046SAli.Saidi@ARM.com 466329Sgblack@eecs.umich.edutypedef uint8_t RegIndex; 476329Sgblack@eecs.umich.edutypedef uint64_t IntReg; 486327SN/A 496329Sgblack@eecs.umich.edu// floating point register file entry type 506329Sgblack@eecs.umich.edutypedef double FloatReg; 516329Sgblack@eecs.umich.edutypedef uint64_t FloatRegBits; 526327SN/A 536329Sgblack@eecs.umich.edu// control register file contents 546329Sgblack@eecs.umich.edutypedef uint64_t MiscReg; 556327SN/A 566329Sgblack@eecs.umich.eduunion AnyReg 576329Sgblack@eecs.umich.edu{ 586329Sgblack@eecs.umich.edu IntReg intreg; 596329Sgblack@eecs.umich.edu FloatReg fpreg; 606329Sgblack@eecs.umich.edu MiscReg ctrlreg; 616329Sgblack@eecs.umich.edu}; 626321SN/A 636329Sgblack@eecs.umich.eduenum MiscRegIndex 646329Sgblack@eecs.umich.edu{ 656329Sgblack@eecs.umich.edu MISCREG_FPCR = NumInternalProcRegs, 666329Sgblack@eecs.umich.edu MISCREG_UNIQ, 676329Sgblack@eecs.umich.edu MISCREG_LOCKFLAG, 686329Sgblack@eecs.umich.edu MISCREG_LOCKADDR, 697699Sgblack@eecs.umich.edu MISCREG_INTR, 707699Sgblack@eecs.umich.edu NUM_MISCREGS 716329Sgblack@eecs.umich.edu}; 725569SN/A 736329Sgblack@eecs.umich.edu// semantically meaningful register indices 746329Sgblack@eecs.umich.educonst RegIndex ZeroReg = 31; // architecturally meaningful 756329Sgblack@eecs.umich.edu// the rest of these depend on the ABI 766329Sgblack@eecs.umich.educonst RegIndex StackPointerReg = 30; 776329Sgblack@eecs.umich.educonst RegIndex GlobalPointerReg = 29; 786329Sgblack@eecs.umich.educonst RegIndex ProcedureValueReg = 27; 796329Sgblack@eecs.umich.educonst RegIndex ReturnAddressReg = 26; 806329Sgblack@eecs.umich.educonst RegIndex ReturnValueReg = 0; 816329Sgblack@eecs.umich.educonst RegIndex FramePointerReg = 15; 826329Sgblack@eecs.umich.edu 836329Sgblack@eecs.umich.educonst RegIndex SyscallNumReg = 0; 846329Sgblack@eecs.umich.educonst RegIndex FirstArgumentReg = 16; 856329Sgblack@eecs.umich.educonst RegIndex SyscallPseudoReturnReg = 20; 866329Sgblack@eecs.umich.educonst RegIndex SyscallSuccessReg = 19; 876329Sgblack@eecs.umich.edu 886329Sgblack@eecs.umich.educonst int NumIntArchRegs = 32; 896329Sgblack@eecs.umich.educonst int NumPALShadowRegs = 8; 906329Sgblack@eecs.umich.educonst int NumFloatArchRegs = 32; 917699Sgblack@eecs.umich.educonst int NumMiscArchRegs = NUM_MISCREGS; 926329Sgblack@eecs.umich.edu 936329Sgblack@eecs.umich.educonst int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 946329Sgblack@eecs.umich.educonst int NumFloatRegs = NumFloatArchRegs; 956329Sgblack@eecs.umich.educonst int NumMiscRegs = NumMiscArchRegs; 966329Sgblack@eecs.umich.edu 976329Sgblack@eecs.umich.educonst int TotalNumRegs = 987699Sgblack@eecs.umich.edu NumIntRegs + NumFloatRegs + NumMiscRegs; 996329Sgblack@eecs.umich.edu 1006329Sgblack@eecs.umich.educonst int TotalDataRegs = NumIntRegs + NumFloatRegs; 1016329Sgblack@eecs.umich.edu 1026329Sgblack@eecs.umich.edu// These enumerate all the registers for dependence tracking. 1036329Sgblack@eecs.umich.eduenum DependenceTags { 1046329Sgblack@eecs.umich.edu // 0..31 are the integer regs 0..31 1056329Sgblack@eecs.umich.edu // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 1066329Sgblack@eecs.umich.edu FP_Base_DepTag = 40, 1077649Sminkyu.jeong@arm.com Ctrl_Base_DepTag = 72, 1087649Sminkyu.jeong@arm.com Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs + NumInternalProcRegs 1096329Sgblack@eecs.umich.edu}; 1105569SN/A 1112440SN/A} // namespace AlphaISA 1122440SN/A 1135569SN/A#endif // __ARCH_ALPHA_REGFILE_HH__ 114