registers.hh revision 2972
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_ALPHA_REGFILE_HH__ 32#define __ARCH_ALPHA_REGFILE_HH__ 33 34#include "arch/alpha/types.hh" 35#include "arch/alpha/isa_traits.hh" 36#include "sim/faults.hh" 37 38#include <string> 39 40//XXX These should be implemented by someone who knows the alpha stuff better 41 42class Checkpoint; 43class ThreadContext; 44 45namespace AlphaISA 46{ 47 48 class IntRegFile 49 { 50 protected: 51 IntReg regs[NumIntRegs]; 52 53 public: 54 55 IntReg readReg(int intReg) 56 { 57 return regs[intReg]; 58 } 59 60 Fault setReg(int intReg, const IntReg &val) 61 { 62 regs[intReg] = val; 63 return NoFault; 64 } 65 66 void serialize(std::ostream &os); 67 68 void unserialize(Checkpoint *cp, const std::string §ion); 69 70 void clear() 71 { bzero(regs, sizeof(regs)); } 72 }; 73 74 class FloatRegFile 75 { 76 public: 77 78 union { 79 uint64_t q[NumFloatRegs]; // integer qword view 80 double d[NumFloatRegs]; // double-precision floating point view 81 }; 82 83 void serialize(std::ostream &os); 84 85 void unserialize(Checkpoint *cp, const std::string §ion); 86 87 void clear() 88 { bzero(d, sizeof(d)); } 89 }; 90 91 class MiscRegFile { 92 protected: 93 uint64_t fpcr; // floating point condition codes 94 uint64_t uniq; // process-unique register 95 bool lock_flag; // lock flag for LL/SC 96 Addr lock_addr; // lock address for LL/SC 97 98 public: 99 MiscReg readReg(int misc_reg); 100 101 MiscReg readRegWithEffect(int misc_reg, Fault &fault, 102 ThreadContext *tc); 103 104 //These functions should be removed once the simplescalar cpu model 105 //has been replaced. 106 int getInstAsid(); 107 int getDataAsid(); 108 109 Fault setReg(int misc_reg, const MiscReg &val); 110 111 Fault setRegWithEffect(int misc_reg, const MiscReg &val, 112 ThreadContext *tc); 113 114 void clear() 115 { 116 fpcr = uniq = 0; 117 lock_flag = 0; 118 lock_addr = 0; 119 } 120 121 void serialize(std::ostream &os); 122 123 void unserialize(Checkpoint *cp, const std::string §ion); 124#if FULL_SYSTEM 125 protected: 126 typedef uint64_t InternalProcReg; 127 128 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 129 130 private: 131 InternalProcReg readIpr(int idx, Fault &fault, ThreadContext *tc); 132 133 Fault setIpr(int idx, InternalProcReg val, ThreadContext *tc); 134#endif 135 friend class RegFile; 136 }; 137 138 class RegFile { 139 140 protected: 141 Addr pc; // program counter 142 Addr npc; // next-cycle program counter 143 Addr nnpc; 144 145 public: 146 Addr readPC() 147 { 148 return pc; 149 } 150 151 void setPC(Addr val) 152 { 153 pc = val; 154 } 155 156 Addr readNextPC() 157 { 158 return npc; 159 } 160 161 void setNextPC(Addr val) 162 { 163 npc = val; 164 } 165 166 Addr readNextNPC() 167 { 168 return nnpc; 169 } 170 171 void setNextNPC(Addr val) 172 { 173 nnpc = val; 174 } 175 176 protected: 177 IntRegFile intRegFile; // (signed) integer register file 178 FloatRegFile floatRegFile; // floating point register file 179 MiscRegFile miscRegFile; // control register file 180 181 public: 182 183#if FULL_SYSTEM 184 int intrflag; // interrupt flag 185 inline int instAsid() 186 { return miscRegFile.getInstAsid(); } 187 inline int dataAsid() 188 { return miscRegFile.getDataAsid(); } 189#endif // FULL_SYSTEM 190 191 void clear() 192 { 193 intRegFile.clear(); 194 floatRegFile.clear(); 195 miscRegFile.clear(); 196 } 197 198 MiscReg readMiscReg(int miscReg) 199 { 200 return miscRegFile.readReg(miscReg); 201 } 202 203 MiscReg readMiscRegWithEffect(int miscReg, 204 Fault &fault, ThreadContext *tc) 205 { 206 fault = NoFault; 207 return miscRegFile.readRegWithEffect(miscReg, fault, tc); 208 } 209 210 Fault setMiscReg(int miscReg, const MiscReg &val) 211 { 212 return miscRegFile.setReg(miscReg, val); 213 } 214 215 Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, 216 ThreadContext * tc) 217 { 218 return miscRegFile.setRegWithEffect(miscReg, val, tc); 219 } 220 221 FloatReg readFloatReg(int floatReg) 222 { 223 return floatRegFile.d[floatReg]; 224 } 225 226 FloatReg readFloatReg(int floatReg, int width) 227 { 228 return readFloatReg(floatReg); 229 } 230 231 FloatRegBits readFloatRegBits(int floatReg) 232 { 233 return floatRegFile.q[floatReg]; 234 } 235 236 FloatRegBits readFloatRegBits(int floatReg, int width) 237 { 238 return readFloatRegBits(floatReg); 239 } 240 241 Fault setFloatReg(int floatReg, const FloatReg &val) 242 { 243 floatRegFile.d[floatReg] = val; 244 return NoFault; 245 } 246 247 Fault setFloatReg(int floatReg, const FloatReg &val, int width) 248 { 249 return setFloatReg(floatReg, val); 250 } 251 252 Fault setFloatRegBits(int floatReg, const FloatRegBits &val) 253 { 254 floatRegFile.q[floatReg] = val; 255 return NoFault; 256 } 257 258 Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) 259 { 260 return setFloatRegBits(floatReg, val); 261 } 262 263 IntReg readIntReg(int intReg) 264 { 265 return intRegFile.readReg(intReg); 266 } 267 268 Fault setIntReg(int intReg, const IntReg &val) 269 { 270 return intRegFile.setReg(intReg, val); 271 } 272 273 void serialize(std::ostream &os); 274 void unserialize(Checkpoint *cp, const std::string §ion); 275 276 void changeContext(RegContextParam param, RegContextVal val) 277 { 278 //This would be an alternative place to call/implement 279 //the swapPALShadow function 280 } 281 }; 282 283 void copyRegs(ThreadContext *src, ThreadContext *dest); 284 285 void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 286 287#if FULL_SYSTEM 288 void copyIprs(ThreadContext *src, ThreadContext *dest); 289#endif 290} // namespace AlphaISA 291 292#endif 293