registers.hh revision 2440
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_ALPHA_REGISTERFILE_HH__ 30#define __ARCH_ALPHA_REGISTERFILE_HH__ 31 32#include "arch/alpha/types.hh" 33#include "arch/alpha/constants.hh" 34#include "sim/faults.hh" 35 36class Checkpoint; 37 38namespace AlphaISA 39{ 40 41 typedef IntReg IntRegFile[NumIntRegs]; 42 43 typedef union { 44 uint64_t q[NumFloatRegs]; // integer qword view 45 double d[NumFloatRegs]; // double-precision floating point view 46 } FloatRegFile; 47 48 class MiscRegFile { 49 protected: 50 uint64_t fpcr; // floating point condition codes 51 uint64_t uniq; // process-unique register 52 bool lock_flag; // lock flag for LL/SC 53 Addr lock_addr; // lock address for LL/SC 54 55 public: 56 MiscReg readReg(int misc_reg); 57 58 //These functions should be removed once the simplescalar cpu model 59 //has been replaced. 60 int getInstAsid(); 61 int getDataAsid(); 62 63 MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); 64 65 Fault setReg(int misc_reg, const MiscReg &val); 66 67 Fault setRegWithEffect(int misc_reg, const MiscReg &val, 68 ExecContext *xc); 69 70 void copyMiscRegs(ExecContext *xc); 71 72#if FULL_SYSTEM 73 protected: 74 typedef uint64_t InternalProcReg; 75 76 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 77 78 private: 79 InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc); 80 81 Fault setIpr(int idx, InternalProcReg val, ExecContext *xc); 82 83 void copyIprs(ExecContext *xc); 84#endif 85 friend class RegFile; 86 }; 87 88 struct RegFile { 89 IntRegFile intRegFile; // (signed) integer register file 90 FloatRegFile floatRegFile; // floating point register file 91 MiscRegFile miscRegs; // control register file 92 Addr pc; // program counter 93 Addr npc; // next-cycle program counter 94 Addr nnpc; 95 96#if FULL_SYSTEM 97 int intrflag; // interrupt flag 98 inline int instAsid() 99 { return miscRegs.getInstAsid(); } 100 inline int dataAsid() 101 { return miscRegs.getDataAsid(); } 102#endif // FULL_SYSTEM 103 104 void serialize(std::ostream &os); 105 void unserialize(Checkpoint *cp, const std::string §ion); 106 }; 107 108} // namespace AlphaISA 109 110#endif 111