process.hh revision 11851
12207SN/A/* 22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32207SN/A * All rights reserved. 42207SN/A * 52207SN/A * Redistribution and use in source and binary forms, with or without 62207SN/A * modification, are permitted provided that the following conditions are 72207SN/A * met: redistributions of source code must retain the above copyright 82207SN/A * notice, this list of conditions and the following disclaimer; 92207SN/A * redistributions in binary form must reproduce the above copyright 102207SN/A * notice, this list of conditions and the following disclaimer in the 112207SN/A * documentation and/or other materials provided with the distribution; 122207SN/A * neither the name of the copyright holders nor the names of its 132207SN/A * contributors may be used to endorse or promote products derived from 142207SN/A * this software without specific prior written permission. 152207SN/A * 162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Ali Saidi 302207SN/A */ 312207SN/A 325569Snate@binkert.org#ifndef __ARCH_ALPHA_PROCESS_HH__ 335569Snate@binkert.org#define __ARCH_ALPHA_PROCESS_HH__ 342207SN/A 3511800Sbrandon.potter@amd.com#include "mem/page_table.hh" 362474SN/A#include "sim/process.hh" 372207SN/A 3811851Sbrandon.potter@amd.comclass AlphaProcess : public Process 392207SN/A{ 407532Ssteve.reinhardt@amd.com private: 417532Ssteve.reinhardt@amd.com void setupASNReg(); 427532Ssteve.reinhardt@amd.com 432474SN/A protected: 4411851Sbrandon.potter@amd.com AlphaProcess(ProcessParams *params, ObjectFile *objFile); 452207SN/A 4611168Sandreas.hansson@arm.com void loadState(CheckpointIn &cp) override; 4711169Sandreas.hansson@arm.com void initState() override; 485759Shsul@eecs.umich.edu 495759Shsul@eecs.umich.edu void argsInit(int intSize, int pageSize); 505958Sgblack@eecs.umich.edu 515958Sgblack@eecs.umich.edu public: 5211169Sandreas.hansson@arm.com AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override; 539552Sandreas.hansson@arm.com /// Explicitly import the otherwise hidden getSyscallArg 5411851Sbrandon.potter@amd.com using Process::getSyscallArg; 5511169Sandreas.hansson@arm.com void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) override; 5611169Sandreas.hansson@arm.com void setSyscallReturn(ThreadContext *tc, 5711169Sandreas.hansson@arm.com SyscallReturn return_value) override; 5811386Ssteve.reinhardt@amd.com 5911851Sbrandon.potter@amd.com // override default implementation in Process as the mmap 6011386Ssteve.reinhardt@amd.com // region for Alpha platforms grows upward 6111386Ssteve.reinhardt@amd.com virtual bool mmapGrowsDown() const override { return false; } 622474SN/A}; 632474SN/A 6410299Salexandru.dutu@amd.com/* No architectural page table defined for this ISA */ 6510299Salexandru.dutu@amd.comtypedef NoArchPageTable ArchPageTable; 6610299Salexandru.dutu@amd.com 675569Snate@binkert.org#endif // __ARCH_ALPHA_PROCESS_HH__ 68