process.cc revision 12432
17405SAli.Saidi@ARM.com/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2003-2004 The Regents of The University of Michigan 37405SAli.Saidi@ARM.com * All rights reserved. 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147405SAli.Saidi@ARM.com * this software without specific prior written permission. 157405SAli.Saidi@ARM.com * 167405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277405SAli.Saidi@ARM.com * 287405SAli.Saidi@ARM.com * Authors: Gabe Black 297405SAli.Saidi@ARM.com * Ali Saidi 307405SAli.Saidi@ARM.com */ 317405SAli.Saidi@ARM.com 327405SAli.Saidi@ARM.com#include "arch/alpha/process.hh" 337405SAli.Saidi@ARM.com 347405SAli.Saidi@ARM.com#include "arch/alpha/isa_traits.hh" 357405SAli.Saidi@ARM.com#include "base/loader/elf_object.hh" 367405SAli.Saidi@ARM.com#include "base/loader/object_file.hh" 377405SAli.Saidi@ARM.com#include "base/logging.hh" 387405SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 397405SAli.Saidi@ARM.com#include "debug/Loader.hh" 407405SAli.Saidi@ARM.com#include "mem/page_table.hh" 417405SAli.Saidi@ARM.com#include "params/Process.hh" 428733Sgeoffrey.blake@arm.com#include "sim/aux_vector.hh" 438232Snate@binkert.org#include "sim/byteswap.hh" 448232Snate@binkert.org#include "sim/process_impl.hh" 457678Sgblack@eecs.umich.edu#include "sim/syscall_return.hh" 468059SAli.Saidi@ARM.com#include "sim/system.hh" 478284SAli.Saidi@ARM.com 487405SAli.Saidi@ARM.comusing namespace AlphaISA; 498733Sgeoffrey.blake@arm.comusing namespace std; 508733Sgeoffrey.blake@arm.com 518733Sgeoffrey.blake@arm.comAlphaProcess::AlphaProcess(ProcessParams *params, ObjectFile *objFile) 528733Sgeoffrey.blake@arm.com : Process(params, new FuncPageTable(params->name, params->pid, PageBytes), 537405SAli.Saidi@ARM.com objFile) 547405SAli.Saidi@ARM.com{ 557405SAli.Saidi@ARM.com fatal_if(!params->useArchPT, "Arch page tables not implemented."); 567427Sgblack@eecs.umich.edu Addr brk_point = objFile->dataBase() + objFile->dataSize() + 577427Sgblack@eecs.umich.edu objFile->bssSize(); 587427Sgblack@eecs.umich.edu brk_point = roundUp(brk_point, PageBytes); 597427Sgblack@eecs.umich.edu 608299Schander.sudanthi@arm.com // Set up stack. On Alpha, stack goes below text section. This 617427Sgblack@eecs.umich.edu // code should get moved to some architecture-specific spot. 627427Sgblack@eecs.umich.edu Addr stack_base = objFile->textBase() - (409600+4096); 637427Sgblack@eecs.umich.edu 647427Sgblack@eecs.umich.edu // Set up region for mmaps. 657427Sgblack@eecs.umich.edu Addr mmap_end = 0x10000; 667427Sgblack@eecs.umich.edu 677427Sgblack@eecs.umich.edu Addr max_stack_size = 8 * 1024 * 1024; 687604SGene.Wu@arm.com 697427Sgblack@eecs.umich.edu // Set pointer for next thread stack. Reserve 8M for main stack. 707427Sgblack@eecs.umich.edu Addr next_thread_stack_base = stack_base - max_stack_size; 717427Sgblack@eecs.umich.edu 727427Sgblack@eecs.umich.edu memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 737427Sgblack@eecs.umich.edu next_thread_stack_base, mmap_end); 747427Sgblack@eecs.umich.edu} 757427Sgblack@eecs.umich.edu 767427Sgblack@eecs.umich.eduvoid 777427Sgblack@eecs.umich.eduAlphaProcess::argsInit(int intSize, int pageSize) 787427Sgblack@eecs.umich.edu{ 798299Schander.sudanthi@arm.com // Patch the ld_bias for dynamic executables. 808299Schander.sudanthi@arm.com updateBias(); 818299Schander.sudanthi@arm.com 827427Sgblack@eecs.umich.edu objFile->loadSections(initVirtMem); 837427Sgblack@eecs.umich.edu 847427Sgblack@eecs.umich.edu typedef AuxVector<uint64_t> auxv_t; 857427Sgblack@eecs.umich.edu std::vector<auxv_t> auxv; 867427Sgblack@eecs.umich.edu 877427Sgblack@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 887427Sgblack@eecs.umich.edu if (elfObject) 897427Sgblack@eecs.umich.edu { 907427Sgblack@eecs.umich.edu // modern glibc uses a bunch of auxiliary vectors to set up 917427Sgblack@eecs.umich.edu // TLS as well as do a bunch of other stuff 927427Sgblack@eecs.umich.edu // these vectors go on the bottom of the stack, below argc/argv/envp 937427Sgblack@eecs.umich.edu // pointers but above actual arg strings 947427Sgblack@eecs.umich.edu // I don't have all the ones glibc looks at here, but so far it doesn't 957427Sgblack@eecs.umich.edu // seem to be a problem. 967427Sgblack@eecs.umich.edu // check out _dl_aux_init() in glibc/elf/dl-support.c for details 977427Sgblack@eecs.umich.edu // --Lisa 987427Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes)); 997427Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 1007427Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 1017427Sgblack@eecs.umich.edu DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable()); 1027427Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 1037427Sgblack@eecs.umich.edu // This is the base address of the ELF interpreter; it should be 1047427Sgblack@eecs.umich.edu // zero for static executables or contain the base address for 1057427Sgblack@eecs.umich.edu // dynamic executables. 1067427Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 1077427Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 1087427Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 1097427Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 1107427Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 1117436Sdam.sunwoo@arm.com auxv.push_back(auxv_t(M5_AT_EGID, egid())); 1127436Sdam.sunwoo@arm.com 1137436Sdam.sunwoo@arm.com } 1147436Sdam.sunwoo@arm.com 1157436Sdam.sunwoo@arm.com // Calculate how much space we need for arg & env & auxv arrays. 1167436Sdam.sunwoo@arm.com int argv_array_size = intSize * (argv.size() + 1); 1177436Sdam.sunwoo@arm.com int envp_array_size = intSize * (envp.size() + 1); 1187436Sdam.sunwoo@arm.com int auxv_array_size = intSize * 2 * (auxv.size() + 1); 1197436Sdam.sunwoo@arm.com 1207436Sdam.sunwoo@arm.com int arg_data_size = 0; 1217436Sdam.sunwoo@arm.com for (vector<string>::size_type i = 0; i < argv.size(); ++i) { 1227436Sdam.sunwoo@arm.com arg_data_size += argv[i].size() + 1; 1237436Sdam.sunwoo@arm.com } 1247436Sdam.sunwoo@arm.com int env_data_size = 0; 1257436Sdam.sunwoo@arm.com for (vector<string>::size_type i = 0; i < envp.size(); ++i) { 1267436Sdam.sunwoo@arm.com env_data_size += envp[i].size() + 1; 1277436Sdam.sunwoo@arm.com } 1287436Sdam.sunwoo@arm.com 1297436Sdam.sunwoo@arm.com int space_needed = 1307436Sdam.sunwoo@arm.com argv_array_size + 1317436Sdam.sunwoo@arm.com envp_array_size + 1327436Sdam.sunwoo@arm.com auxv_array_size + 1337436Sdam.sunwoo@arm.com arg_data_size + 1347436Sdam.sunwoo@arm.com env_data_size; 1357436Sdam.sunwoo@arm.com 1367436Sdam.sunwoo@arm.com if (space_needed < 32*1024) 1377436Sdam.sunwoo@arm.com space_needed = 32*1024; 1387436Sdam.sunwoo@arm.com 1397436Sdam.sunwoo@arm.com // set bottom of stack 1407436Sdam.sunwoo@arm.com memState->setStackMin(memState->getStackBase() - space_needed); 1417436Sdam.sunwoo@arm.com // align it 1427436Sdam.sunwoo@arm.com memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); 1437644Sali.saidi@arm.com memState->setStackSize(memState->getStackBase() - memState->getStackMin()); 1447644Sali.saidi@arm.com // map memory 1458147SAli.Saidi@ARM.com allocateMem(memState->getStackMin(), roundUp(memState->getStackSize(), 1468147SAli.Saidi@ARM.com pageSize)); 1478147SAli.Saidi@ARM.com 1488520SAli.Saidi@ARM.com // map out initial stack contents 1498147SAli.Saidi@ARM.com Addr argv_array_base = memState->getStackMin() + intSize; // room for argc 1508147SAli.Saidi@ARM.com Addr envp_array_base = argv_array_base + argv_array_size; 1518147SAli.Saidi@ARM.com Addr auxv_array_base = envp_array_base + envp_array_size; 1528147SAli.Saidi@ARM.com Addr arg_data_base = auxv_array_base + auxv_array_size; 1538147SAli.Saidi@ARM.com Addr env_data_base = arg_data_base + arg_data_size; 1548147SAli.Saidi@ARM.com 1557427Sgblack@eecs.umich.edu // write contents to stack 1567427Sgblack@eecs.umich.edu uint64_t argc = argv.size(); 1577427Sgblack@eecs.umich.edu if (intSize == 8) 1587405SAli.Saidi@ARM.com argc = htog((uint64_t)argc); 1597405SAli.Saidi@ARM.com else if (intSize == 4) 1607405SAli.Saidi@ARM.com argc = htog((uint32_t)argc); 1617405SAli.Saidi@ARM.com else 1627614Sminkyu.jeong@arm.com panic("Unknown int size"); 1637614Sminkyu.jeong@arm.com 1647614Sminkyu.jeong@arm.com initVirtMem.writeBlob(memState->getStackMin(), (uint8_t*)&argc, intSize); 1657614Sminkyu.jeong@arm.com 1667614Sminkyu.jeong@arm.com copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 1677614Sminkyu.jeong@arm.com copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 1687614Sminkyu.jeong@arm.com 1697614Sminkyu.jeong@arm.com //Copy the aux stuff 1707614Sminkyu.jeong@arm.com for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) { 1717614Sminkyu.jeong@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 1727614Sminkyu.jeong@arm.com (uint8_t*)&(auxv[x].a_type), intSize); 1737405SAli.Saidi@ARM.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 1747405SAli.Saidi@ARM.com (uint8_t*)&(auxv[x].a_val), intSize); 1757405SAli.Saidi@ARM.com } 1767405SAli.Saidi@ARM.com 1777405SAli.Saidi@ARM.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 1787405SAli.Saidi@ARM.com 1797405SAli.Saidi@ARM.com setSyscallArg(tc, 0, argc); 1807405SAli.Saidi@ARM.com setSyscallArg(tc, 1, argv_array_base); 1817720Sgblack@eecs.umich.edu tc->setIntReg(StackPointerReg, memState->getStackMin()); 1827720Sgblack@eecs.umich.edu 1837720Sgblack@eecs.umich.edu tc->pcState(getStartPC()); 1847405SAli.Saidi@ARM.com} 1857405SAli.Saidi@ARM.com 1867757SAli.Saidi@ARM.comvoid 1877405SAli.Saidi@ARM.comAlphaProcess::setupASNReg() 1887405SAli.Saidi@ARM.com{ 1897757SAli.Saidi@ARM.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 1907405SAli.Saidi@ARM.com tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57); 1918284SAli.Saidi@ARM.com} 1928284SAli.Saidi@ARM.com 1938284SAli.Saidi@ARM.com 1948468Swade.walker@arm.comvoid 1958468Swade.walker@arm.comAlphaProcess::unserialize(CheckpointIn &cp) 1968468Swade.walker@arm.com{ 1978468Swade.walker@arm.com Process::unserialize(cp); 1988468Swade.walker@arm.com // need to set up ASN after unserialization since _pid value may 1998284SAli.Saidi@ARM.com // come from checkpoint 2008284SAli.Saidi@ARM.com setupASNReg(); 2018284SAli.Saidi@ARM.com} 2027405SAli.Saidi@ARM.com 2037731SAli.Saidi@ARM.com 2048468Swade.walker@arm.comvoid 2058468Swade.walker@arm.comAlphaProcess::initState() 2068468Swade.walker@arm.com{ 2077405SAli.Saidi@ARM.com // need to set up ASN before further initialization since init 2087731SAli.Saidi@ARM.com // will involve writing to virtual memory addresses 2097405SAli.Saidi@ARM.com setupASNReg(); 2107405SAli.Saidi@ARM.com 2117405SAli.Saidi@ARM.com Process::initState(); 2127588SAli.Saidi@arm.com 2137588SAli.Saidi@arm.com argsInit(MachineBytes, PageBytes); 2147588SAli.Saidi@arm.com 2158299Schander.sudanthi@arm.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 2168299Schander.sudanthi@arm.com tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); 2178299Schander.sudanthi@arm.com //Operate in user mode 2187583SAli.Saidi@arm.com tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3); 2197583SAli.Saidi@arm.com tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3); 2207583SAli.Saidi@arm.com //No super page mapping 2217583SAli.Saidi@arm.com tc->setMiscRegNoEffect(IPR_MCSR, 0); 2227583SAli.Saidi@arm.com} 2237583SAli.Saidi@arm.com 2247583SAli.Saidi@arm.comAlphaISA::IntReg 2257583SAli.Saidi@arm.comAlphaProcess::getSyscallArg(ThreadContext *tc, int &i) 2268299Schander.sudanthi@arm.com{ 2277583SAli.Saidi@arm.com assert(i < 6); 2287583SAli.Saidi@arm.com return tc->readIntReg(FirstArgumentReg + i++); 2298302SAli.Saidi@ARM.com} 2308302SAli.Saidi@ARM.com 2317783SGiacomo.Gabrielli@arm.comvoid 2327783SGiacomo.Gabrielli@arm.comAlphaProcess::setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) 2337783SGiacomo.Gabrielli@arm.com{ 2347783SGiacomo.Gabrielli@arm.com assert(i < 6); 2358549Sdaniel.johnson@arm.com tc->setIntReg(FirstArgumentReg + i, val); 2368549Sdaniel.johnson@arm.com} 2378549Sdaniel.johnson@arm.com 2388549Sdaniel.johnson@arm.comvoid 2398549Sdaniel.johnson@arm.comAlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 2408549Sdaniel.johnson@arm.com{ 2417405SAli.Saidi@ARM.com // check for error condition. Alpha syscall convention is to 2427405SAli.Saidi@ARM.com // indicate success/failure in reg a3 (r19) and put the 2437405SAli.Saidi@ARM.com // return value itself in the standard return value reg (v0). 2447405SAli.Saidi@ARM.com if (sysret.successful()) { 2457405SAli.Saidi@ARM.com // no error 2467405SAli.Saidi@ARM.com tc->setIntReg(SyscallSuccessReg, 0); 2477405SAli.Saidi@ARM.com tc->setIntReg(ReturnValueReg, sysret.returnValue()); 2487405SAli.Saidi@ARM.com } else { 2497614Sminkyu.jeong@arm.com // got an error, return details 2507614Sminkyu.jeong@arm.com tc->setIntReg(SyscallSuccessReg, (IntReg)-1); 2517614Sminkyu.jeong@arm.com tc->setIntReg(ReturnValueReg, sysret.errnoValue()); 2527614Sminkyu.jeong@arm.com } 2537614Sminkyu.jeong@arm.com} 2547614Sminkyu.jeong@arm.com