process.cc revision 6180
12623SN/A/* 22623SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292623SN/A * Ali Saidi 302623SN/A */ 313170Sstever@eecs.umich.edu 323806Ssaidi@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 332623SN/A#include "arch/alpha/process.hh" 344040Ssaidi@eecs.umich.edu#include "base/loader/object_file.hh" 352623SN/A#include "base/loader/elf_object.hh" 362623SN/A#include "base/misc.hh" 373348Sbinkertn@umich.edu#include "cpu/thread_context.hh" 383348Sbinkertn@umich.edu#include "mem/page_table.hh" 394762Snate@binkert.org#include "sim/process_impl.hh" 402901Ssaidi@eecs.umich.edu#include "sim/system.hh" 412623SN/A 422623SN/Ausing namespace AlphaISA; 432623SN/Ausing namespace std; 442623SN/A 452623SN/AAlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params, 462623SN/A ObjectFile *objFile) 472623SN/A : LiveProcess(params, objFile) 482623SN/A{ 492623SN/A brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 502623SN/A brk_point = roundUp(brk_point, VMPageSize); 512623SN/A 522623SN/A // Set up stack. On Alpha, stack goes below text section. This 532623SN/A // code should get moved to some architecture-specific spot. 542623SN/A stack_base = objFile->textBase() - (409600+4096); 552623SN/A 562623SN/A // Set up region for mmaps. Tru64 seems to start just above 0 and 572623SN/A // grow up from there. 585336Shines@cs.fsu.edu mmap_start = mmap_end = 0x10000; 592623SN/A 604873Sstever@eecs.umich.edu // Set pointer for next thread stack. Reserve 8M for main stack. 612623SN/A next_thread_stack_base = stack_base - (8 * 1024 * 1024); 622623SN/A 632856Srdreslin@umich.edu} 642856Srdreslin@umich.edu 652856Srdreslin@umich.eduvoid 662856Srdreslin@umich.eduAlphaLiveProcess::argsInit(int intSize, int pageSize) 672856Srdreslin@umich.edu{ 682856Srdreslin@umich.edu objFile->loadSections(initVirtMem); 692856Srdreslin@umich.edu 704968Sacolyte@umich.edu typedef AuxVector<uint64_t> auxv_t; 714968Sacolyte@umich.edu std::vector<auxv_t> auxv; 724968Sacolyte@umich.edu 734968Sacolyte@umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 742856Srdreslin@umich.edu if(elfObject) 752856Srdreslin@umich.edu { 762856Srdreslin@umich.edu // modern glibc uses a bunch of auxiliary vectors to set up 772623SN/A // TLS as well as do a bunch of other stuff 782623SN/A // these vectors go on the bottom of the stack, below argc/argv/envp 792623SN/A // pointers but above actual arg strings 802623SN/A // I don't have all the ones glibc looks at here, but so far it doesn't 812623SN/A // seem to be a problem. 825310Ssaidi@eecs.umich.edu // check out _dl_aux_init() in glibc/elf/dl-support.c for details 832623SN/A // --Lisa 842680Sktlim@umich.edu auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::VMPageSize)); 852680Sktlim@umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 862623SN/A auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 872623SN/A DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable()); 885310Ssaidi@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 892623SN/A auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 902623SN/A auxv.push_back(auxv_t(M5_AT_UID, uid())); 914968Sacolyte@umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 924968Sacolyte@umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 934968Sacolyte@umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 944968Sacolyte@umich.edu 954968Sacolyte@umich.edu } 964968Sacolyte@umich.edu 975310Ssaidi@eecs.umich.edu // Calculate how much space we need for arg & env & auxv arrays. 985310Ssaidi@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 995310Ssaidi@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 1002623SN/A int auxv_array_size = intSize * 2 * (auxv.size() + 1); 1012623SN/A 1022623SN/A int arg_data_size = 0; 1033349Sbinkertn@umich.edu for (int i = 0; i < argv.size(); ++i) { 1042623SN/A arg_data_size += argv[i].size() + 1; 1053184Srdreslin@umich.edu } 1062623SN/A int env_data_size = 0; 1072623SN/A for (int i = 0; i < envp.size(); ++i) { 1082623SN/A env_data_size += envp[i].size() + 1; 1092623SN/A } 1103349Sbinkertn@umich.edu 1112623SN/A int space_needed = 1123310Srdreslin@umich.edu argv_array_size + 1133649Srdreslin@umich.edu envp_array_size + 1142623SN/A auxv_array_size + 1152623SN/A arg_data_size + 1162623SN/A env_data_size; 1173349Sbinkertn@umich.edu 1182623SN/A if (space_needed < 32*1024) 1193184Srdreslin@umich.edu space_needed = 32*1024; 1203184Srdreslin@umich.edu 1212623SN/A // set bottom of stack 1222623SN/A stack_min = stack_base - space_needed; 1232623SN/A // align it 1242623SN/A stack_min = roundDown(stack_min, pageSize); 1252623SN/A stack_size = stack_base - stack_min; 1263647Srdreslin@umich.edu // map memory 1273647Srdreslin@umich.edu pTable->allocate(stack_min, roundUp(stack_size, pageSize)); 1283647Srdreslin@umich.edu 1293647Srdreslin@umich.edu // map out initial stack contents 1303647Srdreslin@umich.edu Addr argv_array_base = stack_min + intSize; // room for argc 1312626SN/A Addr envp_array_base = argv_array_base + argv_array_size; 1323647Srdreslin@umich.edu Addr auxv_array_base = envp_array_base + envp_array_size; 1332626SN/A Addr arg_data_base = auxv_array_base + auxv_array_size; 1342623SN/A Addr env_data_base = arg_data_base + arg_data_size; 1352623SN/A 1362623SN/A // write contents to stack 1372657Ssaidi@eecs.umich.edu uint64_t argc = argv.size(); 1382623SN/A if (intSize == 8) 1392623SN/A argc = htog((uint64_t)argc); 1402623SN/A else if (intSize == 4) 1412623SN/A argc = htog((uint32_t)argc); 1422623SN/A else 1434192Sktlim@umich.edu panic("Unknown int size"); 1444192Sktlim@umich.edu 1454192Sktlim@umich.edu initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, intSize); 1464192Sktlim@umich.edu 1474192Sktlim@umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 1484192Sktlim@umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 1494192Sktlim@umich.edu 1504192Sktlim@umich.edu //Copy the aux stuff 1514192Sktlim@umich.edu for(int x = 0; x < auxv.size(); x++) 1524192Sktlim@umich.edu { 1534192Sktlim@umich.edu initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, 1542623SN/A (uint8_t*)&(auxv[x].a_type), intSize); 1552623SN/A initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 1562623SN/A (uint8_t*)&(auxv[x].a_val), intSize); 1572623SN/A } 1584968Sacolyte@umich.edu 1594968Sacolyte@umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1602623SN/A 1612623SN/A setSyscallArg(tc, 0, argc); 1622623SN/A setSyscallArg(tc, 1, argv_array_base); 1633647Srdreslin@umich.edu tc->setIntReg(StackPointerReg, stack_min); 1643647Srdreslin@umich.edu 1653647Srdreslin@umich.edu Addr prog_entry = objFile->entryPoint(); 1662623SN/A tc->setPC(prog_entry); 1672623SN/A tc->setNextPC(prog_entry + sizeof(MachInst)); 1682623SN/A 1692623SN/A // MIPS/Sparc need NNPC for delay slot handling, while 1702623SN/A // Alpha has no delay slots... However, CPU models 1712623SN/A // cycle PCs by PC=NPC, NPC=NNPC, etc. so setting this 1722623SN/A // here ensures CPU-Model Compatibility across board 1732623SN/A tc->setNextNPC(prog_entry + (2 * sizeof(MachInst))); 1742623SN/A} 1752623SN/A 1762915Sktlim@umich.eduvoid 1772915Sktlim@umich.eduAlphaLiveProcess::startup() 1783177Shsul@eecs.umich.edu{ 1793177Shsul@eecs.umich.edu if (checkpointRestored) 1803145Shsul@eecs.umich.edu return; 1812623SN/A 1822623SN/A Process::startup(); 1832623SN/A 1842623SN/A argsInit(MachineBytes, VMPageSize); 1852623SN/A 1862623SN/A ThreadContext *tc = system->getThreadContext(contextIds[0]); 1872623SN/A tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); 1882915Sktlim@umich.edu //Operate in user mode 1892915Sktlim@umich.edu tc->setMiscRegNoEffect(IPR_ICM, 0x18); 1903177Shsul@eecs.umich.edu //No super page mapping 1913145Shsul@eecs.umich.edu tc->setMiscRegNoEffect(IPR_MCSR, 0); 1922915Sktlim@umich.edu //Set this to 0 for now, but it should be unique for each process 1932915Sktlim@umich.edu tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57); 1942915Sktlim@umich.edu} 1952915Sktlim@umich.edu 1962915Sktlim@umich.eduAlphaISA::IntReg 1972915Sktlim@umich.eduAlphaLiveProcess::getSyscallArg(ThreadContext *tc, int i) 1985220Ssaidi@eecs.umich.edu{ 1995220Ssaidi@eecs.umich.edu assert(i < 6); 2005220Ssaidi@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + i); 2014940Snate@binkert.org} 2025220Ssaidi@eecs.umich.edu 2033324Shsul@eecs.umich.eduvoid 2045220Ssaidi@eecs.umich.eduAlphaLiveProcess::setSyscallArg(ThreadContext *tc, 2055220Ssaidi@eecs.umich.edu int i, AlphaISA::IntReg val) 2065220Ssaidi@eecs.umich.edu{ 2075220Ssaidi@eecs.umich.edu assert(i < 6); 2083324Shsul@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, val); 2092915Sktlim@umich.edu} 2102623SN/A 2112623SN/Avoid 2122623SN/AAlphaLiveProcess::setSyscallReturn(ThreadContext *tc, 2132798Sktlim@umich.edu SyscallReturn return_value) 2142623SN/A{ 2152798Sktlim@umich.edu // check for error condition. Alpha syscall convention is to 2162798Sktlim@umich.edu // indicate success/failure in reg a3 (r19) and put the 2172623SN/A // return value itself in the standard return value reg (v0). 2182798Sktlim@umich.edu if (return_value.successful()) { 2192623SN/A // no error 2202623SN/A tc->setIntReg(SyscallSuccessReg, 0); 2212623SN/A tc->setIntReg(ReturnValueReg, return_value.value()); 2222623SN/A } else { 2232623SN/A // got an error, return details 2242623SN/A tc->setIntReg(SyscallSuccessReg, (IntReg)-1); 2254192Sktlim@umich.edu tc->setIntReg(ReturnValueReg, -return_value.value()); 2262623SN/A } 2272623SN/A} 2282623SN/A