process.cc revision 5958
12207SN/A/*
22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan
32207SN/A * All rights reserved.
42207SN/A *
52207SN/A * Redistribution and use in source and binary forms, with or without
62207SN/A * modification, are permitted provided that the following conditions are
72207SN/A * met: redistributions of source code must retain the above copyright
82207SN/A * notice, this list of conditions and the following disclaimer;
92207SN/A * redistributions in binary form must reproduce the above copyright
102207SN/A * notice, this list of conditions and the following disclaimer in the
112207SN/A * documentation and/or other materials provided with the distribution;
122207SN/A * neither the name of the copyright holders nor the names of its
132207SN/A * contributors may be used to endorse or promote products derived from
142207SN/A * this software without specific prior written permission.
152207SN/A *
162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Gabe Black
292665Ssaidi@eecs.umich.edu *          Ali Saidi
302207SN/A */
312207SN/A
3211793Sbrandon.potter@amd.com#include "arch/alpha/isa_traits.hh"
3311793Sbrandon.potter@amd.com#include "arch/alpha/process.hh"
342972Sgblack@eecs.umich.edu#include "base/loader/object_file.hh"
358229Snate@binkert.org#include "base/loader/elf_object.hh"
362454SN/A#include "base/misc.hh"
3712334Sgabeblack@google.com#include "cpu/thread_context.hh"
382680Sktlim@umich.edu#include "mem/page_table.hh"
398232Snate@binkert.org#include "sim/process_impl.hh"
405759Shsul@eecs.umich.edu#include "sim/system.hh"
4112431Sgabeblack@google.com
4211854Sbrandon.potter@amd.comusing namespace AlphaISA;
437678Sgblack@eecs.umich.eduusing namespace std;
445759Shsul@eecs.umich.edu
4511800Sbrandon.potter@amd.comstatic const int SyscallSuccessReg = 19;
462474SN/A
472207SN/AAlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params,
482474SN/A                                   ObjectFile *objFile)
492474SN/A    : LiveProcess(params, objFile)
502474SN/A{
5111851Sbrandon.potter@amd.com    brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
5212431Sgabeblack@google.com    brk_point = roundUp(brk_point, VMPageSize);
532474SN/A
5412431Sgabeblack@google.com    // Set up stack.  On Alpha, stack goes below text section.  This
5511905SBrandon.Potter@amd.com    // code should get moved to some architecture-specific spot.
5611905SBrandon.Potter@amd.com    stack_base = objFile->textBase() - (409600+4096);
5711905SBrandon.Potter@amd.com
582474SN/A    // Set up region for mmaps.  Tru64 seems to start just above 0 and
592474SN/A    // grow up from there.
602474SN/A    mmap_start = mmap_end = 0x10000;
6111905SBrandon.Potter@amd.com
622474SN/A    // Set pointer for next thread stack.  Reserve 8M for main stack.
6311905SBrandon.Potter@amd.com    next_thread_stack_base = stack_base - (8 * 1024 * 1024);
6411905SBrandon.Potter@amd.com
6511905SBrandon.Potter@amd.com}
6611905SBrandon.Potter@amd.com
672474SN/Avoid
682474SN/AAlphaLiveProcess::argsInit(int intSize, int pageSize)
6911905SBrandon.Potter@amd.com{
702474SN/A    objFile->loadSections(initVirtMem);
7111905SBrandon.Potter@amd.com
7211905SBrandon.Potter@amd.com    typedef AuxVector<uint64_t> auxv_t;
732474SN/A    std::vector<auxv_t>  auxv;
742474SN/A
752474SN/A    ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
7611851Sbrandon.potter@amd.com    if(elfObject)
775759Shsul@eecs.umich.edu    {
7811389Sbrandon.potter@amd.com        // modern glibc uses a bunch of auxiliary vectors to set up
7911389Sbrandon.potter@amd.com        // TLS as well as do a bunch of other stuff
8011389Sbrandon.potter@amd.com        // these vectors go on the bottom of the stack, below argc/argv/envp
815759Shsul@eecs.umich.edu        // pointers but above actual arg strings
825759Shsul@eecs.umich.edu        // I don't have all the ones glibc looks at here, but so far it doesn't
835771Shsul@eecs.umich.edu        // seem to be a problem.
845759Shsul@eecs.umich.edu        // check out _dl_aux_init() in glibc/elf/dl-support.c for details
855759Shsul@eecs.umich.edu        // --Lisa
865759Shsul@eecs.umich.edu        auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::VMPageSize));
8711321Ssteve.reinhardt@amd.com        auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
885759Shsul@eecs.umich.edu        auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
8911320Ssteve.reinhardt@amd.com        DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
905759Shsul@eecs.umich.edu        auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
915759Shsul@eecs.umich.edu        auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
925759Shsul@eecs.umich.edu        auxv.push_back(auxv_t(M5_AT_UID, uid()));
935759Shsul@eecs.umich.edu        auxv.push_back(auxv_t(M5_AT_EUID, euid()));
945759Shsul@eecs.umich.edu        auxv.push_back(auxv_t(M5_AT_GID, gid()));
955759Shsul@eecs.umich.edu        auxv.push_back(auxv_t(M5_AT_EGID, egid()));
965759Shsul@eecs.umich.edu
9710318Sandreas.hansson@arm.com    }
985759Shsul@eecs.umich.edu
995759Shsul@eecs.umich.edu    // Calculate how much space we need for arg & env & auxv arrays.
1005759Shsul@eecs.umich.edu    int argv_array_size = intSize * (argv.size() + 1);
1015759Shsul@eecs.umich.edu    int envp_array_size = intSize * (envp.size() + 1);
10211389Sbrandon.potter@amd.com    int auxv_array_size = intSize * 2 * (auxv.size() + 1);
10311389Sbrandon.potter@amd.com
10411389Sbrandon.potter@amd.com    int arg_data_size = 0;
10511389Sbrandon.potter@amd.com    for (int i = 0; i < argv.size(); ++i) {
1065759Shsul@eecs.umich.edu        arg_data_size += argv[i].size() + 1;
1075759Shsul@eecs.umich.edu    }
1085759Shsul@eecs.umich.edu    int env_data_size = 0;
1095759Shsul@eecs.umich.edu    for (int i = 0; i < envp.size(); ++i) {
1105759Shsul@eecs.umich.edu        env_data_size += envp[i].size() + 1;
1115759Shsul@eecs.umich.edu    }
1125759Shsul@eecs.umich.edu
1135759Shsul@eecs.umich.edu    int space_needed =
1145759Shsul@eecs.umich.edu        argv_array_size +
1155759Shsul@eecs.umich.edu        envp_array_size +
1165759Shsul@eecs.umich.edu        auxv_array_size +
1175759Shsul@eecs.umich.edu        arg_data_size +
1185759Shsul@eecs.umich.edu        env_data_size;
1195759Shsul@eecs.umich.edu
1206227Snate@binkert.org    if (space_needed < 32*1024)
1215759Shsul@eecs.umich.edu        space_needed = 32*1024;
1225759Shsul@eecs.umich.edu
1235759Shsul@eecs.umich.edu    // set bottom of stack
1246227Snate@binkert.org    stack_min = stack_base - space_needed;
1255759Shsul@eecs.umich.edu    // align it
1265759Shsul@eecs.umich.edu    stack_min = roundDown(stack_min, pageSize);
1275759Shsul@eecs.umich.edu    stack_size = stack_base - stack_min;
1285759Shsul@eecs.umich.edu    // map memory
12911320Ssteve.reinhardt@amd.com    pTable->allocate(stack_min, roundUp(stack_size, pageSize));
13011320Ssteve.reinhardt@amd.com
1315759Shsul@eecs.umich.edu    // map out initial stack contents
13211320Ssteve.reinhardt@amd.com    Addr argv_array_base = stack_min + intSize; // room for argc
1335759Shsul@eecs.umich.edu    Addr envp_array_base = argv_array_base + argv_array_size;
1345759Shsul@eecs.umich.edu    Addr auxv_array_base = envp_array_base + envp_array_size;
1355759Shsul@eecs.umich.edu    Addr arg_data_base = auxv_array_base + auxv_array_size;
1365759Shsul@eecs.umich.edu    Addr env_data_base = arg_data_base + arg_data_size;
1375759Shsul@eecs.umich.edu
1385759Shsul@eecs.umich.edu    // write contents to stack
13911905SBrandon.Potter@amd.com    uint64_t argc = argv.size();
1405759Shsul@eecs.umich.edu    if (intSize == 8)
14111905SBrandon.Potter@amd.com        argc = htog((uint64_t)argc);
14211905SBrandon.Potter@amd.com    else if (intSize == 4)
1435759Shsul@eecs.umich.edu        argc = htog((uint32_t)argc);
14411905SBrandon.Potter@amd.com    else
14511905SBrandon.Potter@amd.com        panic("Unknown int size");
1465759Shsul@eecs.umich.edu
1475759Shsul@eecs.umich.edu    initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, intSize);
14811905SBrandon.Potter@amd.com
1495759Shsul@eecs.umich.edu    copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
1505759Shsul@eecs.umich.edu    copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
1515759Shsul@eecs.umich.edu
1525759Shsul@eecs.umich.edu    //Copy the aux stuff
1535759Shsul@eecs.umich.edu    for(int x = 0; x < auxv.size(); x++)
1545759Shsul@eecs.umich.edu    {
1555759Shsul@eecs.umich.edu        initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
1565759Shsul@eecs.umich.edu                (uint8_t*)&(auxv[x].a_type), intSize);
1575759Shsul@eecs.umich.edu        initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
1585759Shsul@eecs.umich.edu                (uint8_t*)&(auxv[x].a_val), intSize);
1595759Shsul@eecs.umich.edu    }
1605759Shsul@eecs.umich.edu
1615759Shsul@eecs.umich.edu    ThreadContext *tc = system->getThreadContext(contextIds[0]);
1625759Shsul@eecs.umich.edu
16311905SBrandon.Potter@amd.com    setSyscallArg(tc, 0, argc);
1645759Shsul@eecs.umich.edu    setSyscallArg(tc, 1, argv_array_base);
1655759Shsul@eecs.umich.edu    tc->setIntReg(StackPointerReg, stack_min);
1665759Shsul@eecs.umich.edu
1675759Shsul@eecs.umich.edu    Addr prog_entry = objFile->entryPoint();
1685759Shsul@eecs.umich.edu    tc->setPC(prog_entry);
1696227Snate@binkert.org    tc->setNextPC(prog_entry + sizeof(MachInst));
1708852Sandreas.hansson@arm.com
1715759Shsul@eecs.umich.edu#if THE_ISA != ALPHA_ISA //e.g. MIPS or Sparc
1728852Sandreas.hansson@arm.com    tc->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
1735759Shsul@eecs.umich.edu#endif
1745759Shsul@eecs.umich.edu
1755759Shsul@eecs.umich.edu
1765759Shsul@eecs.umich.edu}
1775759Shsul@eecs.umich.edu
1785958Sgblack@eecs.umich.eduvoid
1795958Sgblack@eecs.umich.eduAlphaLiveProcess::startup()
18011905SBrandon.Potter@amd.com{
1815759Shsul@eecs.umich.edu    if (checkpointRestored)
18211389Sbrandon.potter@amd.com        return;
1835759Shsul@eecs.umich.edu
1845759Shsul@eecs.umich.edu    Process::startup();
1855759Shsul@eecs.umich.edu
18611851Sbrandon.potter@amd.com    argsInit(MachineBytes, VMPageSize);
1872474SN/A
1886820SLisa.Hsu@amd.com    ThreadContext *tc = system->getThreadContext(contextIds[0]);
18911801Sbrandon.potter@amd.com    tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
1907532Ssteve.reinhardt@amd.com    //Operate in user mode
1916820SLisa.Hsu@amd.com    tc->setMiscRegNoEffect(IPR_ICM, 0x18);
1925183Ssaidi@eecs.umich.edu    //No super page mapping
1937532Ssteve.reinhardt@amd.com    tc->setMiscRegNoEffect(IPR_MCSR, 0);
19412186Sgabeblack@google.com    //Set this to 0 for now, but it should be unique for each process
1957532Ssteve.reinhardt@amd.com    tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57);
19612186Sgabeblack@google.com}
19711801Sbrandon.potter@amd.com
1987532Ssteve.reinhardt@amd.comAlphaISA::IntReg
1997532Ssteve.reinhardt@amd.comAlphaLiveProcess::getSyscallArg(ThreadContext *tc, int i)
2007532Ssteve.reinhardt@amd.com{
2017532Ssteve.reinhardt@amd.com    assert(i < 6);
2027532Ssteve.reinhardt@amd.com    return tc->readIntReg(FirstArgumentReg + i);
2037532Ssteve.reinhardt@amd.com}
20411851Sbrandon.potter@amd.com
2057532Ssteve.reinhardt@amd.comvoid
2067532Ssteve.reinhardt@amd.comAlphaLiveProcess::setSyscallArg(ThreadContext *tc,
2077532Ssteve.reinhardt@amd.com        int i, AlphaISA::IntReg val)
2087532Ssteve.reinhardt@amd.com{
2097532Ssteve.reinhardt@amd.com    assert(i < 6);
21011851Sbrandon.potter@amd.com    tc->setIntReg(FirstArgumentReg + i, val);
2115759Shsul@eecs.umich.edu}
21210318Sandreas.hansson@arm.com
2132474SN/Avoid
2147532Ssteve.reinhardt@amd.comAlphaLiveProcess::setSyscallReturn(ThreadContext *tc,
2155713Shsul@eecs.umich.edu        SyscallReturn return_value)
2165713Shsul@eecs.umich.edu{
2177701Sgblack@eecs.umich.edu    // check for error condition.  Alpha syscall convention is to
2187701Sgblack@eecs.umich.edu    // indicate success/failure in reg a3 (r19) and put the
2194997Sgblack@eecs.umich.edu    // return value itself in the standard return value reg (v0).
2205713Shsul@eecs.umich.edu    if (return_value.successful()) {
2212474SN/A        // no error
2222474SN/A        tc->setIntReg(SyscallSuccessReg, 0);
2235958Sgblack@eecs.umich.edu        tc->setIntReg(ReturnValueReg, return_value.value());
22411851Sbrandon.potter@amd.com    } else {
2255958Sgblack@eecs.umich.edu        // got an error, return details
2265958Sgblack@eecs.umich.edu        tc->setIntReg(SyscallSuccessReg, (IntReg)-1);
2276701Sgblack@eecs.umich.edu        tc->setIntReg(ReturnValueReg, -return_value.value());
2285958Sgblack@eecs.umich.edu    }
2295958Sgblack@eecs.umich.edu}
2305958Sgblack@eecs.umich.edu