process.cc revision 4997
112771Sqtt2@cornell.edu/* 212771Sqtt2@cornell.edu * Copyright (c) 2003-2004 The Regents of The University of Michigan 312771Sqtt2@cornell.edu * All rights reserved. 412771Sqtt2@cornell.edu * 512771Sqtt2@cornell.edu * Redistribution and use in source and binary forms, with or without 612771Sqtt2@cornell.edu * modification, are permitted provided that the following conditions are 712771Sqtt2@cornell.edu * met: redistributions of source code must retain the above copyright 812771Sqtt2@cornell.edu * notice, this list of conditions and the following disclaimer; 912771Sqtt2@cornell.edu * redistributions in binary form must reproduce the above copyright 1012771Sqtt2@cornell.edu * notice, this list of conditions and the following disclaimer in the 1112771Sqtt2@cornell.edu * documentation and/or other materials provided with the distribution; 1212771Sqtt2@cornell.edu * neither the name of the copyright holders nor the names of its 1312771Sqtt2@cornell.edu * contributors may be used to endorse or promote products derived from 1412771Sqtt2@cornell.edu * this software without specific prior written permission. 1512771Sqtt2@cornell.edu * 1612771Sqtt2@cornell.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712771Sqtt2@cornell.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812771Sqtt2@cornell.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912771Sqtt2@cornell.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012771Sqtt2@cornell.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112771Sqtt2@cornell.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212771Sqtt2@cornell.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312771Sqtt2@cornell.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412771Sqtt2@cornell.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512771Sqtt2@cornell.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612771Sqtt2@cornell.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712771Sqtt2@cornell.edu * 2812771Sqtt2@cornell.edu * Authors: Gabe Black 2912771Sqtt2@cornell.edu * Ali Saidi 3012771Sqtt2@cornell.edu */ 3112771Sqtt2@cornell.edu 3212771Sqtt2@cornell.edu#include "arch/alpha/isa_traits.hh" 3312771Sqtt2@cornell.edu#include "arch/alpha/process.hh" 3412771Sqtt2@cornell.edu#include "base/loader/object_file.hh" 3512771Sqtt2@cornell.edu#include "base/misc.hh" 3612771Sqtt2@cornell.edu#include "cpu/thread_context.hh" 3712771Sqtt2@cornell.edu#include "sim/system.hh" 3812771Sqtt2@cornell.edu 3912771Sqtt2@cornell.edu 4012771Sqtt2@cornell.eduusing namespace AlphaISA; 4112771Sqtt2@cornell.eduusing namespace std; 42 43AlphaLiveProcess::AlphaLiveProcess(const std::string &nm, ObjectFile *objFile, 44 System *_system, int stdin_fd, int stdout_fd, int stderr_fd, 45 std::vector<std::string> &argv, std::vector<std::string> &envp, 46 const std::string &cwd, 47 uint64_t _uid, uint64_t _euid, uint64_t _gid, uint64_t _egid, 48 uint64_t _pid, uint64_t _ppid) 49 : LiveProcess(nm, objFile, _system, stdin_fd, stdout_fd, stderr_fd, 50 argv, envp, cwd, _uid, _euid, _gid, _egid, _pid, _ppid) 51{ 52 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 53 brk_point = roundUp(brk_point, VMPageSize); 54 55 // Set up stack. On Alpha, stack goes below text section. This 56 // code should get moved to some architecture-specific spot. 57 stack_base = objFile->textBase() - (409600+4096); 58 59 // Set up region for mmaps. Tru64 seems to start just above 0 and 60 // grow up from there. 61 mmap_start = mmap_end = 0x10000; 62 63 // Set pointer for next thread stack. Reserve 8M for main stack. 64 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 65 66} 67 68void 69AlphaLiveProcess::startup() 70{ 71 argsInit(MachineBytes, VMPageSize); 72 73 threadContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer()); 74 //Opperate in user mode 75 threadContexts[0]->setMiscRegNoEffect(IPR_ICM, 0x18); 76 //No super page mapping 77 threadContexts[0]->setMiscRegNoEffect(IPR_MCSR, 0); 78 //Set this to 0 for now, but it should be unique for each process 79 threadContexts[0]->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57); 80} 81 82 83