process.cc revision 12431
12207SN/A/* 22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32207SN/A * All rights reserved. 42207SN/A * 52207SN/A * Redistribution and use in source and binary forms, with or without 62207SN/A * modification, are permitted provided that the following conditions are 72207SN/A * met: redistributions of source code must retain the above copyright 82207SN/A * notice, this list of conditions and the following disclaimer; 92207SN/A * redistributions in binary form must reproduce the above copyright 102207SN/A * notice, this list of conditions and the following disclaimer in the 112207SN/A * documentation and/or other materials provided with the distribution; 122207SN/A * neither the name of the copyright holders nor the names of its 132207SN/A * contributors may be used to endorse or promote products derived from 142207SN/A * this software without specific prior written permission. 152207SN/A * 162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Ali Saidi 302207SN/A */ 312207SN/A 3211793Sbrandon.potter@amd.com#include "arch/alpha/process.hh" 3311793Sbrandon.potter@amd.com 342972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 358229Snate@binkert.org#include "base/loader/elf_object.hh" 362454SN/A#include "base/loader/object_file.hh" 3712334Sgabeblack@google.com#include "base/logging.hh" 382680Sktlim@umich.edu#include "cpu/thread_context.hh" 398232Snate@binkert.org#include "debug/Loader.hh" 405759Shsul@eecs.umich.edu#include "mem/page_table.hh" 4112431Sgabeblack@google.com#include "params/Process.hh" 4211854Sbrandon.potter@amd.com#include "sim/aux_vector.hh" 437678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 445759Shsul@eecs.umich.edu#include "sim/process_impl.hh" 4511800Sbrandon.potter@amd.com#include "sim/syscall_return.hh" 462474SN/A#include "sim/system.hh" 472207SN/A 482474SN/Ausing namespace AlphaISA; 492474SN/Ausing namespace std; 502474SN/A 5111851Sbrandon.potter@amd.comAlphaProcess::AlphaProcess(ProcessParams *params, ObjectFile *objFile) 5212431Sgabeblack@google.com : Process(params, new FuncPageTable(params->name, params->pid), objFile) 532474SN/A{ 5412431Sgabeblack@google.com fatal_if(!params->useArchPT, "Arch page tables not implemented."); 5511905SBrandon.Potter@amd.com Addr brk_point = objFile->dataBase() + objFile->dataSize() + 5611905SBrandon.Potter@amd.com objFile->bssSize(); 5711905SBrandon.Potter@amd.com brk_point = roundUp(brk_point, PageBytes); 582474SN/A 592474SN/A // Set up stack. On Alpha, stack goes below text section. This 602474SN/A // code should get moved to some architecture-specific spot. 6111905SBrandon.Potter@amd.com Addr stack_base = objFile->textBase() - (409600+4096); 622474SN/A 6311905SBrandon.Potter@amd.com // Set up region for mmaps. 6411905SBrandon.Potter@amd.com Addr mmap_end = 0x10000; 6511905SBrandon.Potter@amd.com 6611905SBrandon.Potter@amd.com Addr max_stack_size = 8 * 1024 * 1024; 672474SN/A 682474SN/A // Set pointer for next thread stack. Reserve 8M for main stack. 6911905SBrandon.Potter@amd.com Addr next_thread_stack_base = stack_base - max_stack_size; 702474SN/A 7111905SBrandon.Potter@amd.com memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 7211905SBrandon.Potter@amd.com next_thread_stack_base, mmap_end); 732474SN/A} 742474SN/A 752474SN/Avoid 7611851Sbrandon.potter@amd.comAlphaProcess::argsInit(int intSize, int pageSize) 775759Shsul@eecs.umich.edu{ 7811389Sbrandon.potter@amd.com // Patch the ld_bias for dynamic executables. 7911389Sbrandon.potter@amd.com updateBias(); 8011389Sbrandon.potter@amd.com 815759Shsul@eecs.umich.edu objFile->loadSections(initVirtMem); 825759Shsul@eecs.umich.edu 835771Shsul@eecs.umich.edu typedef AuxVector<uint64_t> auxv_t; 845759Shsul@eecs.umich.edu std::vector<auxv_t> auxv; 855759Shsul@eecs.umich.edu 865759Shsul@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 8711321Ssteve.reinhardt@amd.com if (elfObject) 885759Shsul@eecs.umich.edu { 8911320Ssteve.reinhardt@amd.com // modern glibc uses a bunch of auxiliary vectors to set up 905759Shsul@eecs.umich.edu // TLS as well as do a bunch of other stuff 915759Shsul@eecs.umich.edu // these vectors go on the bottom of the stack, below argc/argv/envp 925759Shsul@eecs.umich.edu // pointers but above actual arg strings 935759Shsul@eecs.umich.edu // I don't have all the ones glibc looks at here, but so far it doesn't 945759Shsul@eecs.umich.edu // seem to be a problem. 955759Shsul@eecs.umich.edu // check out _dl_aux_init() in glibc/elf/dl-support.c for details 965759Shsul@eecs.umich.edu // --Lisa 9710318Sandreas.hansson@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes)); 985759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 995759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 1005759Shsul@eecs.umich.edu DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable()); 1015759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 10211389Sbrandon.potter@amd.com // This is the base address of the ELF interpreter; it should be 10311389Sbrandon.potter@amd.com // zero for static executables or contain the base address for 10411389Sbrandon.potter@amd.com // dynamic executables. 10511389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 1065759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 1075759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 1085759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 1095759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 1105759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 1115759Shsul@eecs.umich.edu 1125759Shsul@eecs.umich.edu } 1135759Shsul@eecs.umich.edu 1145759Shsul@eecs.umich.edu // Calculate how much space we need for arg & env & auxv arrays. 1155759Shsul@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 1165759Shsul@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 1175759Shsul@eecs.umich.edu int auxv_array_size = intSize * 2 * (auxv.size() + 1); 1185759Shsul@eecs.umich.edu 1195759Shsul@eecs.umich.edu int arg_data_size = 0; 1206227Snate@binkert.org for (vector<string>::size_type i = 0; i < argv.size(); ++i) { 1215759Shsul@eecs.umich.edu arg_data_size += argv[i].size() + 1; 1225759Shsul@eecs.umich.edu } 1235759Shsul@eecs.umich.edu int env_data_size = 0; 1246227Snate@binkert.org for (vector<string>::size_type i = 0; i < envp.size(); ++i) { 1255759Shsul@eecs.umich.edu env_data_size += envp[i].size() + 1; 1265759Shsul@eecs.umich.edu } 1275759Shsul@eecs.umich.edu 1285759Shsul@eecs.umich.edu int space_needed = 12911320Ssteve.reinhardt@amd.com argv_array_size + 13011320Ssteve.reinhardt@amd.com envp_array_size + 1315759Shsul@eecs.umich.edu auxv_array_size + 13211320Ssteve.reinhardt@amd.com arg_data_size + 1335759Shsul@eecs.umich.edu env_data_size; 1345759Shsul@eecs.umich.edu 1355759Shsul@eecs.umich.edu if (space_needed < 32*1024) 1365759Shsul@eecs.umich.edu space_needed = 32*1024; 1375759Shsul@eecs.umich.edu 1385759Shsul@eecs.umich.edu // set bottom of stack 13911905SBrandon.Potter@amd.com memState->setStackMin(memState->getStackBase() - space_needed); 1405759Shsul@eecs.umich.edu // align it 14111905SBrandon.Potter@amd.com memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); 14211905SBrandon.Potter@amd.com memState->setStackSize(memState->getStackBase() - memState->getStackMin()); 1435759Shsul@eecs.umich.edu // map memory 14411905SBrandon.Potter@amd.com allocateMem(memState->getStackMin(), roundUp(memState->getStackSize(), 14511905SBrandon.Potter@amd.com pageSize)); 1465759Shsul@eecs.umich.edu 1475759Shsul@eecs.umich.edu // map out initial stack contents 14811905SBrandon.Potter@amd.com Addr argv_array_base = memState->getStackMin() + intSize; // room for argc 1495759Shsul@eecs.umich.edu Addr envp_array_base = argv_array_base + argv_array_size; 1505759Shsul@eecs.umich.edu Addr auxv_array_base = envp_array_base + envp_array_size; 1515759Shsul@eecs.umich.edu Addr arg_data_base = auxv_array_base + auxv_array_size; 1525759Shsul@eecs.umich.edu Addr env_data_base = arg_data_base + arg_data_size; 1535759Shsul@eecs.umich.edu 1545759Shsul@eecs.umich.edu // write contents to stack 1555759Shsul@eecs.umich.edu uint64_t argc = argv.size(); 1565759Shsul@eecs.umich.edu if (intSize == 8) 1575759Shsul@eecs.umich.edu argc = htog((uint64_t)argc); 1585759Shsul@eecs.umich.edu else if (intSize == 4) 1595759Shsul@eecs.umich.edu argc = htog((uint32_t)argc); 1605759Shsul@eecs.umich.edu else 1615759Shsul@eecs.umich.edu panic("Unknown int size"); 1625759Shsul@eecs.umich.edu 16311905SBrandon.Potter@amd.com initVirtMem.writeBlob(memState->getStackMin(), (uint8_t*)&argc, intSize); 1645759Shsul@eecs.umich.edu 1655759Shsul@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 1665759Shsul@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 1675759Shsul@eecs.umich.edu 1685759Shsul@eecs.umich.edu //Copy the aux stuff 1696227Snate@binkert.org for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) { 1708852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 1715759Shsul@eecs.umich.edu (uint8_t*)&(auxv[x].a_type), intSize); 1728852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 1735759Shsul@eecs.umich.edu (uint8_t*)&(auxv[x].a_val), intSize); 1745759Shsul@eecs.umich.edu } 1755759Shsul@eecs.umich.edu 1765759Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1775759Shsul@eecs.umich.edu 1785958Sgblack@eecs.umich.edu setSyscallArg(tc, 0, argc); 1795958Sgblack@eecs.umich.edu setSyscallArg(tc, 1, argv_array_base); 18011905SBrandon.Potter@amd.com tc->setIntReg(StackPointerReg, memState->getStackMin()); 1815759Shsul@eecs.umich.edu 18211389Sbrandon.potter@amd.com tc->pcState(getStartPC()); 1835759Shsul@eecs.umich.edu} 1845759Shsul@eecs.umich.edu 1855759Shsul@eecs.umich.eduvoid 18611851Sbrandon.potter@amd.comAlphaProcess::setupASNReg() 1872474SN/A{ 1886820SLisa.Hsu@amd.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 18911801Sbrandon.potter@amd.com tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57); 1907532Ssteve.reinhardt@amd.com} 1916820SLisa.Hsu@amd.com 1925183Ssaidi@eecs.umich.edu 1937532Ssteve.reinhardt@amd.comvoid 19412186Sgabeblack@google.comAlphaProcess::unserialize(CheckpointIn &cp) 1957532Ssteve.reinhardt@amd.com{ 19612186Sgabeblack@google.com Process::unserialize(cp); 19711801Sbrandon.potter@amd.com // need to set up ASN after unserialization since _pid value may 1987532Ssteve.reinhardt@amd.com // come from checkpoint 1997532Ssteve.reinhardt@amd.com setupASNReg(); 2007532Ssteve.reinhardt@amd.com} 2017532Ssteve.reinhardt@amd.com 2027532Ssteve.reinhardt@amd.com 2037532Ssteve.reinhardt@amd.comvoid 20411851Sbrandon.potter@amd.comAlphaProcess::initState() 2057532Ssteve.reinhardt@amd.com{ 2067532Ssteve.reinhardt@amd.com // need to set up ASN before further initialization since init 2077532Ssteve.reinhardt@amd.com // will involve writing to virtual memory addresses 2087532Ssteve.reinhardt@amd.com setupASNReg(); 2097532Ssteve.reinhardt@amd.com 21011851Sbrandon.potter@amd.com Process::initState(); 2115759Shsul@eecs.umich.edu 21210318Sandreas.hansson@arm.com argsInit(MachineBytes, PageBytes); 2132474SN/A 2147532Ssteve.reinhardt@amd.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 2155713Shsul@eecs.umich.edu tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); 2165713Shsul@eecs.umich.edu //Operate in user mode 2177701Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3); 2187701Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3); 2194997Sgblack@eecs.umich.edu //No super page mapping 2205713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(IPR_MCSR, 0); 2212474SN/A} 2222474SN/A 2235958Sgblack@eecs.umich.eduAlphaISA::IntReg 22411851Sbrandon.potter@amd.comAlphaProcess::getSyscallArg(ThreadContext *tc, int &i) 2255958Sgblack@eecs.umich.edu{ 2265958Sgblack@eecs.umich.edu assert(i < 6); 2276701Sgblack@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + i++); 2285958Sgblack@eecs.umich.edu} 2295958Sgblack@eecs.umich.edu 2305958Sgblack@eecs.umich.eduvoid 23111851Sbrandon.potter@amd.comAlphaProcess::setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) 2325958Sgblack@eecs.umich.edu{ 2335958Sgblack@eecs.umich.edu assert(i < 6); 2345958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, val); 2355958Sgblack@eecs.umich.edu} 2365958Sgblack@eecs.umich.edu 2375958Sgblack@eecs.umich.eduvoid 23811851Sbrandon.potter@amd.comAlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 2395958Sgblack@eecs.umich.edu{ 2405958Sgblack@eecs.umich.edu // check for error condition. Alpha syscall convention is to 2415958Sgblack@eecs.umich.edu // indicate success/failure in reg a3 (r19) and put the 2425958Sgblack@eecs.umich.edu // return value itself in the standard return value reg (v0). 24310223Ssteve.reinhardt@amd.com if (sysret.successful()) { 2445958Sgblack@eecs.umich.edu // no error 2455958Sgblack@eecs.umich.edu tc->setIntReg(SyscallSuccessReg, 0); 24610223Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, sysret.returnValue()); 2475958Sgblack@eecs.umich.edu } else { 2485958Sgblack@eecs.umich.edu // got an error, return details 2495958Sgblack@eecs.umich.edu tc->setIntReg(SyscallSuccessReg, (IntReg)-1); 25010223Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, sysret.errnoValue()); 2515958Sgblack@eecs.umich.edu } 2525958Sgblack@eecs.umich.edu} 253