process.cc revision 10905
12207SN/A/* 22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32207SN/A * All rights reserved. 42207SN/A * 52207SN/A * Redistribution and use in source and binary forms, with or without 62207SN/A * modification, are permitted provided that the following conditions are 72207SN/A * met: redistributions of source code must retain the above copyright 82207SN/A * notice, this list of conditions and the following disclaimer; 92207SN/A * redistributions in binary form must reproduce the above copyright 102207SN/A * notice, this list of conditions and the following disclaimer in the 112207SN/A * documentation and/or other materials provided with the distribution; 122207SN/A * neither the name of the copyright holders nor the names of its 132207SN/A * contributors may be used to endorse or promote products derived from 142207SN/A * this software without specific prior written permission. 152207SN/A * 162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Ali Saidi 302207SN/A */ 312207SN/A 322972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 332207SN/A#include "arch/alpha/process.hh" 348229Snate@binkert.org#include "base/loader/elf_object.hh" 352454SN/A#include "base/loader/object_file.hh" 362454SN/A#include "base/misc.hh" 372680Sktlim@umich.edu#include "cpu/thread_context.hh" 388232Snate@binkert.org#include "debug/Loader.hh" 395759Shsul@eecs.umich.edu#include "mem/page_table.hh" 407678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 415759Shsul@eecs.umich.edu#include "sim/process_impl.hh" 422474SN/A#include "sim/system.hh" 432207SN/A 442474SN/Ausing namespace AlphaISA; 452474SN/Ausing namespace std; 462474SN/A 475569Snate@binkert.orgAlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params, 485569Snate@binkert.org ObjectFile *objFile) 495154Sgblack@eecs.umich.edu : LiveProcess(params, objFile) 502474SN/A{ 512474SN/A brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 5210318Sandreas.hansson@arm.com brk_point = roundUp(brk_point, PageBytes); 532474SN/A 542474SN/A // Set up stack. On Alpha, stack goes below text section. This 552474SN/A // code should get moved to some architecture-specific spot. 562474SN/A stack_base = objFile->textBase() - (409600+4096); 572474SN/A 582474SN/A // Set up region for mmaps. Tru64 seems to start just above 0 and 592474SN/A // grow up from there. 602474SN/A mmap_start = mmap_end = 0x10000; 612474SN/A 622474SN/A // Set pointer for next thread stack. Reserve 8M for main stack. 632474SN/A next_thread_stack_base = stack_base - (8 * 1024 * 1024); 642474SN/A 652474SN/A} 662474SN/A 672474SN/Avoid 685759Shsul@eecs.umich.eduAlphaLiveProcess::argsInit(int intSize, int pageSize) 695759Shsul@eecs.umich.edu{ 705759Shsul@eecs.umich.edu objFile->loadSections(initVirtMem); 715759Shsul@eecs.umich.edu 725771Shsul@eecs.umich.edu typedef AuxVector<uint64_t> auxv_t; 735759Shsul@eecs.umich.edu std::vector<auxv_t> auxv; 745759Shsul@eecs.umich.edu 755759Shsul@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 765759Shsul@eecs.umich.edu if(elfObject) 775759Shsul@eecs.umich.edu { 785759Shsul@eecs.umich.edu // modern glibc uses a bunch of auxiliary vectors to set up 795759Shsul@eecs.umich.edu // TLS as well as do a bunch of other stuff 805759Shsul@eecs.umich.edu // these vectors go on the bottom of the stack, below argc/argv/envp 815759Shsul@eecs.umich.edu // pointers but above actual arg strings 825759Shsul@eecs.umich.edu // I don't have all the ones glibc looks at here, but so far it doesn't 835759Shsul@eecs.umich.edu // seem to be a problem. 845759Shsul@eecs.umich.edu // check out _dl_aux_init() in glibc/elf/dl-support.c for details 855759Shsul@eecs.umich.edu // --Lisa 8610318Sandreas.hansson@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes)); 875759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 885759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 895759Shsul@eecs.umich.edu DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable()); 905759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 915759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 925759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 935759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 945759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 955759Shsul@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 965759Shsul@eecs.umich.edu 975759Shsul@eecs.umich.edu } 985759Shsul@eecs.umich.edu 995759Shsul@eecs.umich.edu // Calculate how much space we need for arg & env & auxv arrays. 1005759Shsul@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 1015759Shsul@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 1025759Shsul@eecs.umich.edu int auxv_array_size = intSize * 2 * (auxv.size() + 1); 1035759Shsul@eecs.umich.edu 1045759Shsul@eecs.umich.edu int arg_data_size = 0; 1056227Snate@binkert.org for (vector<string>::size_type i = 0; i < argv.size(); ++i) { 1065759Shsul@eecs.umich.edu arg_data_size += argv[i].size() + 1; 1075759Shsul@eecs.umich.edu } 1085759Shsul@eecs.umich.edu int env_data_size = 0; 1096227Snate@binkert.org for (vector<string>::size_type i = 0; i < envp.size(); ++i) { 1105759Shsul@eecs.umich.edu env_data_size += envp[i].size() + 1; 1115759Shsul@eecs.umich.edu } 1125759Shsul@eecs.umich.edu 1135759Shsul@eecs.umich.edu int space_needed = 1145759Shsul@eecs.umich.edu argv_array_size + 1155759Shsul@eecs.umich.edu envp_array_size + 1165759Shsul@eecs.umich.edu auxv_array_size + 1175759Shsul@eecs.umich.edu arg_data_size + 1185759Shsul@eecs.umich.edu env_data_size; 1195759Shsul@eecs.umich.edu 1205759Shsul@eecs.umich.edu if (space_needed < 32*1024) 1215759Shsul@eecs.umich.edu space_needed = 32*1024; 1225759Shsul@eecs.umich.edu 1235759Shsul@eecs.umich.edu // set bottom of stack 1245759Shsul@eecs.umich.edu stack_min = stack_base - space_needed; 1255759Shsul@eecs.umich.edu // align it 1265759Shsul@eecs.umich.edu stack_min = roundDown(stack_min, pageSize); 1275759Shsul@eecs.umich.edu stack_size = stack_base - stack_min; 1285759Shsul@eecs.umich.edu // map memory 1298601Ssteve.reinhardt@amd.com allocateMem(stack_min, roundUp(stack_size, pageSize)); 1305759Shsul@eecs.umich.edu 1315759Shsul@eecs.umich.edu // map out initial stack contents 1325759Shsul@eecs.umich.edu Addr argv_array_base = stack_min + intSize; // room for argc 1335759Shsul@eecs.umich.edu Addr envp_array_base = argv_array_base + argv_array_size; 1345759Shsul@eecs.umich.edu Addr auxv_array_base = envp_array_base + envp_array_size; 1355759Shsul@eecs.umich.edu Addr arg_data_base = auxv_array_base + auxv_array_size; 1365759Shsul@eecs.umich.edu Addr env_data_base = arg_data_base + arg_data_size; 1375759Shsul@eecs.umich.edu 1385759Shsul@eecs.umich.edu // write contents to stack 1395759Shsul@eecs.umich.edu uint64_t argc = argv.size(); 1405759Shsul@eecs.umich.edu if (intSize == 8) 1415759Shsul@eecs.umich.edu argc = htog((uint64_t)argc); 1425759Shsul@eecs.umich.edu else if (intSize == 4) 1435759Shsul@eecs.umich.edu argc = htog((uint32_t)argc); 1445759Shsul@eecs.umich.edu else 1455759Shsul@eecs.umich.edu panic("Unknown int size"); 1465759Shsul@eecs.umich.edu 1478852Sandreas.hansson@arm.com initVirtMem.writeBlob(stack_min, (uint8_t*)&argc, intSize); 1485759Shsul@eecs.umich.edu 1495759Shsul@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 1505759Shsul@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 1515759Shsul@eecs.umich.edu 1525759Shsul@eecs.umich.edu //Copy the aux stuff 1536227Snate@binkert.org for (vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) { 1548852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 1555759Shsul@eecs.umich.edu (uint8_t*)&(auxv[x].a_type), intSize); 1568852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 1575759Shsul@eecs.umich.edu (uint8_t*)&(auxv[x].a_val), intSize); 1585759Shsul@eecs.umich.edu } 1595759Shsul@eecs.umich.edu 1605759Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1615759Shsul@eecs.umich.edu 1625958Sgblack@eecs.umich.edu setSyscallArg(tc, 0, argc); 1635958Sgblack@eecs.umich.edu setSyscallArg(tc, 1, argv_array_base); 1645759Shsul@eecs.umich.edu tc->setIntReg(StackPointerReg, stack_min); 1655759Shsul@eecs.umich.edu 1667720Sgblack@eecs.umich.edu tc->pcState(objFile->entryPoint()); 1675759Shsul@eecs.umich.edu} 1685759Shsul@eecs.umich.edu 1695759Shsul@eecs.umich.eduvoid 1707532Ssteve.reinhardt@amd.comAlphaLiveProcess::setupASNReg() 1712474SN/A{ 1726820SLisa.Hsu@amd.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 1736820SLisa.Hsu@amd.com tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57); 1747532Ssteve.reinhardt@amd.com} 1756820SLisa.Hsu@amd.com 1765183Ssaidi@eecs.umich.edu 1777532Ssteve.reinhardt@amd.comvoid 17810905Sandreas.sandberg@arm.comAlphaLiveProcess::loadState(CheckpointIn &cp) 1797532Ssteve.reinhardt@amd.com{ 1807532Ssteve.reinhardt@amd.com LiveProcess::loadState(cp); 1817532Ssteve.reinhardt@amd.com // need to set up ASN after unserialization since M5_pid value may 1827532Ssteve.reinhardt@amd.com // come from checkpoint 1837532Ssteve.reinhardt@amd.com setupASNReg(); 1847532Ssteve.reinhardt@amd.com} 1857532Ssteve.reinhardt@amd.com 1867532Ssteve.reinhardt@amd.com 1877532Ssteve.reinhardt@amd.comvoid 1887532Ssteve.reinhardt@amd.comAlphaLiveProcess::initState() 1897532Ssteve.reinhardt@amd.com{ 1907532Ssteve.reinhardt@amd.com // need to set up ASN before further initialization since init 1917532Ssteve.reinhardt@amd.com // will involve writing to virtual memory addresses 1927532Ssteve.reinhardt@amd.com setupASNReg(); 1937532Ssteve.reinhardt@amd.com 1947532Ssteve.reinhardt@amd.com LiveProcess::initState(); 1955759Shsul@eecs.umich.edu 19610318Sandreas.hansson@arm.com argsInit(MachineBytes, PageBytes); 1972474SN/A 1987532Ssteve.reinhardt@amd.com ThreadContext *tc = system->getThreadContext(contextIds[0]); 1995713Shsul@eecs.umich.edu tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); 2005713Shsul@eecs.umich.edu //Operate in user mode 2017701Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3); 2027701Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3); 2034997Sgblack@eecs.umich.edu //No super page mapping 2045713Shsul@eecs.umich.edu tc->setMiscRegNoEffect(IPR_MCSR, 0); 2052474SN/A} 2062474SN/A 2075958Sgblack@eecs.umich.eduAlphaISA::IntReg 2086701Sgblack@eecs.umich.eduAlphaLiveProcess::getSyscallArg(ThreadContext *tc, int &i) 2095958Sgblack@eecs.umich.edu{ 2105958Sgblack@eecs.umich.edu assert(i < 6); 2116701Sgblack@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + i++); 2125958Sgblack@eecs.umich.edu} 2135958Sgblack@eecs.umich.edu 2145958Sgblack@eecs.umich.eduvoid 2155958Sgblack@eecs.umich.eduAlphaLiveProcess::setSyscallArg(ThreadContext *tc, 2165958Sgblack@eecs.umich.edu int i, AlphaISA::IntReg val) 2175958Sgblack@eecs.umich.edu{ 2185958Sgblack@eecs.umich.edu assert(i < 6); 2195958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, val); 2205958Sgblack@eecs.umich.edu} 2215958Sgblack@eecs.umich.edu 2225958Sgblack@eecs.umich.eduvoid 22310223Ssteve.reinhardt@amd.comAlphaLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 2245958Sgblack@eecs.umich.edu{ 2255958Sgblack@eecs.umich.edu // check for error condition. Alpha syscall convention is to 2265958Sgblack@eecs.umich.edu // indicate success/failure in reg a3 (r19) and put the 2275958Sgblack@eecs.umich.edu // return value itself in the standard return value reg (v0). 22810223Ssteve.reinhardt@amd.com if (sysret.successful()) { 2295958Sgblack@eecs.umich.edu // no error 2305958Sgblack@eecs.umich.edu tc->setIntReg(SyscallSuccessReg, 0); 23110223Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, sysret.returnValue()); 2325958Sgblack@eecs.umich.edu } else { 2335958Sgblack@eecs.umich.edu // got an error, return details 2345958Sgblack@eecs.umich.edu tc->setIntReg(SyscallSuccessReg, (IntReg)-1); 23510223Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, sysret.errnoValue()); 2365958Sgblack@eecs.umich.edu } 2375958Sgblack@eecs.umich.edu} 238