locked_mem.hh revision 7783:9b880b40ac10
12SN/A/* 21762SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu */ 302SN/A 312SN/A#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__ 321110SN/A#define __ARCH_ALPHA_LOCKED_MEM_HH__ 332680Sktlim@umich.edu 342196SN/A/** 352196SN/A * @file 362289SN/A * 372289SN/A * ISA-specific helper functions for locked memory accesses. 382800Ssaidi@eecs.umich.edu * 392800Ssaidi@eecs.umich.edu * Note that these functions are not embedded in the ISA description 402800Ssaidi@eecs.umich.edu * because they operate on the *physical* address rather than the 412289SN/A * virtual address. In the current M5 design, the physical address is 422SN/A * not accessible from the ISA description, only from the CPU model. 432167SN/A * Thus the CPU is responsible for calling back to the ISA (here) 442167SN/A * after the address translation has been performed to allow the ISA 452167SN/A * to do these manipulations based on the physical address. 462203SN/A */ 472203SN/A 482222SN/A#include "arch/alpha/registers.hh" 492166SN/A#include "base/misc.hh" 502203SN/A#include "mem/request.hh" 512203SN/A 522222SN/Anamespace AlphaISA { 532166SN/A 542147SN/Atemplate <class XC> 552147SN/Ainline void 562222SN/AhandleLockedRead(XC *xc, Request *req) 572147SN/A{ 582147SN/A xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); 592147SN/A xc->setMiscReg(MISCREG_LOCKFLAG, true); 602222SN/A} 612147SN/A 622800Ssaidi@eecs.umich.edu 632800Ssaidi@eecs.umich.edutemplate <class XC> 642800Ssaidi@eecs.umich.eduinline bool 652800Ssaidi@eecs.umich.eduhandleLockedWrite(XC *xc, Request *req) 662800Ssaidi@eecs.umich.edu{ 672800Ssaidi@eecs.umich.edu if (req->isUncacheable()) { 682147SN/A // Funky Turbolaser mailbox access...don't update 692147SN/A // result register (see stq_c in decoder.isa) 702222SN/A req->setExtraData(2); 712147SN/A } else { 722147SN/A // standard store conditional 732147SN/A bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 742222SN/A Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR); 752147SN/A if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 762147SN/A // Lock flag not set or addr mismatch in CPU; 772147SN/A // don't even bother sending to memory system 782222SN/A req->setExtraData(0); 792147SN/A xc->setMiscReg(MISCREG_LOCKFLAG, false); 802147SN/A // the rest of this code is not architectural; 812147SN/A // it's just a debugging aid to help detect 822222SN/A // livelock by warning on long sequences of failed 832147SN/A // store conditionals 842147SN/A int stCondFailures = xc->readStCondFailures(); 852147SN/A stCondFailures++; 862222SN/A xc->setStCondFailures(stCondFailures); 872147SN/A if (stCondFailures % 100000 == 0) { 882289SN/A warn("context %d: %d consecutive " 892289SN/A "store conditional failures\n", 902289SN/A xc->contextId(), stCondFailures); 912289SN/A } 922147SN/A 932147SN/A // store conditional failed already, so don't issue it to mem 942222SN/A return false; 952147SN/A } 962147SN/A } 972147SN/A 982222SN/A return true; 992147SN/A} 1002147SN/A 1012147SN/A} // namespace AlphaISA 1022222SN/A 1032147SN/A#endif // __ARCH_ALPHA_LOCKED_MEM_HH__ 1042147SN/A