locked_mem.hh revision 5569:baeee670d4ce
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__ 32#define __ARCH_ALPHA_LOCKED_MEM_HH__ 33 34/** 35 * @file 36 * 37 * ISA-specific helper functions for locked memory accesses. 38 * 39 * Note that these functions are not embedded in the ISA description 40 * because they operate on the *physical* address rather than the 41 * virtual address. In the current M5 design, the physical address is 42 * not accessible from the ISA description, only from the CPU model. 43 * Thus the CPU is responsible for calling back to the ISA (here) 44 * after the address translation has been performed to allow the ISA 45 * to do these manipulations based on the physical address. 46 */ 47 48#include "arch/alpha/miscregfile.hh" 49#include "base/misc.hh" 50#include "mem/request.hh" 51 52namespace AlphaISA { 53 54template <class XC> 55inline void 56handleLockedRead(XC *xc, Request *req) 57{ 58 xc->setMiscRegNoEffect(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); 59 xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, true); 60} 61 62 63template <class XC> 64inline bool 65handleLockedWrite(XC *xc, Request *req) 66{ 67 if (req->isUncacheable()) { 68 // Funky Turbolaser mailbox access...don't update 69 // result register (see stq_c in decoder.isa) 70 req->setExtraData(2); 71 } else { 72 // standard store conditional 73 bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LOCKFLAG); 74 Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LOCKADDR); 75 if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 76 // Lock flag not set or addr mismatch in CPU; 77 // don't even bother sending to memory system 78 req->setExtraData(0); 79 xc->setMiscRegNoEffect(MISCREG_LOCKFLAG, false); 80 // the rest of this code is not architectural; 81 // it's just a debugging aid to help detect 82 // livelock by warning on long sequences of failed 83 // store conditionals 84 int stCondFailures = xc->readStCondFailures(); 85 stCondFailures++; 86 xc->setStCondFailures(stCondFailures); 87 if (stCondFailures % 100000 == 0) { 88 warn("cpu %d: %d consecutive " 89 "store conditional failures\n", 90 xc->readCpuId(), stCondFailures); 91 } 92 93 // store conditional failed already, so don't issue it to mem 94 return false; 95 } 96 } 97 98 return true; 99} 100 101} // namespace AlphaISA 102 103#endif // __ARCH_ALPHA_LOCKED_MEM_HH__ 104