isa_traits.hh revision 6216
15148SN/A/* 25148SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 35148SN/A * All rights reserved. 48835SAli.Saidi@ARM.com * 57873SN/A * Redistribution and use in source and binary forms, with or without 67873SN/A * modification, are permitted provided that the following conditions are 77873SN/A * met: redistributions of source code must retain the above copyright 85148SN/A * notice, this list of conditions and the following disclaimer; 95148SN/A * redistributions in binary form must reproduce the above copyright 105148SN/A * notice, this list of conditions and the following disclaimer in the 115148SN/A * documentation and/or other materials provided with the distribution; 128835SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 139373Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 148835SAli.Saidi@ARM.com * this software without specific prior written permission. 158835SAli.Saidi@ARM.com * 168835SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175148SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189481Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198673SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208721SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218835SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228835SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237935SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247935SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257935SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267935SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277935SN/A * 287935SN/A * Authors: Steve Reinhardt 297935SN/A * Gabe Black 308983Snate@binkert.org */ 315148SN/A 325148SN/A#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 335148SN/A#define __ARCH_ALPHA_ISA_TRAITS_HH__ 349481Snilay@cs.wisc.edu 359481Snilay@cs.wisc.edunamespace LittleEndianGuest {} 365876SN/A 375148SN/A#include "arch/alpha/ipr.hh" 385148SN/A#include "arch/alpha/max_inst_regs.hh" 395876SN/A#include "arch/alpha/types.hh" 408835SAli.Saidi@ARM.com#include "base/types.hh" 415876SN/A#include "config/full_system.hh" 425148SN/A 438983Snate@binkert.orgclass StaticInstPtr; 445148SN/A 455148SN/Anamespace AlphaISA { 468835SAli.Saidi@ARM.com 479481Snilay@cs.wisc.eduusing namespace LittleEndianGuest; 485148SN/Ausing AlphaISAInst::MaxInstSrcRegs; 495148SN/Ausing AlphaISAInst::MaxInstDestRegs; 505148SN/A 515148SN/A// These enumerate all the registers for dependence tracking. 525148SN/Aenum DependenceTags { 535540SN/A // 0..31 are the integer regs 0..31 548835SAli.Saidi@ARM.com // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 555148SN/A FP_Base_DepTag = 40, 565509SN/A Ctrl_Base_DepTag = 72 575509SN/A}; 589481Snilay@cs.wisc.edu 595148SN/AStaticInstPtr decodeInst(ExtMachInst); 605148SN/A 615148SN/A// Alpha Does NOT have a delay slot 625148SN/A#define ISA_HAS_DELAY_SLOT 0 638983Snate@binkert.org 648983Snate@binkert.orgconst Addr PageShift = 13; 655148SN/Aconst Addr PageBytes = ULL(1) << PageShift; 665148SN/Aconst Addr PageMask = ~(PageBytes - 1); 676024SN/Aconst Addr PageOffset = PageBytes - 1; 688835SAli.Saidi@ARM.com 695148SN/A//////////////////////////////////////////////////////////////////////// 708835SAli.Saidi@ARM.com// 718835SAli.Saidi@ARM.com// Translation stuff 728835SAli.Saidi@ARM.com// 738835SAli.Saidi@ARM.com 749373Snilay@cs.wisc.educonst Addr PteShift = 3; 758835SAli.Saidi@ARM.comconst Addr NPtePageShift = PageShift - PteShift; 768983Snate@binkert.orgconst Addr NPtePage = ULL(1) << NPtePageShift; 778835SAli.Saidi@ARM.comconst Addr PteMask = NPtePage - 1; 788835SAli.Saidi@ARM.com 798835SAli.Saidi@ARM.com// User Virtual 809583Snilay@cs.wisc.educonst Addr USegBase = ULL(0x0); 818835SAli.Saidi@ARM.comconst Addr USegEnd = ULL(0x000003ffffffffff); 828835SAli.Saidi@ARM.com 839213Snilay@cs.wisc.edu// Kernel Direct Mapped 848835SAli.Saidi@ARM.comconst Addr K0SegBase = ULL(0xfffffc0000000000); 858983Snate@binkert.orgconst Addr K0SegEnd = ULL(0xfffffdffffffffff); 868983Snate@binkert.org 878983Snate@binkert.org// Kernel Virtual 885148SN/Aconst Addr K1SegBase = ULL(0xfffffe0000000000); 899481Snilay@cs.wisc.educonst Addr K1SegEnd = ULL(0xffffffffffffffff); 909481Snilay@cs.wisc.edu 919481Snilay@cs.wisc.edu// For loading... XXX This maybe could be USegEnd?? --ali 925148SN/Aconst Addr LoadAddrMask = ULL(0xffffffffff); 936024SN/A 948835SAli.Saidi@ARM.com//////////////////////////////////////////////////////////////////////// 955148SN/A// 968835SAli.Saidi@ARM.com// Interrupt levels 978835SAli.Saidi@ARM.com// 988835SAli.Saidi@ARM.comenum InterruptLevels 998835SAli.Saidi@ARM.com{ 1009373Snilay@cs.wisc.edu INTLEVEL_SOFTWARE_MIN = 4, 1018835SAli.Saidi@ARM.com INTLEVEL_SOFTWARE_MAX = 19, 1028983Snate@binkert.org 1035148SN/A INTLEVEL_EXTERNAL_MIN = 20, 1045148SN/A INTLEVEL_EXTERNAL_MAX = 34, 1055148SN/A 1065148SN/A INTLEVEL_IRQ0 = 20, 1075148SN/A INTLEVEL_IRQ1 = 21, 1085148SN/A INTINDEX_ETHERNET = 0, 1095148SN/A INTINDEX_SCSI = 1, 1105148SN/A INTLEVEL_IRQ2 = 22, 1115148SN/A INTLEVEL_IRQ3 = 23, 1125148SN/A 1135516SN/A INTLEVEL_SERIAL = 33, 1145148SN/A 1159213Snilay@cs.wisc.edu NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 1165148SN/A}; 1175148SN/A 1185176SN/A// EV5 modes 1195148SN/Aenum mode_type 1205148SN/A{ 1215148SN/A mode_kernel = 0, // kernel 1225410SN/A mode_executive = 1, // executive (unused by unix) 1235148SN/A mode_supervisor = 2, // supervisor (unused by unix) 1245148SN/A mode_user = 3, // user mode 1255148SN/A mode_number // number of modes 1265148SN/A}; 1279039Sgblack@eecs.umich.edu 1285148SN/A// Constants Related to the number of registers 1295148SN/A 1305410SN/Aconst int NumIntArchRegs = 32; 1319583Snilay@cs.wisc.educonst int NumPALShadowRegs = 8; 1327524SN/Aconst int NumFloatArchRegs = 32; 1339150SAli.Saidi@ARM.com// @todo: Figure out what this number really should be. 1349150SAli.Saidi@ARM.comconst int NumMiscArchRegs = 77; 1358983Snate@binkert.org 1365148SN/Aconst int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 1375148SN/Aconst int NumFloatRegs = NumFloatArchRegs; 1388983Snate@binkert.orgconst int NumMiscRegs = NumMiscArchRegs; 1399373Snilay@cs.wisc.edu 1409373Snilay@cs.wisc.educonst int TotalNumRegs = 1418983Snate@binkert.org NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs; 1428983Snate@binkert.org 1435540SN/Aconst int TotalDataRegs = NumIntRegs + NumFloatRegs; 1445410SN/A 1455509SN/A// semantically meaningful register indices 1465148SN/Aconst int ZeroReg = 31; // architecturally meaningful 1475148SN/A// the rest of these depend on the ABI 1488983Snate@binkert.orgconst int StackPointerReg = 30; 1495148SN/Aconst int GlobalPointerReg = 29; 150const int ProcedureValueReg = 27; 151const int ReturnAddressReg = 26; 152const int ReturnValueReg = 0; 153const int FramePointerReg = 15; 154 155const int SyscallNumReg = 0; 156const int FirstArgumentReg = 16; 157const int SyscallPseudoReturnReg = 20; 158const int SyscallSuccessReg = 19; 159 160const int LogVMPageSize = 13; // 8K bytes 161const int VMPageSize = (1 << LogVMPageSize); 162 163const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 164 165const int MachineBytes = 8; 166const int WordBytes = 4; 167const int HalfwordBytes = 2; 168const int ByteBytes = 1; 169 170// return a no-op instruction... used for instruction fetch faults 171// Alpha UNOP (ldq_u r31,0(r0)) 172const ExtMachInst NoopMachInst = 0x2ffe0000; 173 174} // namespace AlphaISA 175 176#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 177