isa_traits.hh revision 6110
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Gabe Black 30 */ 31 32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 33#define __ARCH_ALPHA_ISA_TRAITS_HH__ 34 35namespace LittleEndianGuest {} 36 37#include "arch/alpha/ipr.hh" 38#include "arch/alpha/max_inst_regs.hh" 39#include "arch/alpha/types.hh" 40#include "config/full_system.hh" 41#include "sim/host.hh" 42 43class StaticInstPtr; 44 45namespace AlphaISA { 46 47using namespace LittleEndianGuest; 48using AlphaISAInst::MaxInstSrcRegs; 49using AlphaISAInst::MaxInstDestRegs; 50 51// These enumerate all the registers for dependence tracking. 52enum DependenceTags { 53 // 0..31 are the integer regs 0..31 54 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 55 FP_Base_DepTag = 40, 56 Ctrl_Base_DepTag = 72 57}; 58 59StaticInstPtr decodeInst(ExtMachInst); 60 61// Alpha Does NOT have a delay slot 62#define ISA_HAS_DELAY_SLOT 0 63 64const Addr PageShift = 13; 65const Addr PageBytes = ULL(1) << PageShift; 66const Addr PageMask = ~(PageBytes - 1); 67const Addr PageOffset = PageBytes - 1; 68 69//////////////////////////////////////////////////////////////////////// 70// 71// Translation stuff 72// 73 74const Addr PteShift = 3; 75const Addr NPtePageShift = PageShift - PteShift; 76const Addr NPtePage = ULL(1) << NPtePageShift; 77const Addr PteMask = NPtePage - 1; 78 79// User Virtual 80const Addr USegBase = ULL(0x0); 81const Addr USegEnd = ULL(0x000003ffffffffff); 82 83// Kernel Direct Mapped 84const Addr K0SegBase = ULL(0xfffffc0000000000); 85const Addr K0SegEnd = ULL(0xfffffdffffffffff); 86 87// Kernel Virtual 88const Addr K1SegBase = ULL(0xfffffe0000000000); 89const Addr K1SegEnd = ULL(0xffffffffffffffff); 90 91// For loading... XXX This maybe could be USegEnd?? --ali 92const Addr LoadAddrMask = ULL(0xffffffffff); 93 94//////////////////////////////////////////////////////////////////////// 95// 96// Interrupt levels 97// 98enum InterruptLevels 99{ 100 INTLEVEL_SOFTWARE_MIN = 4, 101 INTLEVEL_SOFTWARE_MAX = 19, 102 103 INTLEVEL_EXTERNAL_MIN = 20, 104 INTLEVEL_EXTERNAL_MAX = 34, 105 106 INTLEVEL_IRQ0 = 20, 107 INTLEVEL_IRQ1 = 21, 108 INTINDEX_ETHERNET = 0, 109 INTINDEX_SCSI = 1, 110 INTLEVEL_IRQ2 = 22, 111 INTLEVEL_IRQ3 = 23, 112 113 INTLEVEL_SERIAL = 33, 114 115 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 116}; 117 118// EV5 modes 119enum mode_type 120{ 121 mode_kernel = 0, // kernel 122 mode_executive = 1, // executive (unused by unix) 123 mode_supervisor = 2, // supervisor (unused by unix) 124 mode_user = 3, // user mode 125 mode_number // number of modes 126}; 127 128// Constants Related to the number of registers 129 130const int NumIntArchRegs = 32; 131const int NumPALShadowRegs = 8; 132const int NumFloatArchRegs = 32; 133// @todo: Figure out what this number really should be. 134const int NumMiscArchRegs = 77; 135 136const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 137const int NumFloatRegs = NumFloatArchRegs; 138const int NumMiscRegs = NumMiscArchRegs; 139 140const int TotalNumRegs = 141 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs; 142 143const int TotalDataRegs = NumIntRegs + NumFloatRegs; 144 145// semantically meaningful register indices 146const int ZeroReg = 31; // architecturally meaningful 147// the rest of these depend on the ABI 148const int StackPointerReg = 30; 149const int GlobalPointerReg = 29; 150const int ProcedureValueReg = 27; 151const int ReturnAddressReg = 26; 152const int ReturnValueReg = 0; 153const int FramePointerReg = 15; 154 155const int SyscallNumReg = 0; 156const int FirstArgumentReg = 16; 157const int SyscallPseudoReturnReg = 20; 158const int SyscallSuccessReg = 19; 159 160const int LogVMPageSize = 13; // 8K bytes 161const int VMPageSize = (1 << LogVMPageSize); 162 163const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 164 165const int MachineBytes = 8; 166const int WordBytes = 4; 167const int HalfwordBytes = 2; 168const int ByteBytes = 1; 169 170// return a no-op instruction... used for instruction fetch faults 171// Alpha UNOP (ldq_u r31,0(r0)) 172const ExtMachInst NoopMachInst = 0x2ffe0000; 173 174} // namespace AlphaISA 175 176#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 177