isa_traits.hh revision 5958:2d9737bf3c2f
110428Sandreas.hansson@arm.com/* 210428Sandreas.hansson@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 310428Sandreas.hansson@arm.com * All rights reserved. 410428Sandreas.hansson@arm.com * 510428Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 610428Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 710428Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 810428Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 910428Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 1010428Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 1110428Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 1210428Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 1310428Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 1410428Sandreas.hansson@arm.com * this software without specific prior written permission. 1510428Sandreas.hansson@arm.com * 1610428Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710428Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810428Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910428Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010428Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110428Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210428Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310428Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410428Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510428Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610428Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710428Sandreas.hansson@arm.com * 2810428Sandreas.hansson@arm.com * Authors: Steve Reinhardt 2910428Sandreas.hansson@arm.com * Gabe Black 3010428Sandreas.hansson@arm.com */ 3110428Sandreas.hansson@arm.com 3210428Sandreas.hansson@arm.com#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 3310428Sandreas.hansson@arm.com#define __ARCH_ALPHA_ISA_TRAITS_HH__ 3410428Sandreas.hansson@arm.com 3510428Sandreas.hansson@arm.comnamespace LittleEndianGuest {} 3610428Sandreas.hansson@arm.com 3710428Sandreas.hansson@arm.com#include "arch/alpha/ipr.hh" 3810428Sandreas.hansson@arm.com#include "arch/alpha/max_inst_regs.hh" 3910428Sandreas.hansson@arm.com#include "arch/alpha/types.hh" 4010428Sandreas.hansson@arm.com#include "config/full_system.hh" 4110428Sandreas.hansson@arm.com#include "sim/host.hh" 4210428Sandreas.hansson@arm.com 4310428Sandreas.hansson@arm.comclass StaticInstPtr; 4410428Sandreas.hansson@arm.com 4512266Sradhika.jagtap@arm.comnamespace AlphaISA { 4612266Sradhika.jagtap@arm.com 4711555Sjungma@eit.uni-kl.deusing namespace LittleEndianGuest; 4811555Sjungma@eit.uni-kl.deusing AlphaISAInst::MaxInstSrcRegs; 4911555Sjungma@eit.uni-kl.deusing AlphaISAInst::MaxInstDestRegs; 5011555Sjungma@eit.uni-kl.de 5110428Sandreas.hansson@arm.com// These enumerate all the registers for dependence tracking. 5210428Sandreas.hansson@arm.comenum DependenceTags { 5311555Sjungma@eit.uni-kl.de // 0..31 are the integer regs 0..31 5410428Sandreas.hansson@arm.com // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 5510428Sandreas.hansson@arm.com FP_Base_DepTag = 40, 5611555Sjungma@eit.uni-kl.de Ctrl_Base_DepTag = 72 5710428Sandreas.hansson@arm.com}; 5810428Sandreas.hansson@arm.com 5910428Sandreas.hansson@arm.comStaticInstPtr decodeInst(ExtMachInst); 6010428Sandreas.hansson@arm.com 6110428Sandreas.hansson@arm.com// Alpha Does NOT have a delay slot 6210428Sandreas.hansson@arm.com#define ISA_HAS_DELAY_SLOT 0 6310428Sandreas.hansson@arm.com 6410428Sandreas.hansson@arm.comconst Addr PageShift = 13; 6510428Sandreas.hansson@arm.comconst Addr PageBytes = ULL(1) << PageShift; 6610428Sandreas.hansson@arm.comconst Addr PageMask = ~(PageBytes - 1); 6710428Sandreas.hansson@arm.comconst Addr PageOffset = PageBytes - 1; 6810428Sandreas.hansson@arm.com 6910428Sandreas.hansson@arm.com//////////////////////////////////////////////////////////////////////// 7010428Sandreas.hansson@arm.com// 7110428Sandreas.hansson@arm.com// Translation stuff 7210428Sandreas.hansson@arm.com// 7310428Sandreas.hansson@arm.com 7410428Sandreas.hansson@arm.comconst Addr PteShift = 3; 7510428Sandreas.hansson@arm.comconst Addr NPtePageShift = PageShift - PteShift; 7610428Sandreas.hansson@arm.comconst Addr NPtePage = ULL(1) << NPtePageShift; 7710428Sandreas.hansson@arm.comconst Addr PteMask = NPtePage - 1; 7810428Sandreas.hansson@arm.com 7910428Sandreas.hansson@arm.com// User Virtual 8010428Sandreas.hansson@arm.comconst Addr USegBase = ULL(0x0); 8110428Sandreas.hansson@arm.comconst Addr USegEnd = ULL(0x000003ffffffffff); 8210428Sandreas.hansson@arm.com 8312266Sradhika.jagtap@arm.com// Kernel Direct Mapped 8410428Sandreas.hansson@arm.comconst Addr K0SegBase = ULL(0xfffffc0000000000); 8510428Sandreas.hansson@arm.comconst Addr K0SegEnd = ULL(0xfffffdffffffffff); 8610428Sandreas.hansson@arm.com 8710428Sandreas.hansson@arm.com// Kernel Virtual 8810428Sandreas.hansson@arm.comconst Addr K1SegBase = ULL(0xfffffe0000000000); 8910428Sandreas.hansson@arm.comconst Addr K1SegEnd = ULL(0xffffffffffffffff); 9010428Sandreas.hansson@arm.com 9110428Sandreas.hansson@arm.com// For loading... XXX This maybe could be USegEnd?? --ali 9210428Sandreas.hansson@arm.comconst Addr LoadAddrMask = ULL(0xffffffffff); 9310428Sandreas.hansson@arm.com 9410428Sandreas.hansson@arm.com//////////////////////////////////////////////////////////////////////// 9510428Sandreas.hansson@arm.com// 9612266Sradhika.jagtap@arm.com// Interrupt levels 9710428Sandreas.hansson@arm.com// 9810428Sandreas.hansson@arm.comenum InterruptLevels 9910428Sandreas.hansson@arm.com{ 10010428Sandreas.hansson@arm.com INTLEVEL_SOFTWARE_MIN = 4, 10110428Sandreas.hansson@arm.com INTLEVEL_SOFTWARE_MAX = 19, 10212266Sradhika.jagtap@arm.com 10310428Sandreas.hansson@arm.com INTLEVEL_EXTERNAL_MIN = 20, 10410428Sandreas.hansson@arm.com INTLEVEL_EXTERNAL_MAX = 34, 10510428Sandreas.hansson@arm.com 10610428Sandreas.hansson@arm.com INTLEVEL_IRQ0 = 20, 10710428Sandreas.hansson@arm.com INTLEVEL_IRQ1 = 21, 10810428Sandreas.hansson@arm.com INTINDEX_ETHERNET = 0, 10910428Sandreas.hansson@arm.com INTINDEX_SCSI = 1, 11010428Sandreas.hansson@arm.com INTLEVEL_IRQ2 = 22, 11110428Sandreas.hansson@arm.com INTLEVEL_IRQ3 = 23, 11212266Sradhika.jagtap@arm.com 11310428Sandreas.hansson@arm.com INTLEVEL_SERIAL = 33, 11410428Sandreas.hansson@arm.com 11510428Sandreas.hansson@arm.com NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 11610428Sandreas.hansson@arm.com}; 11710428Sandreas.hansson@arm.com 11812266Sradhika.jagtap@arm.com// EV5 modes 11910428Sandreas.hansson@arm.comenum mode_type 12010428Sandreas.hansson@arm.com{ 12110428Sandreas.hansson@arm.com mode_kernel = 0, // kernel 12210428Sandreas.hansson@arm.com mode_executive = 1, // executive (unused by unix) 12310428Sandreas.hansson@arm.com mode_supervisor = 2, // supervisor (unused by unix) 124 mode_user = 3, // user mode 125 mode_number // number of modes 126}; 127 128// Constants Related to the number of registers 129 130const int NumIntArchRegs = 32; 131const int NumPALShadowRegs = 8; 132const int NumFloatArchRegs = 32; 133// @todo: Figure out what this number really should be. 134const int NumMiscArchRegs = 77; 135 136const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 137const int NumFloatRegs = NumFloatArchRegs; 138const int NumMiscRegs = NumMiscArchRegs; 139 140const int TotalNumRegs = 141 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs; 142 143const int TotalDataRegs = NumIntRegs + NumFloatRegs; 144 145// semantically meaningful register indices 146const int ZeroReg = 31; // architecturally meaningful 147// the rest of these depend on the ABI 148const int StackPointerReg = 30; 149const int GlobalPointerReg = 29; 150const int ProcedureValueReg = 27; 151const int ReturnAddressReg = 26; 152const int ReturnValueReg = 0; 153const int FramePointerReg = 15; 154 155const int SyscallNumReg = 0; 156const int FirstArgumentReg = 16; 157const int SyscallPseudoReturnReg = 20; 158 159const int LogVMPageSize = 13; // 8K bytes 160const int VMPageSize = (1 << LogVMPageSize); 161 162const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 163 164const int MachineBytes = 8; 165const int WordBytes = 4; 166const int HalfwordBytes = 2; 167const int ByteBytes = 1; 168 169// return a no-op instruction... used for instruction fetch faults 170// Alpha UNOP (ldq_u r31,0(r0)) 171const ExtMachInst NoopMachInst = 0x2ffe0000; 172 173} // namespace AlphaISA 174 175#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 176