isa_traits.hh revision 56
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ISA_TRAITS_HH__ 30#define __ISA_TRAITS_HH__ 31 32#include "sim/host.hh" 33#include "targetarch/faults.hh" 34#include "base/misc.hh" 35 36class CPU; 37class IniFile; 38 39#define TARGET_ALPHA 40 41template <class ISA> class StaticInst; 42template <class ISA> class StaticInstPtr; 43 44class AlphaISA 45{ 46 public: 47 48 typedef uint32_t MachInst; 49 typedef uint64_t Addr; 50 typedef uint8_t RegIndex; 51 52 enum { 53 MemoryEnd = 0xffffffffffffffffULL, 54 55 NumIntRegs = 32, 56 NumFloatRegs = 32, 57 NumMiscRegs = 32, 58 59 MaxRegsOfAnyType = 32, 60 // Static instruction parameters 61 MaxInstSrcRegs = 3, 62 MaxInstDestRegs = 2, 63 64 // semantically meaningful register indices 65 ZeroReg = 31, // architecturally meaningful 66 // the rest of these depend on the ABI 67 StackPointerReg = 30, 68 GlobalPointerReg = 29, 69 ReturnAddressReg = 26, 70 ReturnValueReg = 0, 71 ArgumentReg0 = 16, 72 ArgumentReg1 = 17, 73 ArgumentReg2 = 18, 74 ArgumentReg3 = 19, 75 ArgumentReg4 = 20, 76 ArgumentReg5 = 21, 77 78 LogVMPageSize = 13, // 8K bytes 79 VMPageSize = (1 << LogVMPageSize), 80 81 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned 82 83 WordBytes = 4, 84 HalfwordBytes = 2, 85 ByteBytes = 1, 86 DepNA = 0, 87 }; 88 89 // These enumerate all the registers for dependence tracking. 90 enum DependenceTags { 91 // 0..31 are the integer regs 0..31 92 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 93 FP_Base_DepTag = 32, 94 Ctrl_Base_DepTag = 64, 95 Fpcr_DepTag = 64, // floating point control register 96 Uniq_DepTag = 65, 97 IPR_Base_DepTag = 66 98 }; 99 100 typedef uint64_t IntReg; 101 typedef IntReg IntRegFile[NumIntRegs]; 102 103 // floating point register file entry type 104 typedef union { 105 uint64_t q; 106 double d; 107 } FloatReg; 108 109 typedef union { 110 uint64_t q[NumFloatRegs]; // integer qword view 111 double d[NumFloatRegs]; // double-precision floating point view 112 } FloatRegFile; 113 114 // control register file contents 115 typedef uint64_t MiscReg; 116 typedef struct { 117 uint64_t fpcr; // floating point condition codes 118 uint64_t uniq; // process-unique register 119 bool lock_flag; // lock flag for LL/SC 120 Addr lock_addr; // lock address for LL/SC 121 } MiscRegFile; 122 123#ifdef FULL_SYSTEM 124 125 typedef uint64_t InternalProcReg; 126 127#include "targetarch/isa_fullsys_traits.hh" 128 129#else 130 enum { 131 NumInternalProcRegs = 0 132 }; 133#endif 134 135 enum { 136 TotalNumRegs = 137 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs 138 }; 139 140 typedef union { 141 IntReg intreg; 142 FloatReg fpreg; 143 MiscReg ctrlreg; 144 } AnyReg; 145 146 struct RegFile { 147 IntRegFile intRegFile; // (signed) integer register file 148 FloatRegFile floatRegFile; // floating point register file 149 MiscRegFile miscRegs; // control register file 150 Addr pc; // program counter 151 Addr npc; // next-cycle program counter 152#ifdef FULL_SYSTEM 153 IntReg palregs[NumIntRegs]; // PAL shadow registers 154 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 155 int intrlock; // interrupt register lock flag 156 int intrflag; // interrupt flag 157 bool pal_shadow; // using pal_shadow registers 158#endif // FULL_SYSTEM 159 // Are these architectural, or just for convenience? 160 uint8_t opcode, ra; // current instruction details (for intr's) 161 }; 162 163 static StaticInstPtr<AlphaISA> decodeInst(MachInst); 164 165 enum annotes { 166 ANNOTE_NONE = 0, 167 // An impossible number for instruction annotations 168 ITOUCH_ANNOTE = 0xffffffff, 169 }; 170 171#if 0 172 static inline Addr 173 extractInstructionPrefetchTarget(const MachInst &IR, Addr PC) { 174 return(0); 175 } 176#endif 177 178 static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 179 panic("register classification not implemented"); 180 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 181 } 182 183 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 184 panic("register classification not implemented"); 185 return (reg >= 9 && reg <= 15); 186 } 187 188 static inline bool isCallerSaveFloatRegister(unsigned int reg) { 189 panic("register classification not implemented"); 190 return false; 191 } 192 193 static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 194 panic("register classification not implemented"); 195 return false; 196 } 197 198 static inline Addr alignAddress(const Addr &addr, 199 unsigned int nbytes) { 200 return (addr & ~(nbytes - 1)); 201 } 202 203 // Instruction address compression hooks 204 static inline Addr realPCToFetchPC(const Addr &addr) { 205 return addr; 206 } 207 208 static inline Addr fetchPCToRealPC(const Addr &addr) { 209 return addr; 210 } 211 212 // the size of "fetched" instructions (not necessarily the size 213 // of real instructions for PISA) 214 static inline size_t fetchInstSize() { 215 return sizeof(MachInst); 216 } 217 218 static inline MachInst makeRegisterCopy(int dest, int src) { 219 panic("makeRegisterCopy not implemented"); 220 return 0; 221 } 222 223 // Machine operations 224 225 static void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 226 int regnum); 227 228 static void restoreMachineReg(RegFile ®s, const AnyReg ®, 229 int regnum); 230 231#if 0 232 static void serializeSpecialRegs(const Serializeable::Proxy &proxy, 233 const RegFile ®s); 234 235 static void unserializeSpecialRegs(IniFile &db, 236 const std::string &category, 237 ConfigNode *node, 238 RegFile ®s); 239#endif 240}; 241 242 243typedef AlphaISA TheISA; 244 245typedef TheISA::MachInst MachInst; 246typedef TheISA::Addr Addr; 247typedef TheISA::RegIndex RegIndex; 248typedef TheISA::IntReg IntReg; 249typedef TheISA::IntRegFile IntRegFile; 250typedef TheISA::FloatReg FloatReg; 251typedef TheISA::FloatRegFile FloatRegFile; 252typedef TheISA::MiscReg MiscReg; 253typedef TheISA::MiscRegFile MiscRegFile; 254typedef TheISA::AnyReg AnyReg; 255typedef TheISA::RegFile RegFile; 256 257const int NumIntRegs = TheISA::NumIntRegs; 258const int NumFloatRegs = TheISA::NumFloatRegs; 259const int NumMiscRegs = TheISA::NumMiscRegs; 260const int TotalNumRegs = TheISA::TotalNumRegs; 261const int VMPageSize = TheISA::VMPageSize; 262const int LogVMPageSize = TheISA::LogVMPageSize; 263const int ZeroReg = TheISA::ZeroReg; 264const int StackPointerReg = TheISA::StackPointerReg; 265const int GlobalPointerReg = TheISA::GlobalPointerReg; 266const int ReturnAddressReg = TheISA::ReturnAddressReg; 267const int ReturnValueReg = TheISA::ReturnValueReg; 268const int ArgumentReg0 = TheISA::ArgumentReg0; 269const int ArgumentReg1 = TheISA::ArgumentReg1; 270const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; 271 272#ifdef FULL_SYSTEM 273typedef TheISA::InternalProcReg InternalProcReg; 274const int NumInternalProcRegs = TheISA::NumInternalProcRegs; 275const int NumInterruptLevels = TheISA::NumInterruptLevels; 276 277// more stuff that should be imported here, but I'm too tired to do it 278// right now... 279#include "targetarch/ev5.hh" 280#endif 281 282#endif // __ALPHA_ISA_H__ 283