isa_traits.hh revision 3454
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Gabe Black 30 */ 31 32#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 33#define __ARCH_ALPHA_ISA_TRAITS_HH__ 34 35namespace LittleEndianGuest {} 36 37#include "arch/alpha/types.hh" 38#include "config/full_system.hh" 39#include "sim/host.hh" 40 41class StaticInstPtr; 42 43namespace AlphaISA 44{ 45 using namespace LittleEndianGuest; 46 47 // These enumerate all the registers for dependence tracking. 48 enum DependenceTags { 49 // 0..31 are the integer regs 0..31 50 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 51 FP_Base_DepTag = 40, 52 Ctrl_Base_DepTag = 72, 53 Fpcr_DepTag = 72, // floating point control register 54 Uniq_DepTag = 73, 55 Lock_Flag_DepTag = 74, 56 Lock_Addr_DepTag = 75, 57 Intr_Flag_DepTag = 76, 58 IPR_Base_DepTag = 77 59 }; 60 61 StaticInstPtr decodeInst(ExtMachInst); 62 63 // Alpha Does NOT have a delay slot 64 #define ISA_HAS_DELAY_SLOT 0 65 66 const Addr PageShift = 13; 67 const Addr PageBytes = ULL(1) << PageShift; 68 const Addr PageMask = ~(PageBytes - 1); 69 const Addr PageOffset = PageBytes - 1; 70 71#if FULL_SYSTEM 72 73 //////////////////////////////////////////////////////////////////////// 74 // 75 // Translation stuff 76 // 77 78 const Addr PteShift = 3; 79 const Addr NPtePageShift = PageShift - PteShift; 80 const Addr NPtePage = ULL(1) << NPtePageShift; 81 const Addr PteMask = NPtePage - 1; 82 83 // User Virtual 84 const Addr USegBase = ULL(0x0); 85 const Addr USegEnd = ULL(0x000003ffffffffff); 86 87 // Kernel Direct Mapped 88 const Addr K0SegBase = ULL(0xfffffc0000000000); 89 const Addr K0SegEnd = ULL(0xfffffdffffffffff); 90 91 // Kernel Virtual 92 const Addr K1SegBase = ULL(0xfffffe0000000000); 93 const Addr K1SegEnd = ULL(0xffffffffffffffff); 94 95 // For loading... XXX This maybe could be USegEnd?? --ali 96 const Addr LoadAddrMask = ULL(0xffffffffff); 97 98 //////////////////////////////////////////////////////////////////////// 99 // 100 // Interrupt levels 101 // 102 enum InterruptLevels 103 { 104 INTLEVEL_SOFTWARE_MIN = 4, 105 INTLEVEL_SOFTWARE_MAX = 19, 106 107 INTLEVEL_EXTERNAL_MIN = 20, 108 INTLEVEL_EXTERNAL_MAX = 34, 109 110 INTLEVEL_IRQ0 = 20, 111 INTLEVEL_IRQ1 = 21, 112 INTINDEX_ETHERNET = 0, 113 INTINDEX_SCSI = 1, 114 INTLEVEL_IRQ2 = 22, 115 INTLEVEL_IRQ3 = 23, 116 117 INTLEVEL_SERIAL = 33, 118 119 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 120 }; 121 122 123 // EV5 modes 124 enum mode_type 125 { 126 mode_kernel = 0, // kernel 127 mode_executive = 1, // executive (unused by unix) 128 mode_supervisor = 2, // supervisor (unused by unix) 129 mode_user = 3, // user mode 130 mode_number // number of modes 131 }; 132 133#endif 134 135#if FULL_SYSTEM 136 //////////////////////////////////////////////////////////////////////// 137 // 138 // Internal Processor Reigsters 139 // 140 enum md_ipr_names 141 { 142 IPR_ISR = 0x100, // interrupt summary register 143 IPR_ITB_TAG = 0x101, // ITLB tag register 144 IPR_ITB_PTE = 0x102, // ITLB page table entry register 145 IPR_ITB_ASN = 0x103, // ITLB address space register 146 IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register 147 IPR_ITB_IA = 0x105, // ITLB invalidate all register 148 IPR_ITB_IAP = 0x106, // ITLB invalidate all process register 149 IPR_ITB_IS = 0x107, // ITLB invalidate select register 150 IPR_SIRR = 0x108, // software interrupt request register 151 IPR_ASTRR = 0x109, // asynchronous system trap request register 152 IPR_ASTER = 0x10a, // asynchronous system trap enable register 153 IPR_EXC_ADDR = 0x10b, // exception address register 154 IPR_EXC_SUM = 0x10c, // exception summary register 155 IPR_EXC_MASK = 0x10d, // exception mask register 156 IPR_PAL_BASE = 0x10e, // PAL base address register 157 IPR_ICM = 0x10f, // instruction current mode 158 IPR_IPLR = 0x110, // interrupt priority level register 159 IPR_INTID = 0x111, // interrupt ID register 160 IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register 161 IPR_IVPTBR = 0x113, // virtual page table base register 162 IPR_HWINT_CLR = 0x115, // H/W interrupt clear register 163 IPR_SL_XMIT = 0x116, // serial line transmit register 164 IPR_SL_RCV = 0x117, // serial line receive register 165 IPR_ICSR = 0x118, // instruction control and status register 166 IPR_IC_FLUSH = 0x119, // instruction cache flush control 167 IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register 168 IPR_PMCTR = 0x11c, // performance counter register 169 170 // PAL temporary registers... 171 // register meanings gleaned from osfpal.s source code 172 IPR_PALtemp0 = 0x140, // local scratch 173 IPR_PALtemp1 = 0x141, // local scratch 174 IPR_PALtemp2 = 0x142, // entUna 175 IPR_PALtemp3 = 0x143, // CPU specific impure area pointer 176 IPR_PALtemp4 = 0x144, // memory management temp 177 IPR_PALtemp5 = 0x145, // memory management temp 178 IPR_PALtemp6 = 0x146, // memory management temp 179 IPR_PALtemp7 = 0x147, // entIF 180 IPR_PALtemp8 = 0x148, // intmask 181 IPR_PALtemp9 = 0x149, // entSys 182 IPR_PALtemp10 = 0x14a, // ?? 183 IPR_PALtemp11 = 0x14b, // entInt 184 IPR_PALtemp12 = 0x14c, // entArith 185 IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL 186 IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL 187 IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL 188 IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> 189 IPR_PALtemp17 = 0x151, // sysval 190 IPR_PALtemp18 = 0x152, // usp 191 IPR_PALtemp19 = 0x153, // ksp 192 IPR_PALtemp20 = 0x154, // PTBR 193 IPR_PALtemp21 = 0x155, // entMM 194 IPR_PALtemp22 = 0x156, // kgp 195 IPR_PALtemp23 = 0x157, // PCBB 196 197 IPR_DTB_ASN = 0x200, // DTLB address space number register 198 IPR_DTB_CM = 0x201, // DTLB current mode register 199 IPR_DTB_TAG = 0x202, // DTLB tag register 200 IPR_DTB_PTE = 0x203, // DTLB page table entry register 201 IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register 202 203 IPR_MM_STAT = 0x205, // data MMU fault status register 204 IPR_VA = 0x206, // fault virtual address register 205 IPR_VA_FORM = 0x207, // formatted virtual address register 206 IPR_MVPTBR = 0x208, // MTU virtual page table base register 207 IPR_DTB_IAP = 0x209, // DTLB invalidate all process register 208 IPR_DTB_IA = 0x20a, // DTLB invalidate all register 209 IPR_DTB_IS = 0x20b, // DTLB invalidate single register 210 IPR_ALT_MODE = 0x20c, // alternate mode register 211 IPR_CC = 0x20d, // cycle counter register 212 IPR_CC_CTL = 0x20e, // cycle counter control register 213 IPR_MCSR = 0x20f, // MTU control register 214 215 IPR_DC_FLUSH = 0x210, 216 IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register 217 IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register 218 IPR_DC_TEST_TAG = 0x214, // Dcache test tag register 219 IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register 220 IPR_DC_MODE = 0x216, // Dcache mode register 221 IPR_MAF_MODE = 0x217, // miss address file mode register 222 223 NumInternalProcRegs // number of IPR registers 224 }; 225#else 226 const int NumInternalProcRegs = 0; 227#endif 228 229 // Constants Related to the number of registers 230 231 const int NumIntArchRegs = 32; 232 const int NumPALShadowRegs = 8; 233 const int NumFloatArchRegs = 32; 234 // @todo: Figure out what this number really should be. 235 const int NumMiscArchRegs = 32; 236 237 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 238 const int NumFloatRegs = NumFloatArchRegs; 239 const int NumMiscRegs = NumMiscArchRegs; 240 241 const int TotalNumRegs = NumIntRegs + NumFloatRegs + 242 NumMiscRegs + NumInternalProcRegs; 243 244 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 245 246 // Static instruction parameters 247 const int MaxInstSrcRegs = 3; 248 const int MaxInstDestRegs = 2; 249 250 // semantically meaningful register indices 251 const int ZeroReg = 31; // architecturally meaningful 252 // the rest of these depend on the ABI 253 const int StackPointerReg = 30; 254 const int GlobalPointerReg = 29; 255 const int ProcedureValueReg = 27; 256 const int ReturnAddressReg = 26; 257 const int ReturnValueReg = 0; 258 const int FramePointerReg = 15; 259 const int ArgumentReg0 = 16; 260 const int ArgumentReg1 = 17; 261 const int ArgumentReg2 = 18; 262 const int ArgumentReg3 = 19; 263 const int ArgumentReg4 = 20; 264 const int ArgumentReg5 = 21; 265 const int SyscallNumReg = ReturnValueReg; 266 const int SyscallPseudoReturnReg = ArgumentReg4; 267 const int SyscallSuccessReg = 19; 268 269 const int LogVMPageSize = 13; // 8K bytes 270 const int VMPageSize = (1 << LogVMPageSize); 271 272 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 273 274 const int MachineBytes = 8; 275 const int WordBytes = 4; 276 const int HalfwordBytes = 2; 277 const int ByteBytes = 1; 278 279 // return a no-op instruction... used for instruction fetch faults 280 // Alpha UNOP (ldq_u r31,0(r0)) 281 const ExtMachInst NoopMachInst = 0x2ffe0000; 282 283 // redirected register map, really only used for the full system case. 284 extern const int reg_redir[NumIntRegs]; 285 286}; 287 288#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 289