isa_traits.hh revision 6974
12SN/A/* 21458SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Gabe Black 302SN/A */ 312SN/A 321147SN/A#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 331147SN/A#define __ARCH_ALPHA_ISA_TRAITS_HH__ 342SN/A 352037SN/Anamespace LittleEndianGuest {} 362037SN/A 372428SN/A#include "arch/alpha/types.hh" 386216Snate@binkert.org#include "base/types.hh" 391858SN/A#include "config/full_system.hh" 402SN/A 412107SN/Aclass StaticInstPtr; 422SN/A 435569Snate@binkert.orgnamespace AlphaISA { 442238SN/A 455569Snate@binkert.orgusing namespace LittleEndianGuest; 462107SN/A 475569Snate@binkert.orgStaticInstPtr decodeInst(ExtMachInst); 485569Snate@binkert.org 495569Snate@binkert.org// Alpha Does NOT have a delay slot 505569Snate@binkert.org#define ISA_HAS_DELAY_SLOT 0 515569Snate@binkert.org 525569Snate@binkert.orgconst Addr PageShift = 13; 535569Snate@binkert.orgconst Addr PageBytes = ULL(1) << PageShift; 545569Snate@binkert.orgconst Addr PageMask = ~(PageBytes - 1); 555569Snate@binkert.orgconst Addr PageOffset = PageBytes - 1; 565569Snate@binkert.org 575569Snate@binkert.org//////////////////////////////////////////////////////////////////////// 585569Snate@binkert.org// 595569Snate@binkert.org// Translation stuff 605569Snate@binkert.org// 615569Snate@binkert.org 625569Snate@binkert.orgconst Addr PteShift = 3; 635569Snate@binkert.orgconst Addr NPtePageShift = PageShift - PteShift; 645569Snate@binkert.orgconst Addr NPtePage = ULL(1) << NPtePageShift; 655569Snate@binkert.orgconst Addr PteMask = NPtePage - 1; 665569Snate@binkert.org 675569Snate@binkert.org// User Virtual 685569Snate@binkert.orgconst Addr USegBase = ULL(0x0); 695569Snate@binkert.orgconst Addr USegEnd = ULL(0x000003ffffffffff); 705569Snate@binkert.org 715569Snate@binkert.org// Kernel Direct Mapped 725569Snate@binkert.orgconst Addr K0SegBase = ULL(0xfffffc0000000000); 735569Snate@binkert.orgconst Addr K0SegEnd = ULL(0xfffffdffffffffff); 745569Snate@binkert.org 755569Snate@binkert.org// Kernel Virtual 765569Snate@binkert.orgconst Addr K1SegBase = ULL(0xfffffe0000000000); 775569Snate@binkert.orgconst Addr K1SegEnd = ULL(0xffffffffffffffff); 785569Snate@binkert.org 795569Snate@binkert.org// For loading... XXX This maybe could be USegEnd?? --ali 805569Snate@binkert.orgconst Addr LoadAddrMask = ULL(0xffffffffff); 815569Snate@binkert.org 825569Snate@binkert.org//////////////////////////////////////////////////////////////////////// 835569Snate@binkert.org// 845569Snate@binkert.org// Interrupt levels 855569Snate@binkert.org// 865569Snate@binkert.orgenum InterruptLevels 875569Snate@binkert.org{ 885569Snate@binkert.org INTLEVEL_SOFTWARE_MIN = 4, 895569Snate@binkert.org INTLEVEL_SOFTWARE_MAX = 19, 905569Snate@binkert.org 915569Snate@binkert.org INTLEVEL_EXTERNAL_MIN = 20, 925569Snate@binkert.org INTLEVEL_EXTERNAL_MAX = 34, 935569Snate@binkert.org 945569Snate@binkert.org INTLEVEL_IRQ0 = 20, 955569Snate@binkert.org INTLEVEL_IRQ1 = 21, 965569Snate@binkert.org INTINDEX_ETHERNET = 0, 975569Snate@binkert.org INTINDEX_SCSI = 1, 985569Snate@binkert.org INTLEVEL_IRQ2 = 22, 995569Snate@binkert.org INTLEVEL_IRQ3 = 23, 1005569Snate@binkert.org 1015569Snate@binkert.org INTLEVEL_SERIAL = 33, 1025569Snate@binkert.org 1035569Snate@binkert.org NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 1045569Snate@binkert.org}; 1055569Snate@binkert.org 1065569Snate@binkert.org// EV5 modes 1075569Snate@binkert.orgenum mode_type 1085569Snate@binkert.org{ 1095569Snate@binkert.org mode_kernel = 0, // kernel 1105569Snate@binkert.org mode_executive = 1, // executive (unused by unix) 1115569Snate@binkert.org mode_supervisor = 2, // supervisor (unused by unix) 1125569Snate@binkert.org mode_user = 3, // user mode 1135569Snate@binkert.org mode_number // number of modes 1145569Snate@binkert.org}; 1155569Snate@binkert.org 1165569Snate@binkert.org// Constants Related to the number of registers 1175569Snate@binkert.org 1186227Snate@binkert.orgenum { 1196227Snate@binkert.org LogVMPageSize = 13, // 8K bytes 1206227Snate@binkert.org VMPageSize = (1 << LogVMPageSize), 1215569Snate@binkert.org 1226227Snate@binkert.org BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned 1235569Snate@binkert.org 1246227Snate@binkert.org MachineBytes = 8, 1256227Snate@binkert.org WordBytes = 4, 1266227Snate@binkert.org HalfwordBytes = 2, 1276227Snate@binkert.org ByteBytes = 1, 1286227Snate@binkert.org}; 1295569Snate@binkert.org 1305569Snate@binkert.org// return a no-op instruction... used for instruction fetch faults 1315569Snate@binkert.org// Alpha UNOP (ldq_u r31,0(r0)) 1325569Snate@binkert.orgconst ExtMachInst NoopMachInst = 0x2ffe0000; 1335569Snate@binkert.org 1346974Stjones1@inf.ed.ac.uk// Memory accesses cannot be unaligned 1356974Stjones1@inf.ed.ac.ukconst bool HasUnalignedMemAcc = false; 1366974Stjones1@inf.ed.ac.uk 1375569Snate@binkert.org} // namespace AlphaISA 1385569Snate@binkert.org 1391147SN/A#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 140