isa_traits.hh revision 4997
12SN/A/* 21458SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Gabe Black 302SN/A */ 312SN/A 321147SN/A#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 331147SN/A#define __ARCH_ALPHA_ISA_TRAITS_HH__ 342SN/A 352037SN/Anamespace LittleEndianGuest {} 362037SN/A 373457Sgblack@eecs.umich.edu#include "arch/alpha/ipr.hh" 382428SN/A#include "arch/alpha/types.hh" 391858SN/A#include "config/full_system.hh" 4056SN/A#include "sim/host.hh" 412SN/A 422107SN/Aclass StaticInstPtr; 432SN/A 442972Sgblack@eecs.umich.edunamespace AlphaISA 452972Sgblack@eecs.umich.edu{ 462972Sgblack@eecs.umich.edu using namespace LittleEndianGuest; 472238SN/A 482972Sgblack@eecs.umich.edu // These enumerate all the registers for dependence tracking. 492972Sgblack@eecs.umich.edu enum DependenceTags { 502972Sgblack@eecs.umich.edu // 0..31 are the integer regs 0..31 512972Sgblack@eecs.umich.edu // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 522972Sgblack@eecs.umich.edu FP_Base_DepTag = 40, 533586Sgblack@eecs.umich.edu Ctrl_Base_DepTag = 72 542972Sgblack@eecs.umich.edu }; 552238SN/A 562972Sgblack@eecs.umich.edu StaticInstPtr decodeInst(ExtMachInst); 572238SN/A 583093Sksewell@umich.edu // Alpha Does NOT have a delay slot 593093Sksewell@umich.edu #define ISA_HAS_DELAY_SLOT 0 603093Sksewell@umich.edu 612972Sgblack@eecs.umich.edu const Addr PageShift = 13; 622972Sgblack@eecs.umich.edu const Addr PageBytes = ULL(1) << PageShift; 632972Sgblack@eecs.umich.edu const Addr PageMask = ~(PageBytes - 1); 642972Sgblack@eecs.umich.edu const Addr PageOffset = PageBytes - 1; 652972Sgblack@eecs.umich.edu 662972Sgblack@eecs.umich.edu 672972Sgblack@eecs.umich.edu //////////////////////////////////////////////////////////////////////// 682972Sgblack@eecs.umich.edu // 692972Sgblack@eecs.umich.edu // Translation stuff 702972Sgblack@eecs.umich.edu // 712972Sgblack@eecs.umich.edu 724997Sgblack@eecs.umich.edu const Addr PteShift = 3; 732972Sgblack@eecs.umich.edu const Addr NPtePageShift = PageShift - PteShift; 742972Sgblack@eecs.umich.edu const Addr NPtePage = ULL(1) << NPtePageShift; 752972Sgblack@eecs.umich.edu const Addr PteMask = NPtePage - 1; 762972Sgblack@eecs.umich.edu 772972Sgblack@eecs.umich.edu // User Virtual 782972Sgblack@eecs.umich.edu const Addr USegBase = ULL(0x0); 792972Sgblack@eecs.umich.edu const Addr USegEnd = ULL(0x000003ffffffffff); 802972Sgblack@eecs.umich.edu 812972Sgblack@eecs.umich.edu // Kernel Direct Mapped 822972Sgblack@eecs.umich.edu const Addr K0SegBase = ULL(0xfffffc0000000000); 832972Sgblack@eecs.umich.edu const Addr K0SegEnd = ULL(0xfffffdffffffffff); 842972Sgblack@eecs.umich.edu 852972Sgblack@eecs.umich.edu // Kernel Virtual 862972Sgblack@eecs.umich.edu const Addr K1SegBase = ULL(0xfffffe0000000000); 872972Sgblack@eecs.umich.edu const Addr K1SegEnd = ULL(0xffffffffffffffff); 882972Sgblack@eecs.umich.edu 892972Sgblack@eecs.umich.edu // For loading... XXX This maybe could be USegEnd?? --ali 902972Sgblack@eecs.umich.edu const Addr LoadAddrMask = ULL(0xffffffffff); 912972Sgblack@eecs.umich.edu 924997Sgblack@eecs.umich.edu#if FULL_SYSTEM 934997Sgblack@eecs.umich.edu 942972Sgblack@eecs.umich.edu //////////////////////////////////////////////////////////////////////// 952972Sgblack@eecs.umich.edu // 962972Sgblack@eecs.umich.edu // Interrupt levels 972972Sgblack@eecs.umich.edu // 982972Sgblack@eecs.umich.edu enum InterruptLevels 992972Sgblack@eecs.umich.edu { 1002972Sgblack@eecs.umich.edu INTLEVEL_SOFTWARE_MIN = 4, 1012972Sgblack@eecs.umich.edu INTLEVEL_SOFTWARE_MAX = 19, 1022972Sgblack@eecs.umich.edu 1032972Sgblack@eecs.umich.edu INTLEVEL_EXTERNAL_MIN = 20, 1042972Sgblack@eecs.umich.edu INTLEVEL_EXTERNAL_MAX = 34, 1052972Sgblack@eecs.umich.edu 1062972Sgblack@eecs.umich.edu INTLEVEL_IRQ0 = 20, 1072972Sgblack@eecs.umich.edu INTLEVEL_IRQ1 = 21, 1082972Sgblack@eecs.umich.edu INTINDEX_ETHERNET = 0, 1092972Sgblack@eecs.umich.edu INTINDEX_SCSI = 1, 1102972Sgblack@eecs.umich.edu INTLEVEL_IRQ2 = 22, 1112972Sgblack@eecs.umich.edu INTLEVEL_IRQ3 = 23, 1122972Sgblack@eecs.umich.edu 1132972Sgblack@eecs.umich.edu INTLEVEL_SERIAL = 33, 1142972Sgblack@eecs.umich.edu 1152972Sgblack@eecs.umich.edu NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 1162972Sgblack@eecs.umich.edu }; 1172972Sgblack@eecs.umich.edu 1184997Sgblack@eecs.umich.edu#endif 1194997Sgblack@eecs.umich.edu 1202972Sgblack@eecs.umich.edu // EV5 modes 1212972Sgblack@eecs.umich.edu enum mode_type 1222972Sgblack@eecs.umich.edu { 1232972Sgblack@eecs.umich.edu mode_kernel = 0, // kernel 1242972Sgblack@eecs.umich.edu mode_executive = 1, // executive (unused by unix) 1252972Sgblack@eecs.umich.edu mode_supervisor = 2, // supervisor (unused by unix) 1262972Sgblack@eecs.umich.edu mode_user = 3, // user mode 1272972Sgblack@eecs.umich.edu mode_number // number of modes 1282972Sgblack@eecs.umich.edu }; 1292238SN/A 1302972Sgblack@eecs.umich.edu // Constants Related to the number of registers 1312512SN/A 1322972Sgblack@eecs.umich.edu const int NumIntArchRegs = 32; 1332972Sgblack@eecs.umich.edu const int NumPALShadowRegs = 8; 1342972Sgblack@eecs.umich.edu const int NumFloatArchRegs = 32; 1352972Sgblack@eecs.umich.edu // @todo: Figure out what this number really should be. 1363964Sgblack@eecs.umich.edu const int NumMiscArchRegs = 77; 1372SN/A 1382972Sgblack@eecs.umich.edu const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 1392972Sgblack@eecs.umich.edu const int NumFloatRegs = NumFloatArchRegs; 1402972Sgblack@eecs.umich.edu const int NumMiscRegs = NumMiscArchRegs; 1412449SN/A 1422972Sgblack@eecs.umich.edu const int TotalNumRegs = NumIntRegs + NumFloatRegs + 1432972Sgblack@eecs.umich.edu NumMiscRegs + NumInternalProcRegs; 1442227SN/A 1452972Sgblack@eecs.umich.edu const int TotalDataRegs = NumIntRegs + NumFloatRegs; 1462SN/A 1472972Sgblack@eecs.umich.edu // Static instruction parameters 1482972Sgblack@eecs.umich.edu const int MaxInstSrcRegs = 3; 1492972Sgblack@eecs.umich.edu const int MaxInstDestRegs = 2; 1502972Sgblack@eecs.umich.edu 1512972Sgblack@eecs.umich.edu // semantically meaningful register indices 1522972Sgblack@eecs.umich.edu const int ZeroReg = 31; // architecturally meaningful 1532972Sgblack@eecs.umich.edu // the rest of these depend on the ABI 1542972Sgblack@eecs.umich.edu const int StackPointerReg = 30; 1552972Sgblack@eecs.umich.edu const int GlobalPointerReg = 29; 1562972Sgblack@eecs.umich.edu const int ProcedureValueReg = 27; 1572972Sgblack@eecs.umich.edu const int ReturnAddressReg = 26; 1582972Sgblack@eecs.umich.edu const int ReturnValueReg = 0; 1592972Sgblack@eecs.umich.edu const int FramePointerReg = 15; 1604772Sgblack@eecs.umich.edu 1614772Sgblack@eecs.umich.edu const int ArgumentReg[] = {16, 17, 18, 19, 20, 21}; 1624772Sgblack@eecs.umich.edu const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 1634772Sgblack@eecs.umich.edu 1642972Sgblack@eecs.umich.edu const int SyscallNumReg = ReturnValueReg; 1654772Sgblack@eecs.umich.edu const int SyscallPseudoReturnReg = ArgumentReg[4]; 1662972Sgblack@eecs.umich.edu const int SyscallSuccessReg = 19; 1672972Sgblack@eecs.umich.edu 1682972Sgblack@eecs.umich.edu const int LogVMPageSize = 13; // 8K bytes 1692972Sgblack@eecs.umich.edu const int VMPageSize = (1 << LogVMPageSize); 1702972Sgblack@eecs.umich.edu 1712972Sgblack@eecs.umich.edu const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 1722972Sgblack@eecs.umich.edu 1732972Sgblack@eecs.umich.edu const int MachineBytes = 8; 1742972Sgblack@eecs.umich.edu const int WordBytes = 4; 1752972Sgblack@eecs.umich.edu const int HalfwordBytes = 2; 1762972Sgblack@eecs.umich.edu const int ByteBytes = 1; 1772972Sgblack@eecs.umich.edu 1782972Sgblack@eecs.umich.edu // return a no-op instruction... used for instruction fetch faults 1792972Sgblack@eecs.umich.edu // Alpha UNOP (ldq_u r31,0(r0)) 1802972Sgblack@eecs.umich.edu const ExtMachInst NoopMachInst = 0x2ffe0000; 1812972Sgblack@eecs.umich.edu 1822264SN/A}; 1832107SN/A 1841147SN/A#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 185