isa_traits.hh revision 2972
12SN/A/* 21458SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Gabe Black 302SN/A */ 312SN/A 321147SN/A#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ 331147SN/A#define __ARCH_ALPHA_ISA_TRAITS_HH__ 342SN/A 352037SN/Anamespace LittleEndianGuest {} 362037SN/A 372428SN/A#include "arch/alpha/types.hh" 382972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh" 391858SN/A#include "config/full_system.hh" 4056SN/A#include "sim/host.hh" 412SN/A 422107SN/Aclass StaticInstPtr; 432SN/A 442972Sgblack@eecs.umich.edu#if FULL_SYSTEM 452972Sgblack@eecs.umich.edu#include "arch/alpha/isa_fullsys_traits.hh" 462972Sgblack@eecs.umich.edu#endif 472238SN/A 482238SN/A 492972Sgblack@eecs.umich.edunamespace AlphaISA 502972Sgblack@eecs.umich.edu{ 512238SN/A 522972Sgblack@eecs.umich.edu using namespace LittleEndianGuest; 532238SN/A 542972Sgblack@eecs.umich.edu // These enumerate all the registers for dependence tracking. 552972Sgblack@eecs.umich.edu enum DependenceTags { 562972Sgblack@eecs.umich.edu // 0..31 are the integer regs 0..31 572972Sgblack@eecs.umich.edu // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 582972Sgblack@eecs.umich.edu FP_Base_DepTag = 40, 592972Sgblack@eecs.umich.edu Ctrl_Base_DepTag = 72, 602972Sgblack@eecs.umich.edu Fpcr_DepTag = 72, // floating point control register 612972Sgblack@eecs.umich.edu Uniq_DepTag = 73, 622972Sgblack@eecs.umich.edu Lock_Flag_DepTag = 74, 632972Sgblack@eecs.umich.edu Lock_Addr_DepTag = 75, 642972Sgblack@eecs.umich.edu IPR_Base_DepTag = 76 652972Sgblack@eecs.umich.edu }; 662238SN/A 672972Sgblack@eecs.umich.edu StaticInstPtr decodeInst(ExtMachInst); 682238SN/A 692972Sgblack@eecs.umich.edu const Addr PageShift = 13; 702972Sgblack@eecs.umich.edu const Addr PageBytes = ULL(1) << PageShift; 712972Sgblack@eecs.umich.edu const Addr PageMask = ~(PageBytes - 1); 722972Sgblack@eecs.umich.edu const Addr PageOffset = PageBytes - 1; 732972Sgblack@eecs.umich.edu 742972Sgblack@eecs.umich.edu 752972Sgblack@eecs.umich.edu#if FULL_SYSTEM 762972Sgblack@eecs.umich.edu 772972Sgblack@eecs.umich.edu //////////////////////////////////////////////////////////////////////// 782972Sgblack@eecs.umich.edu // 792972Sgblack@eecs.umich.edu // Translation stuff 802972Sgblack@eecs.umich.edu // 812972Sgblack@eecs.umich.edu 822972Sgblack@eecs.umich.edu const Addr PteShift = 3; 832972Sgblack@eecs.umich.edu const Addr NPtePageShift = PageShift - PteShift; 842972Sgblack@eecs.umich.edu const Addr NPtePage = ULL(1) << NPtePageShift; 852972Sgblack@eecs.umich.edu const Addr PteMask = NPtePage - 1; 862972Sgblack@eecs.umich.edu 872972Sgblack@eecs.umich.edu // User Virtual 882972Sgblack@eecs.umich.edu const Addr USegBase = ULL(0x0); 892972Sgblack@eecs.umich.edu const Addr USegEnd = ULL(0x000003ffffffffff); 902972Sgblack@eecs.umich.edu 912972Sgblack@eecs.umich.edu // Kernel Direct Mapped 922972Sgblack@eecs.umich.edu const Addr K0SegBase = ULL(0xfffffc0000000000); 932972Sgblack@eecs.umich.edu const Addr K0SegEnd = ULL(0xfffffdffffffffff); 942972Sgblack@eecs.umich.edu 952972Sgblack@eecs.umich.edu // Kernel Virtual 962972Sgblack@eecs.umich.edu const Addr K1SegBase = ULL(0xfffffe0000000000); 972972Sgblack@eecs.umich.edu const Addr K1SegEnd = ULL(0xffffffffffffffff); 982972Sgblack@eecs.umich.edu 992972Sgblack@eecs.umich.edu // For loading... XXX This maybe could be USegEnd?? --ali 1002972Sgblack@eecs.umich.edu const Addr LoadAddrMask = ULL(0xffffffffff); 1012972Sgblack@eecs.umich.edu 1022972Sgblack@eecs.umich.edu //////////////////////////////////////////////////////////////////////// 1032972Sgblack@eecs.umich.edu // 1042972Sgblack@eecs.umich.edu // Interrupt levels 1052972Sgblack@eecs.umich.edu // 1062972Sgblack@eecs.umich.edu enum InterruptLevels 1072972Sgblack@eecs.umich.edu { 1082972Sgblack@eecs.umich.edu INTLEVEL_SOFTWARE_MIN = 4, 1092972Sgblack@eecs.umich.edu INTLEVEL_SOFTWARE_MAX = 19, 1102972Sgblack@eecs.umich.edu 1112972Sgblack@eecs.umich.edu INTLEVEL_EXTERNAL_MIN = 20, 1122972Sgblack@eecs.umich.edu INTLEVEL_EXTERNAL_MAX = 34, 1132972Sgblack@eecs.umich.edu 1142972Sgblack@eecs.umich.edu INTLEVEL_IRQ0 = 20, 1152972Sgblack@eecs.umich.edu INTLEVEL_IRQ1 = 21, 1162972Sgblack@eecs.umich.edu INTINDEX_ETHERNET = 0, 1172972Sgblack@eecs.umich.edu INTINDEX_SCSI = 1, 1182972Sgblack@eecs.umich.edu INTLEVEL_IRQ2 = 22, 1192972Sgblack@eecs.umich.edu INTLEVEL_IRQ3 = 23, 1202972Sgblack@eecs.umich.edu 1212972Sgblack@eecs.umich.edu INTLEVEL_SERIAL = 33, 1222972Sgblack@eecs.umich.edu 1232972Sgblack@eecs.umich.edu NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 1242972Sgblack@eecs.umich.edu }; 1252972Sgblack@eecs.umich.edu 1262972Sgblack@eecs.umich.edu 1272972Sgblack@eecs.umich.edu // EV5 modes 1282972Sgblack@eecs.umich.edu enum mode_type 1292972Sgblack@eecs.umich.edu { 1302972Sgblack@eecs.umich.edu mode_kernel = 0, // kernel 1312972Sgblack@eecs.umich.edu mode_executive = 1, // executive (unused by unix) 1322972Sgblack@eecs.umich.edu mode_supervisor = 2, // supervisor (unused by unix) 1332972Sgblack@eecs.umich.edu mode_user = 3, // user mode 1342972Sgblack@eecs.umich.edu mode_number // number of modes 1352972Sgblack@eecs.umich.edu }; 1362238SN/A 1372238SN/A#endif 1382238SN/A 1392512SN/A#if FULL_SYSTEM 1402972Sgblack@eecs.umich.edu //////////////////////////////////////////////////////////////////////// 1412972Sgblack@eecs.umich.edu // 1422972Sgblack@eecs.umich.edu // Internal Processor Reigsters 1432972Sgblack@eecs.umich.edu // 1442972Sgblack@eecs.umich.edu enum md_ipr_names 1452972Sgblack@eecs.umich.edu { 1462972Sgblack@eecs.umich.edu IPR_ISR = 0x100, // interrupt summary register 1472972Sgblack@eecs.umich.edu IPR_ITB_TAG = 0x101, // ITLB tag register 1482972Sgblack@eecs.umich.edu IPR_ITB_PTE = 0x102, // ITLB page table entry register 1492972Sgblack@eecs.umich.edu IPR_ITB_ASN = 0x103, // ITLB address space register 1502972Sgblack@eecs.umich.edu IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register 1512972Sgblack@eecs.umich.edu IPR_ITB_IA = 0x105, // ITLB invalidate all register 1522972Sgblack@eecs.umich.edu IPR_ITB_IAP = 0x106, // ITLB invalidate all process register 1532972Sgblack@eecs.umich.edu IPR_ITB_IS = 0x107, // ITLB invalidate select register 1542972Sgblack@eecs.umich.edu IPR_SIRR = 0x108, // software interrupt request register 1552972Sgblack@eecs.umich.edu IPR_ASTRR = 0x109, // asynchronous system trap request register 1562972Sgblack@eecs.umich.edu IPR_ASTER = 0x10a, // asynchronous system trap enable register 1572972Sgblack@eecs.umich.edu IPR_EXC_ADDR = 0x10b, // exception address register 1582972Sgblack@eecs.umich.edu IPR_EXC_SUM = 0x10c, // exception summary register 1592972Sgblack@eecs.umich.edu IPR_EXC_MASK = 0x10d, // exception mask register 1602972Sgblack@eecs.umich.edu IPR_PAL_BASE = 0x10e, // PAL base address register 1612972Sgblack@eecs.umich.edu IPR_ICM = 0x10f, // instruction current mode 1622972Sgblack@eecs.umich.edu IPR_IPLR = 0x110, // interrupt priority level register 1632972Sgblack@eecs.umich.edu IPR_INTID = 0x111, // interrupt ID register 1642972Sgblack@eecs.umich.edu IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register 1652972Sgblack@eecs.umich.edu IPR_IVPTBR = 0x113, // virtual page table base register 1662972Sgblack@eecs.umich.edu IPR_HWINT_CLR = 0x115, // H/W interrupt clear register 1672972Sgblack@eecs.umich.edu IPR_SL_XMIT = 0x116, // serial line transmit register 1682972Sgblack@eecs.umich.edu IPR_SL_RCV = 0x117, // serial line receive register 1692972Sgblack@eecs.umich.edu IPR_ICSR = 0x118, // instruction control and status register 1702972Sgblack@eecs.umich.edu IPR_IC_FLUSH = 0x119, // instruction cache flush control 1712972Sgblack@eecs.umich.edu IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register 1722972Sgblack@eecs.umich.edu IPR_PMCTR = 0x11c, // performance counter register 1732972Sgblack@eecs.umich.edu 1742972Sgblack@eecs.umich.edu // PAL temporary registers... 1752972Sgblack@eecs.umich.edu // register meanings gleaned from osfpal.s source code 1762972Sgblack@eecs.umich.edu IPR_PALtemp0 = 0x140, // local scratch 1772972Sgblack@eecs.umich.edu IPR_PALtemp1 = 0x141, // local scratch 1782972Sgblack@eecs.umich.edu IPR_PALtemp2 = 0x142, // entUna 1792972Sgblack@eecs.umich.edu IPR_PALtemp3 = 0x143, // CPU specific impure area pointer 1802972Sgblack@eecs.umich.edu IPR_PALtemp4 = 0x144, // memory management temp 1812972Sgblack@eecs.umich.edu IPR_PALtemp5 = 0x145, // memory management temp 1822972Sgblack@eecs.umich.edu IPR_PALtemp6 = 0x146, // memory management temp 1832972Sgblack@eecs.umich.edu IPR_PALtemp7 = 0x147, // entIF 1842972Sgblack@eecs.umich.edu IPR_PALtemp8 = 0x148, // intmask 1852972Sgblack@eecs.umich.edu IPR_PALtemp9 = 0x149, // entSys 1862972Sgblack@eecs.umich.edu IPR_PALtemp10 = 0x14a, // ?? 1872972Sgblack@eecs.umich.edu IPR_PALtemp11 = 0x14b, // entInt 1882972Sgblack@eecs.umich.edu IPR_PALtemp12 = 0x14c, // entArith 1892972Sgblack@eecs.umich.edu IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL 1902972Sgblack@eecs.umich.edu IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL 1912972Sgblack@eecs.umich.edu IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL 1922972Sgblack@eecs.umich.edu IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> 1932972Sgblack@eecs.umich.edu IPR_PALtemp17 = 0x151, // sysval 1942972Sgblack@eecs.umich.edu IPR_PALtemp18 = 0x152, // usp 1952972Sgblack@eecs.umich.edu IPR_PALtemp19 = 0x153, // ksp 1962972Sgblack@eecs.umich.edu IPR_PALtemp20 = 0x154, // PTBR 1972972Sgblack@eecs.umich.edu IPR_PALtemp21 = 0x155, // entMM 1982972Sgblack@eecs.umich.edu IPR_PALtemp22 = 0x156, // kgp 1992972Sgblack@eecs.umich.edu IPR_PALtemp23 = 0x157, // PCBB 2002972Sgblack@eecs.umich.edu 2012972Sgblack@eecs.umich.edu IPR_DTB_ASN = 0x200, // DTLB address space number register 2022972Sgblack@eecs.umich.edu IPR_DTB_CM = 0x201, // DTLB current mode register 2032972Sgblack@eecs.umich.edu IPR_DTB_TAG = 0x202, // DTLB tag register 2042972Sgblack@eecs.umich.edu IPR_DTB_PTE = 0x203, // DTLB page table entry register 2052972Sgblack@eecs.umich.edu IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register 2062972Sgblack@eecs.umich.edu 2072972Sgblack@eecs.umich.edu IPR_MM_STAT = 0x205, // data MMU fault status register 2082972Sgblack@eecs.umich.edu IPR_VA = 0x206, // fault virtual address register 2092972Sgblack@eecs.umich.edu IPR_VA_FORM = 0x207, // formatted virtual address register 2102972Sgblack@eecs.umich.edu IPR_MVPTBR = 0x208, // MTU virtual page table base register 2112972Sgblack@eecs.umich.edu IPR_DTB_IAP = 0x209, // DTLB invalidate all process register 2122972Sgblack@eecs.umich.edu IPR_DTB_IA = 0x20a, // DTLB invalidate all register 2132972Sgblack@eecs.umich.edu IPR_DTB_IS = 0x20b, // DTLB invalidate single register 2142972Sgblack@eecs.umich.edu IPR_ALT_MODE = 0x20c, // alternate mode register 2152972Sgblack@eecs.umich.edu IPR_CC = 0x20d, // cycle counter register 2162972Sgblack@eecs.umich.edu IPR_CC_CTL = 0x20e, // cycle counter control register 2172972Sgblack@eecs.umich.edu IPR_MCSR = 0x20f, // MTU control register 2182972Sgblack@eecs.umich.edu 2192972Sgblack@eecs.umich.edu IPR_DC_FLUSH = 0x210, 2202972Sgblack@eecs.umich.edu IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register 2212972Sgblack@eecs.umich.edu IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register 2222972Sgblack@eecs.umich.edu IPR_DC_TEST_TAG = 0x214, // Dcache test tag register 2232972Sgblack@eecs.umich.edu IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register 2242972Sgblack@eecs.umich.edu IPR_DC_MODE = 0x216, // Dcache mode register 2252972Sgblack@eecs.umich.edu IPR_MAF_MODE = 0x217, // miss address file mode register 2262972Sgblack@eecs.umich.edu 2272972Sgblack@eecs.umich.edu NumInternalProcRegs // number of IPR registers 2282972Sgblack@eecs.umich.edu }; 2292972Sgblack@eecs.umich.edu#else 2302972Sgblack@eecs.umich.edu const int NumInternalProcRegs = 0; 2312512SN/A#endif 2322512SN/A 2332972Sgblack@eecs.umich.edu // Constants Related to the number of registers 2342512SN/A 2352972Sgblack@eecs.umich.edu const int NumIntArchRegs = 32; 2362972Sgblack@eecs.umich.edu const int NumPALShadowRegs = 8; 2372972Sgblack@eecs.umich.edu const int NumFloatArchRegs = 32; 2382972Sgblack@eecs.umich.edu // @todo: Figure out what this number really should be. 2392972Sgblack@eecs.umich.edu const int NumMiscArchRegs = 32; 2402SN/A 2412972Sgblack@eecs.umich.edu const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 2422972Sgblack@eecs.umich.edu const int NumFloatRegs = NumFloatArchRegs; 2432972Sgblack@eecs.umich.edu const int NumMiscRegs = NumMiscArchRegs; 2442449SN/A 2452972Sgblack@eecs.umich.edu const int TotalNumRegs = NumIntRegs + NumFloatRegs + 2462972Sgblack@eecs.umich.edu NumMiscRegs + NumInternalProcRegs; 2472227SN/A 2482972Sgblack@eecs.umich.edu const int TotalDataRegs = NumIntRegs + NumFloatRegs; 2492SN/A 2502972Sgblack@eecs.umich.edu // Static instruction parameters 2512972Sgblack@eecs.umich.edu const int MaxInstSrcRegs = 3; 2522972Sgblack@eecs.umich.edu const int MaxInstDestRegs = 2; 2532972Sgblack@eecs.umich.edu 2542972Sgblack@eecs.umich.edu // semantically meaningful register indices 2552972Sgblack@eecs.umich.edu const int ZeroReg = 31; // architecturally meaningful 2562972Sgblack@eecs.umich.edu // the rest of these depend on the ABI 2572972Sgblack@eecs.umich.edu const int StackPointerReg = 30; 2582972Sgblack@eecs.umich.edu const int GlobalPointerReg = 29; 2592972Sgblack@eecs.umich.edu const int ProcedureValueReg = 27; 2602972Sgblack@eecs.umich.edu const int ReturnAddressReg = 26; 2612972Sgblack@eecs.umich.edu const int ReturnValueReg = 0; 2622972Sgblack@eecs.umich.edu const int FramePointerReg = 15; 2632972Sgblack@eecs.umich.edu const int ArgumentReg0 = 16; 2642972Sgblack@eecs.umich.edu const int ArgumentReg1 = 17; 2652972Sgblack@eecs.umich.edu const int ArgumentReg2 = 18; 2662972Sgblack@eecs.umich.edu const int ArgumentReg3 = 19; 2672972Sgblack@eecs.umich.edu const int ArgumentReg4 = 20; 2682972Sgblack@eecs.umich.edu const int ArgumentReg5 = 21; 2692972Sgblack@eecs.umich.edu const int SyscallNumReg = ReturnValueReg; 2702972Sgblack@eecs.umich.edu const int SyscallPseudoReturnReg = ArgumentReg4; 2712972Sgblack@eecs.umich.edu const int SyscallSuccessReg = 19; 2722972Sgblack@eecs.umich.edu 2732972Sgblack@eecs.umich.edu const int LogVMPageSize = 13; // 8K bytes 2742972Sgblack@eecs.umich.edu const int VMPageSize = (1 << LogVMPageSize); 2752972Sgblack@eecs.umich.edu 2762972Sgblack@eecs.umich.edu const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 2772972Sgblack@eecs.umich.edu 2782972Sgblack@eecs.umich.edu const int MachineBytes = 8; 2792972Sgblack@eecs.umich.edu const int WordBytes = 4; 2802972Sgblack@eecs.umich.edu const int HalfwordBytes = 2; 2812972Sgblack@eecs.umich.edu const int ByteBytes = 1; 2822972Sgblack@eecs.umich.edu 2832972Sgblack@eecs.umich.edu // return a no-op instruction... used for instruction fetch faults 2842972Sgblack@eecs.umich.edu // Alpha UNOP (ldq_u r31,0(r0)) 2852972Sgblack@eecs.umich.edu const ExtMachInst NoopMachInst = 0x2ffe0000; 2862972Sgblack@eecs.umich.edu 2872972Sgblack@eecs.umich.edu // redirected register map, really only used for the full system case. 2882972Sgblack@eecs.umich.edu extern const int reg_redir[NumIntRegs]; 2892972Sgblack@eecs.umich.edu 2902264SN/A}; 2912107SN/A 2921147SN/A#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ 293