isa_traits.hh revision 2238 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
30#define __ARCH_ALPHA_ISA_TRAITS_HH__
31
32namespace LittleEndianGuest {}
33using namespace LittleEndianGuest;
34
35//#include "arch/alpha/faults.hh"
36#include "base/misc.hh"
37#include "config/full_system.hh"
38#include "sim/host.hh"
39#include "sim/faults.hh"
40
41class ExecContext;
42class FastCPU;
43class FullCPU;
44class Checkpoint;
45
46#define TARGET_ALPHA
47
48class StaticInst;
49class StaticInstPtr;
50
51namespace EV5 {
52int DTB_ASN_ASN(uint64_t reg);
53int ITB_ASN_ASN(uint64_t reg);
54}
55
56#if !FULL_SYSTEM
57class SyscallReturn {
58        public:
59           template <class T>
60           SyscallReturn(T v, bool s)
61           {
62               retval = (uint64_t)v;
63               success = s;
64           }
65
66           template <class T>
67           SyscallReturn(T v)
68           {
69               success = (v >= 0);
70               retval = (uint64_t)v;
71           }
72
73           ~SyscallReturn() {}
74
75           SyscallReturn& operator=(const SyscallReturn& s) {
76               retval = s.retval;
77               success = s.success;
78               return *this;
79           }
80
81           bool successful() { return success; }
82           uint64_t value() { return retval; }
83
84
85       private:
86           uint64_t retval;
87           bool success;
88};
89
90#endif
91
92
93
94namespace AlphaISA
95{
96
97    typedef uint32_t MachInst;
98    typedef uint64_t ExtMachInst;
99    typedef uint8_t  RegIndex;
100
101    enum {
102        MemoryEnd = 0xffffffffffffffffULL,
103
104        NumIntArchRegs = 32,
105        NumPALShadowRegs = 8,
106        NumFloatArchRegs = 32,
107        // @todo: Figure out what this number really should be.
108        NumMiscArchRegs = 32,
109
110        MaxRegsOfAnyType = 32,
111        // Static instruction parameters
112        MaxInstSrcRegs = 3,
113        MaxInstDestRegs = 2,
114
115        // semantically meaningful register indices
116        ZeroReg = 31,	// architecturally meaningful
117        // the rest of these depend on the ABI
118        StackPointerReg = 30,
119        GlobalPointerReg = 29,
120        ProcedureValueReg = 27,
121        ReturnAddressReg = 26,
122        ReturnValueReg = 0,
123        SyscallNumReg = 0,
124        FramePointerReg = 15,
125        ArgumentReg0 = 16,
126        ArgumentReg1 = 17,
127        ArgumentReg2 = 18,
128        ArgumentReg3 = 19,
129        ArgumentReg4 = 20,
130        ArgumentReg5 = 21,
131        SyscallSuccessReg = 19,
132        // Some OS use a second register (o1) to return a second value
133        // for some syscalls
134        SyscallPseudoReturnReg = ArgumentReg4,
135
136        LogVMPageSize = 13,	// 8K bytes
137        VMPageSize = (1 << LogVMPageSize),
138
139        BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
140
141        WordBytes = 4,
142        HalfwordBytes = 2,
143        ByteBytes = 1,
144        DepNA = 0,
145    };
146
147    enum {
148        NumIntRegs = NumIntArchRegs + NumPALShadowRegs,
149        NumFloatRegs = NumFloatArchRegs,
150        NumMiscRegs = NumMiscArchRegs
151    };
152
153    // These enumerate all the registers for dependence tracking.
154    enum DependenceTags {
155        // 0..31 are the integer regs 0..31
156        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
157        FP_Base_DepTag = 40,
158        Ctrl_Base_DepTag = 72,
159        Fpcr_DepTag = 72,		// floating point control register
160        Uniq_DepTag = 73,
161        Lock_Flag_DepTag = 74,
162        Lock_Addr_DepTag = 75,
163        IPR_Base_DepTag = 76
164    };
165
166    typedef uint64_t IntReg;
167    typedef IntReg IntRegFile[NumIntRegs];
168
169    // floating point register file entry type
170    typedef union {
171        uint64_t q;
172        double d;
173    } FloatReg;
174
175    typedef union {
176        uint64_t q[NumFloatRegs];	// integer qword view
177        double d[NumFloatRegs];		// double-precision floating point view
178    } FloatRegFile;
179
180extern const Addr PageShift;
181extern const Addr PageBytes;
182extern const Addr PageMask;
183extern const Addr PageOffset;
184
185// redirected register map, really only used for the full system case.
186extern const int reg_redir[NumIntRegs];
187
188#if FULL_SYSTEM
189
190    typedef uint64_t InternalProcReg;
191
192#include "arch/alpha/isa_fullsys_traits.hh"
193
194#else
195    enum {
196        NumInternalProcRegs = 0
197    };
198#endif
199
200    // control register file contents
201    typedef uint64_t MiscReg;
202    class MiscRegFile {
203      protected:
204        uint64_t	fpcr;		// floating point condition codes
205        uint64_t	uniq;		// process-unique register
206        bool		lock_flag;	// lock flag for LL/SC
207        Addr		lock_addr;	// lock address for LL/SC
208
209      public:
210        MiscReg readReg(int misc_reg);
211
212        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
213
214        Fault setReg(int misc_reg, const MiscReg &val);
215
216        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
217                               ExecContext *xc);
218
219#if FULL_SYSTEM
220        void clearIprs();
221
222      protected:
223        InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
224
225      private:
226        MiscReg readIpr(int idx, Fault &fault, ExecContext *xc);
227
228        Fault setIpr(int idx, uint64_t val, ExecContext *xc);
229#endif
230        friend class RegFile;
231    };
232
233    enum {
234        TotalNumRegs =
235        NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
236    };
237
238    enum {
239        TotalDataRegs = NumIntRegs + NumFloatRegs
240    };
241
242    typedef union {
243        IntReg  intreg;
244        FloatReg   fpreg;
245        MiscReg ctrlreg;
246    } AnyReg;
247
248    struct RegFile {
249        IntRegFile intRegFile;		// (signed) integer register file
250        FloatRegFile floatRegFile;	// floating point register file
251        MiscRegFile miscRegs;		// control register file
252        Addr pc;			// program counter
253        Addr npc;			// next-cycle program counter
254#if FULL_SYSTEM
255        int intrflag;			// interrupt flag
256        inline int instAsid()
257        { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); }
258        inline int dataAsid()
259        { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); }
260#endif // FULL_SYSTEM
261
262        void serialize(std::ostream &os);
263        void unserialize(Checkpoint *cp, const std::string &section);
264    };
265
266    static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc);
267
268    StaticInstPtr decodeInst(ExtMachInst);
269
270    // return a no-op instruction... used for instruction fetch faults
271    extern const ExtMachInst NoopMachInst;
272
273    enum annotes {
274        ANNOTE_NONE = 0,
275        // An impossible number for instruction annotations
276        ITOUCH_ANNOTE = 0xffffffff,
277    };
278
279    static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
280        panic("register classification not implemented");
281        return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
282    }
283
284    static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
285        panic("register classification not implemented");
286        return (reg >= 9 && reg <= 15);
287    }
288
289    static inline bool isCallerSaveFloatRegister(unsigned int reg) {
290        panic("register classification not implemented");
291        return false;
292    }
293
294    static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
295        panic("register classification not implemented");
296        return false;
297    }
298
299    static inline Addr alignAddress(const Addr &addr,
300                                         unsigned int nbytes) {
301        return (addr & ~(nbytes - 1));
302    }
303
304    // Instruction address compression hooks
305    static inline Addr realPCToFetchPC(const Addr &addr) {
306        return addr;
307    }
308
309    static inline Addr fetchPCToRealPC(const Addr &addr) {
310        return addr;
311    }
312
313    // the size of "fetched" instructions (not necessarily the size
314    // of real instructions for PISA)
315    static inline size_t fetchInstSize() {
316        return sizeof(MachInst);
317    }
318
319    static inline MachInst makeRegisterCopy(int dest, int src) {
320        panic("makeRegisterCopy not implemented");
321        return 0;
322    }
323
324    // Machine operations
325
326    void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
327                               int regnum);
328
329    void restoreMachineReg(RegFile &regs, const AnyReg &reg,
330                                  int regnum);
331
332#if 0
333    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
334                                     const RegFile &regs);
335
336    static void unserializeSpecialRegs(const IniFile *db,
337                                       const std::string &category,
338                                       ConfigNode *node,
339                                       RegFile &regs);
340#endif
341
342    /**
343     * Function to insure ISA semantics about 0 registers.
344     * @param xc The execution context.
345     */
346    template <class XC>
347    void zeroRegisters(XC *xc);
348
349    static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
350    {
351        // check for error condition.  Alpha syscall convention is to
352        // indicate success/failure in reg a3 (r19) and put the
353        // return value itself in the standard return value reg (v0).
354        if (return_value.successful()) {
355            // no error
356            regs->intRegFile[SyscallSuccessReg] = 0;
357            regs->intRegFile[ReturnValueReg] = return_value.value();
358        } else {
359            // got an error, return details
360            regs->intRegFile[SyscallSuccessReg] = (IntReg) -1;
361            regs->intRegFile[ReturnValueReg] = -return_value.value();
362        }
363    }
364
365//typedef AlphaISA TheISA;
366
367//typedef TheISA::MachInst MachInst;
368//typedef TheISA::Addr Addr;
369//typedef TheISA::RegIndex RegIndex;
370//typedef TheISA::IntReg IntReg;
371//typedef TheISA::IntRegFile IntRegFile;
372//typedef TheISA::FloatReg FloatReg;
373//typedef TheISA::FloatRegFile FloatRegFile;
374//typedef TheISA::MiscReg MiscReg;
375//typedef TheISA::MiscRegFile MiscRegFile;
376//typedef TheISA::AnyReg AnyReg;
377//typedef TheISA::RegFile RegFile;
378
379//const int NumIntRegs   = TheISA::NumIntRegs;
380//const int NumFloatRegs = TheISA::NumFloatRegs;
381//const int NumMiscRegs  = TheISA::NumMiscRegs;
382//const int TotalNumRegs = TheISA::TotalNumRegs;
383//const int VMPageSize   = TheISA::VMPageSize;
384//const int LogVMPageSize   = TheISA::LogVMPageSize;
385//const int ZeroReg = TheISA::ZeroReg;
386//const int StackPointerReg = TheISA::StackPointerReg;
387//const int GlobalPointerReg = TheISA::GlobalPointerReg;
388//const int ReturnAddressReg = TheISA::ReturnAddressReg;
389//const int ReturnValueReg = TheISA::ReturnValueReg;
390//const int ArgumentReg0 = TheISA::ArgumentReg0;
391//const int ArgumentReg1 = TheISA::ArgumentReg1;
392//const int ArgumentReg2 = TheISA::ArgumentReg2;
393//const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
394const Addr MaxAddr = (Addr)-1;
395};
396
397static inline AlphaISA::ExtMachInst
398AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) {
399#if FULL_SYSTEM
400    AlphaISA::ExtMachInst ext_inst = inst;
401    if (pc && 0x1)
402        return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32);
403    else
404        return ext_inst;
405#else
406    return AlphaISA::ExtMachInst(inst);
407#endif
408}
409
410#if FULL_SYSTEM
411//typedef TheISA::InternalProcReg InternalProcReg;
412//const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
413//const int NumInterruptLevels = TheISA::NumInterruptLevels;
414
415#include "arch/alpha/ev5.hh"
416#endif
417
418#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
419