opcdec.isa revision 12616
18528SN/A// -*- mode:c++ -*-
28528SN/A
38528SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan
48835SAli.Saidi@ARM.com// All rights reserved.
58528SN/A//
68528SN/A// Redistribution and use in source and binary forms, with or without
78528SN/A// modification, are permitted provided that the following conditions are
88528SN/A// met: redistributions of source code must retain the above copyright
98528SN/A// notice, this list of conditions and the following disclaimer;
108528SN/A// redistributions in binary form must reproduce the above copyright
118891SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer in the
128891SAli.Saidi@ARM.com// documentation and/or other materials provided with the distribution;
138983Snate@binkert.org// neither the name of the copyright holders nor the names of its
148528SN/A// contributors may be used to endorse or promote products derived from
158528SN/A// this software without specific prior written permission.
168528SN/A//
178528SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
188983Snate@binkert.org// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
198528SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
208528SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
218528SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
228891SAli.Saidi@ARM.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
238528SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
248721SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
258528SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
268528SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
278528SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
288528SN/A//
298528SN/A// Authors: Kevin Lim
308528SN/A
318528SN/A////////////////////////////////////////////////////////////////////
328528SN/A//
338528SN/A// OPCDEC fault instructions
348891SAli.Saidi@ARM.com//
358528SN/A
368528SN/Aoutput header {{
378528SN/A    /**
388528SN/A     * Static instruction class for instructions that cause an OPCDEC fault
398528SN/A     * when executed.  This is currently only for PAL mode instructions
408891SAli.Saidi@ARM.com     * executed in non-PAL mode.
418721SN/A     */
428721SN/A    class OpcdecFault : public AlphaStaticInst
438528SN/A    {
448891SAli.Saidi@ARM.com      public:
458891SAli.Saidi@ARM.com        /// Constructor
468528SN/A        OpcdecFault(ExtMachInst _machInst)
478528SN/A            : AlphaStaticInst("opcdec fault", _machInst, No_OpClass)
488528SN/A        {
498528SN/A        }
508528SN/A
518528SN/A        Fault execute(ExecContext *, Trace::InstRecord *) const override;
528528SN/A
538528SN/A        std::string generateDisassembly(
548528SN/A                Addr pc, const SymbolTable *symtab) const override;
558528SN/A    };
568528SN/A}};
578528SN/A
588528SN/Aoutput decoder {{
598528SN/A    std::string
608528SN/A    OpcdecFault::generateDisassembly(Addr pc, const SymbolTable *symtab) const
618528SN/A    {
628528SN/A        return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
638528SN/A                        " OPCDEC fault", machInst, OPCODE);
648983Snate@binkert.org    }
658528SN/A}};
668528SN/A
678528SN/Aoutput exec {{
688528SN/A    Fault
698528SN/A    OpcdecFault::execute(ExecContext *xc, Trace::InstRecord *traceData) const
708528SN/A    {
718528SN/A        return std::make_shared<UnimplementedOpcodeFault>();
728528SN/A    }
738528SN/A}};
748528SN/A
758528SN/Adef format OpcdecFault() {{
768528SN/A    decode_block = 'return new OpcdecFault(machInst);\n'
778528SN/A}};
788528SN/A
798528SN/A