opcdec.isa revision 2665
12227SN/A// -*- mode:c++ -*- 22227SN/A 32227SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 42227SN/A// All rights reserved. 52227SN/A// 62227SN/A// Redistribution and use in source and binary forms, with or without 72227SN/A// modification, are permitted provided that the following conditions are 82227SN/A// met: redistributions of source code must retain the above copyright 92227SN/A// notice, this list of conditions and the following disclaimer; 102227SN/A// redistributions in binary form must reproduce the above copyright 112227SN/A// notice, this list of conditions and the following disclaimer in the 122227SN/A// documentation and/or other materials provided with the distribution; 132227SN/A// neither the name of the copyright holders nor the names of its 142227SN/A// contributors may be used to endorse or promote products derived from 152227SN/A// this software without specific prior written permission. 162227SN/A// 172227SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182227SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192227SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202227SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212227SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222227SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232227SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242227SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252227SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262227SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272227SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292665Ssaidi@eecs.umich.edu// Authors: Kevin Lim 302227SN/A 312649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 322649Ssaidi@eecs.umich.edu// 332649Ssaidi@eecs.umich.edu// OPCDEC fault instructions 342649Ssaidi@eecs.umich.edu// 352649Ssaidi@eecs.umich.edu 362227SN/Aoutput header {{ 372227SN/A /** 382227SN/A * Static instruction class for instructions that cause an OPCDEC fault 392227SN/A * when executed. This is currently only for PAL mode instructions 402227SN/A * executed in non-PAL mode. 412227SN/A */ 422227SN/A class OpcdecFault : public AlphaStaticInst 432227SN/A { 442227SN/A public: 452227SN/A /// Constructor 462227SN/A OpcdecFault(ExtMachInst _machInst) 472227SN/A : AlphaStaticInst("opcdec fault", _machInst, No_OpClass) 482227SN/A { 492227SN/A } 502227SN/A 512227SN/A %(BasicExecDeclare)s 522227SN/A 532227SN/A std::string 542227SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 552227SN/A }; 562227SN/A}}; 572227SN/A 582227SN/Aoutput decoder {{ 592227SN/A std::string 602227SN/A OpcdecFault::generateDisassembly(Addr pc, const SymbolTable *symtab) const 612227SN/A { 622227SN/A return csprintf("%-10s (inst 0x%x, opcode 0x%x)", 632227SN/A " OPCDEC fault", machInst, OPCODE); 642227SN/A } 652227SN/A}}; 662227SN/A 672227SN/Aoutput exec {{ 682227SN/A Fault 692227SN/A OpcdecFault::execute(%(CPU_exec_context)s *xc, 702227SN/A Trace::InstRecord *traceData) const 712227SN/A { 722227SN/A return new UnimplementedOpcodeFault; 732227SN/A } 742227SN/A}}; 752227SN/A 762227SN/Adef format OpcdecFault() {{ 772227SN/A decode_block = 'return new OpcdecFault(machInst);\n' 782227SN/A}}; 792227SN/A 80