xref: /gem5/src/arch/alpha/isa/opcdec.isa

// -*- mode:c++ -*-

// Copyright (c) 2003-2005 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

////////////////////////////////////////////////////////////////////
//
// OPCDEC fault instructions
//

output header {{
    /**
     * Static instruction class for instructions that cause an OPCDEC fault
     * when executed.  This is currently only for PAL mode instructions
     * executed in non-PAL mode.
     */
    class OpcdecFault : public AlphaStaticInst
    {
      public:
        /// Constructor
        OpcdecFault(ExtMachInst _machInst)
            : AlphaStaticInst("opcdec fault", _machInst, No_OpClass)
        {
        }

        %(BasicExecDeclare)s

        std::string
        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
    };
}};

output decoder {{
    std::string
    OpcdecFault::generateDisassembly(Addr pc, const SymbolTable *symtab) const
    {
        return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
                        " OPCDEC fault", machInst, OPCODE);
    }
}};

output exec {{
    Fault
    OpcdecFault::execute(%(CPU_exec_context)s *xc,
                     Trace::InstRecord *traceData) const
    {
        return new UnimplementedOpcodeFault;
    }
}};

def format OpcdecFault() {{
    decode_block = 'return new OpcdecFault(machInst);\n'
}};