mem.isa revision 10184:bbfa3152bdea
12SN/A// -*- mode:c++ -*- 21762SN/A 32SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 42SN/A// All rights reserved. 52SN/A// 62SN/A// Redistribution and use in source and binary forms, with or without 72SN/A// modification, are permitted provided that the following conditions are 82SN/A// met: redistributions of source code must retain the above copyright 92SN/A// notice, this list of conditions and the following disclaimer; 102SN/A// redistributions in binary form must reproduce the above copyright 112SN/A// notice, this list of conditions and the following disclaimer in the 122SN/A// documentation and/or other materials provided with the distribution; 132SN/A// neither the name of the copyright holders nor the names of its 142SN/A// contributors may be used to endorse or promote products derived from 152SN/A// this software without specific prior written permission. 162SN/A// 172SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292SN/A// Authors: Steve Reinhardt 302SN/A// Kevin Lim 312439SN/A 322984Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 33146SN/A// 345953Ssaidi@eecs.umich.edu// Memory-format instructions: LoadAddress, Load, Store 35146SN/A// 36146SN/A 37146SN/Aoutput header {{ 38146SN/A /** 39146SN/A * Base class for general Alpha memory-format instructions. 401717SN/A */ 41146SN/A class Memory : public AlphaStaticInst 421717SN/A { 43146SN/A protected: 441977SN/A 452623SN/A /// Memory request flags. See mem_req_base.hh. 462683Sktlim@umich.edu Request::Flags memAccessFlags; 471717SN/A 48146SN/A /// Constructor 492683Sktlim@umich.edu Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 503348Sbinkertn@umich.edu : AlphaStaticInst(mnem, _machInst, __opClass) 516105Ssteve.reinhardt@amd.com { 522036SN/A } 53146SN/A 5456SN/A std::string 5556SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 5656SN/A }; 57695SN/A 582901Ssaidi@eecs.umich.edu /** 592SN/A * Base class for memory-format instructions using a 32-bit 601858SN/A * displacement (i.e. most of them). 613565Sgblack@eecs.umich.edu */ 623565Sgblack@eecs.umich.edu class MemoryDisp32 : public Memory 632171SN/A { 642170SN/A protected: 653562Sgblack@eecs.umich.edu /// Displacement for EA calculation (signed). 66146SN/A int32_t disp; 672462SN/A 68146SN/A /// Constructor. 692SN/A MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 705529Snate@binkert.org : Memory(mnem, _machInst, __opClass), 715529Snate@binkert.org disp(MEMDISP) 722SN/A { 732449SN/A } 741355SN/A }; 755529Snate@binkert.org 764495Sacolyte@umich.edu 77224SN/A /** 781858SN/A * Base class for a few miscellaneous memory-format insts 792683Sktlim@umich.edu * that don't interpret the disp field: wh64, fetch, fetch_m, ecb. 802420SN/A * None of these instructions has a destination register either. 815529Snate@binkert.org */ 824997Sgblack@eecs.umich.edu class MemoryNoDisp : public Memory 832420SN/A { 842SN/A protected: 856029Ssteve.reinhardt@amd.com /// Constructor 862672Sktlim@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 872683Sktlim@umich.edu : Memory(mnem, _machInst, __opClass) 882SN/A { 892SN/A } 90334SN/A 91140SN/A std::string 92334SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 932SN/A }; 942SN/A}}; 952SN/A 962680Sktlim@umich.edu 974377Sgblack@eecs.umich.eduoutput decoder {{ 985169Ssaidi@eecs.umich.edu std::string 994377Sgblack@eecs.umich.edu Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1004377Sgblack@eecs.umich.edu { 1012SN/A return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 1022SN/A flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB); 1032623SN/A } 1042SN/A 1052SN/A std::string 1062SN/A MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 107180SN/A { 1082623SN/A return csprintf("%-10s (r%d)", mnemonic, RB); 109393SN/A } 110393SN/A}}; 111393SN/A 112393SN/Adef format LoadAddress(code) {{ 113384SN/A iop = InstObjParams(name, Name, 'MemoryDisp32', code) 114384SN/A header_output = BasicDeclare.subst(iop) 115393SN/A decoder_output = BasicConstructor.subst(iop) 1162623SN/A decode_block = BasicDecode.subst(iop) 117393SN/A exec_output = BasicExecute.subst(iop) 118393SN/A}}; 119393SN/A 120393SN/A 121384SN/Adef template LoadStoreDeclare {{ 122189SN/A /** 123189SN/A * Static instruction class for "%(mnemonic)s". 1242623SN/A */ 1252SN/A class %(class_name)s : public %(base_class)s 126729SN/A { 127334SN/A public: 1282SN/A 1292SN/A /// Constructor. 1302SN/A %(class_name)s(ExtMachInst machInst); 1312SN/A 1322SN/A %(BasicExecDeclare)s 1332SN/A 1342SN/A %(EACompDeclare)s 1352SN/A 1362SN/A %(InitiateAccDeclare)s 1372SN/A 1382SN/A %(CompleteAccDeclare)s 1392SN/A }; 1401001SN/A}}; 1411001SN/A 1421001SN/A 1431001SN/Adef template EACompDeclare {{ 1441001SN/A Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1452SN/A}}; 1462SN/A 1472SN/Adef template InitiateAccDeclare {{ 1482SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1492SN/A}}; 1502SN/A 1512SN/A 1522SN/Adef template CompleteAccDeclare {{ 1532SN/A Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, 1542SN/A Trace::InstRecord *) const; 1552SN/A}}; 1562SN/A 1572SN/Adef template LoadStoreConstructor {{ 1582SN/A %(class_name)s::%(class_name)s(ExtMachInst machInst) 1592SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1602SN/A { 1612SN/A %(constructor)s; 1622390SN/A } 1632390SN/A}}; 1642390SN/A 1652390SN/Adef template EACompExecute {{ 1662390SN/A Fault %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 1672390SN/A Trace::InstRecord *traceData) const 1682390SN/A { 1692390SN/A Addr EA; 1702390SN/A Fault fault = NoFault; 1712390SN/A 1722390SN/A %(fp_enable_check)s; 1732390SN/A %(op_decl)s; 174385SN/A %(op_rd)s; 1752SN/A %(ea_code)s; 1762SN/A 1772SN/A if (fault == NoFault) { 1782623SN/A %(op_wb)s; 179334SN/A xc->setEA(EA); 1802361SN/A } 1815496Ssaidi@eecs.umich.edu 182334SN/A return fault; 183334SN/A } 184334SN/A}}; 1852623SN/A 1862SN/A 1875496Ssaidi@eecs.umich.edudef template LoadExecute {{ 188921SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1892915Sktlim@umich.edu Trace::InstRecord *traceData) const 1902915Sktlim@umich.edu { 1912683Sktlim@umich.edu Addr EA; 1922SN/A Fault fault = NoFault; 1932SN/A 1942SN/A %(fp_enable_check)s; 1952623SN/A %(op_decl)s; 1962SN/A %(op_rd)s; 1975496Ssaidi@eecs.umich.edu %(ea_code)s; 198921SN/A 1992915Sktlim@umich.edu if (fault == NoFault) { 2002915Sktlim@umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 2012SN/A %(memacc_code)s; 2022SN/A } 2032SN/A 2042SN/A if (fault == NoFault) { 2052SN/A %(op_wb)s; 2062SN/A } 2072SN/A 208595SN/A return fault; 2092623SN/A } 210595SN/A}}; 2112390SN/A 2121080SN/A 2131080SN/Adef template LoadInitiateAcc {{ 2141080SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2151080SN/A Trace::InstRecord *traceData) const 2161080SN/A { 2171080SN/A Addr EA; 2181080SN/A Fault fault = NoFault; 2191121SN/A 2202107SN/A %(fp_enable_check)s; 2211089SN/A %(op_src_decl)s; 2221089SN/A %(op_rd)s; 2231080SN/A %(ea_code)s; 2241080SN/A 2251080SN/A if (fault == NoFault) { 2261080SN/A fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags); 227595SN/A } 2282623SN/A 2292683Sktlim@umich.edu return fault; 230595SN/A } 2312090SN/A}}; 2322683Sktlim@umich.edu 2332683Sktlim@umich.edu 234595SN/Adef template LoadCompleteAcc {{ 2352205SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, 2362205SN/A %(CPU_exec_context)s *xc, 2372683Sktlim@umich.edu Trace::InstRecord *traceData) const 2382683Sktlim@umich.edu { 239595SN/A Fault fault = NoFault; 240595SN/A 2412390SN/A %(fp_enable_check)s; 2422423SN/A %(op_decl)s; 2432390SN/A 244595SN/A getMem(pkt, Mem, traceData); 245595SN/A 246595SN/A if (fault == NoFault) { 2472623SN/A %(memacc_code)s; 248595SN/A } 2492390SN/A 2501080SN/A if (fault == NoFault) { 251595SN/A %(op_wb)s; 2521080SN/A } 2531080SN/A 254595SN/A return fault; 2552683Sktlim@umich.edu } 2561080SN/A}}; 2571080SN/A 2581080SN/A 2591121SN/Adef template StoreExecute {{ 2602107SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2611089SN/A Trace::InstRecord *traceData) const 2621080SN/A { 2631089SN/A Addr EA; 2641080SN/A Fault fault = NoFault; 2651080SN/A 2661080SN/A %(fp_enable_check)s; 267595SN/A %(op_decl)s; 2682683Sktlim@umich.edu %(op_rd)s; 2691080SN/A %(ea_code)s; 2702090SN/A 2711080SN/A if (fault == NoFault) { 272595SN/A %(memacc_code)s; 2732683Sktlim@umich.edu } 2742683Sktlim@umich.edu 275595SN/A if (fault == NoFault) { 2762683Sktlim@umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, 2771098SN/A memAccessFlags, NULL); 2781098SN/A } 2791098SN/A 2802683Sktlim@umich.edu if (fault == NoFault) { 2811098SN/A %(postacc_code)s; 2821098SN/A } 2831098SN/A 2846105Ssteve.reinhardt@amd.com if (fault == NoFault) { 2851098SN/A %(op_wb)s; 2861098SN/A } 287595SN/A 2882205SN/A return fault; 2892205SN/A } 2902205SN/A}}; 291595SN/A 2922390SN/Adef template StoreCondExecute {{ 2932420SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2942423SN/A Trace::InstRecord *traceData) const 2952390SN/A { 296595SN/A Addr EA; 297595SN/A Fault fault = NoFault; 2981858SN/A uint64_t write_result = 0; 2992SN/A 3002623SN/A %(fp_enable_check)s; 3012SN/A %(op_decl)s; 3022680Sktlim@umich.edu %(op_rd)s; 3032SN/A %(ea_code)s; 3042SN/A 3052SN/A if (fault == NoFault) { 3061858SN/A %(memacc_code)s; 3072SN/A } 3085807Snate@binkert.org 3092SN/A if (fault == NoFault) { 3105807Snate@binkert.org fault = writeMemAtomic(xc, traceData, Mem, EA, 3115807Snate@binkert.org memAccessFlags, &write_result); 3122SN/A } 3135807Snate@binkert.org 3145807Snate@binkert.org if (fault == NoFault) { 3152SN/A %(postacc_code)s; 3162SN/A } 3172SN/A 3182SN/A if (fault == NoFault) { 3192623SN/A %(op_wb)s; 3202SN/A } 3211858SN/A 3225704Snate@binkert.org return fault; 3235647Sgblack@eecs.umich.edu } 3242SN/A}}; 3253520Sgblack@eecs.umich.edu 3265835Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 3275647Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3283520Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3292SN/A { 3302SN/A Addr EA; 3312SN/A Fault fault = NoFault; 3322623SN/A 3332SN/A %(fp_enable_check)s; 3342623SN/A %(op_decl)s; 3355894Sgblack@eecs.umich.edu %(op_rd)s; 3362662Sstever@eecs.umich.edu %(ea_code)s; 3372623SN/A 3384514Ssaidi@eecs.umich.edu if (fault == NoFault) { 3394495Sacolyte@umich.edu %(memacc_code)s; 3402623SN/A } 3413093Sksewell@umich.edu 3424495Sacolyte@umich.edu if (fault == NoFault) { 3433093Sksewell@umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, 3443093Sksewell@umich.edu memAccessFlags, NULL); 3454564Sgblack@eecs.umich.edu } 3462741Sksewell@umich.edu 3472741Sksewell@umich.edu return fault; 3482623SN/A } 3494564Sgblack@eecs.umich.edu}}; 3506105Ssteve.reinhardt@amd.com 3512623SN/A 3522623SN/Adef template StoreCompleteAcc {{ 3532623SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, 3542623SN/A %(CPU_exec_context)s *xc, 3552623SN/A Trace::InstRecord *traceData) const 3562623SN/A { 3572SN/A return NoFault; 3582683Sktlim@umich.edu } 3592427SN/A}}; 3602683Sktlim@umich.edu 3612427SN/A 3622SN/Adef template StoreCondCompleteAcc {{ 3632623SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, 3642623SN/A %(CPU_exec_context)s *xc, 3652SN/A Trace::InstRecord *traceData) const 3662623SN/A { 3672623SN/A Fault fault = NoFault; 3684377Sgblack@eecs.umich.edu 3695665Sgblack@eecs.umich.edu %(fp_enable_check)s; 3704377Sgblack@eecs.umich.edu %(op_dest_decl)s; 3715665Sgblack@eecs.umich.edu 3725665Sgblack@eecs.umich.edu uint64_t write_result = pkt->req->getExtraData(); 3735665Sgblack@eecs.umich.edu 3745665Sgblack@eecs.umich.edu if (fault == NoFault) { 3755665Sgblack@eecs.umich.edu %(postacc_code)s; 3764181Sgblack@eecs.umich.edu } 3774181Sgblack@eecs.umich.edu 3784181Sgblack@eecs.umich.edu if (fault == NoFault) { 3794182Sgblack@eecs.umich.edu %(op_wb)s; 3804182Sgblack@eecs.umich.edu } 3814182Sgblack@eecs.umich.edu 3824593Sgblack@eecs.umich.edu return fault; 3834593Sgblack@eecs.umich.edu } 3844593Sgblack@eecs.umich.edu}}; 3854593Sgblack@eecs.umich.edu 3864593Sgblack@eecs.umich.edu 3874377Sgblack@eecs.umich.edudef template MiscExecute {{ 3884377Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3894377Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3904377Sgblack@eecs.umich.edu { 3914377Sgblack@eecs.umich.edu Addr EA M5_VAR_USED; 3924377Sgblack@eecs.umich.edu Fault fault = NoFault; 3934377Sgblack@eecs.umich.edu 3944377Sgblack@eecs.umich.edu %(fp_enable_check)s; 3954572Sacolyte@umich.edu %(op_decl)s; 3964572Sacolyte@umich.edu %(op_rd)s; 3974377Sgblack@eecs.umich.edu %(ea_code)s; 3984377Sgblack@eecs.umich.edu 3994377Sgblack@eecs.umich.edu warn_once("Prefetch instructions in Alpha do not do anything\n"); 4004377Sgblack@eecs.umich.edu if (fault == NoFault) { 4014181Sgblack@eecs.umich.edu %(memacc_code)s; 4024181Sgblack@eecs.umich.edu } 4034181Sgblack@eecs.umich.edu 4044539Sgblack@eecs.umich.edu return NoFault; 4053276Sgblack@eecs.umich.edu } 4065665Sgblack@eecs.umich.edu}}; 4073280Sgblack@eecs.umich.edu 4083280Sgblack@eecs.umich.edu// Prefetches in Alpha don't actually do anything 4093276Sgblack@eecs.umich.edu// They just build an effective address and complete 4103276Sgblack@eecs.umich.edudef template MiscInitiateAcc {{ 4113276Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4125665Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4133276Sgblack@eecs.umich.edu { 4143276Sgblack@eecs.umich.edu warn("initiateAcc undefined: Misc instruction does not support split " 4154181Sgblack@eecs.umich.edu "access method!"); 4164181Sgblack@eecs.umich.edu return NoFault; 4174181Sgblack@eecs.umich.edu } 4184522Ssaidi@eecs.umich.edu}}; 4195784Sgblack@eecs.umich.edu 4205784Sgblack@eecs.umich.edu 4215784Sgblack@eecs.umich.edudef template MiscCompleteAcc {{ 4222470SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, 4234181Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 4244181Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4254522Ssaidi@eecs.umich.edu { 4262623SN/A warn("completeAcc undefined: Misc instruction does not support split " 4272623SN/A "access method!"); 4284181Sgblack@eecs.umich.edu 4292623SN/A return NoFault; 4304181Sgblack@eecs.umich.edu } 4312623SN/A}}; 4322623SN/A 4332623SN/A 4342623SN/A// load instructions use Ra as dest, so check for 4352623SN/A// Ra == 31 to detect nops 4362623SN/Adef template LoadNopCheckDecode {{ 4375086Sgblack@eecs.umich.edu { 4383577Sgblack@eecs.umich.edu AlphaStaticInst *i = new %(class_name)s(machInst); 4392683Sktlim@umich.edu if (RA == 31) { 4405086Sgblack@eecs.umich.edu i = makeNop(i); 4412623SN/A } 4422683Sktlim@umich.edu return i; 4432623SN/A } 4442420SN/A}}; 4452SN/A 4462623SN/A 4472623SN/A// for some load instructions, Ra == 31 indicates a prefetch (not a nop) 4482SN/Adef template LoadPrefetchCheckDecode {{ 4492SN/A { 4502623SN/A if (RA != 31) { 4512623SN/A return new %(class_name)s(machInst); 4522623SN/A } 4532623SN/A else { 4542SN/A return new %(class_name)sPrefetch(machInst); 4555953Ssaidi@eecs.umich.edu } 4565953Ssaidi@eecs.umich.edu } 4575953Ssaidi@eecs.umich.edu}}; 4585953Ssaidi@eecs.umich.edu 4592683Sktlim@umich.edu 4602644Sstever@eecs.umich.edulet {{ 4612644Sstever@eecs.umich.edudef LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4624046Sbinkertn@umich.edu postacc_code = '', base_class = 'MemoryDisp32', 4634046Sbinkertn@umich.edu decode_template = BasicDecode, exec_template_base = ''): 4644046Sbinkertn@umich.edu # Make sure flags are in lists (convert to lists if not). 4652644Sstever@eecs.umich.edu mem_flags = makeList(mem_flags) 4662623SN/A inst_flags = makeList(inst_flags) 4672SN/A 4682SN/A iop = InstObjParams(name, Name, base_class, 4692623SN/A { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 4702623SN/A inst_flags) 4712623SN/A 4724377Sgblack@eecs.umich.edu if mem_flags: 4734377Sgblack@eecs.umich.edu mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] 4742090SN/A s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 4753905Ssaidi@eecs.umich.edu iop.constructor += s 4765120Sgblack@eecs.umich.edu 4775281Sgblack@eecs.umich.edu # select templates 4784377Sgblack@eecs.umich.edu 4793276Sgblack@eecs.umich.edu # The InitiateAcc template is the same for StoreCond templates as the 4804539Sgblack@eecs.umich.edu # corresponding Store template.. 4815665Sgblack@eecs.umich.edu StoreCondInitiateAcc = StoreInitiateAcc 4825665Sgblack@eecs.umich.edu 4835665Sgblack@eecs.umich.edu fullExecTemplate = eval(exec_template_base + 'Execute') 4843276Sgblack@eecs.umich.edu initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 4853276Sgblack@eecs.umich.edu completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 4863280Sgblack@eecs.umich.edu 4875665Sgblack@eecs.umich.edu # (header_output, decoder_output, decode_block, exec_output) 4885665Sgblack@eecs.umich.edu return (LoadStoreDeclare.subst(iop), 4893276Sgblack@eecs.umich.edu LoadStoreConstructor.subst(iop), 4903276Sgblack@eecs.umich.edu decode_template.subst(iop), 4915665Sgblack@eecs.umich.edu fullExecTemplate.subst(iop) 4923276Sgblack@eecs.umich.edu + EACompExecute.subst(iop) 4933280Sgblack@eecs.umich.edu + initiateAccTemplate.subst(iop) 4943276Sgblack@eecs.umich.edu + completeAccTemplate.subst(iop)) 4953276Sgblack@eecs.umich.edu}}; 4963280Sgblack@eecs.umich.edu 4973276Sgblack@eecs.umich.edudef format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }}, 4983276Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 4993276Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5003276Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5013276Sgblack@eecs.umich.edu decode_template = LoadNopCheckDecode, 5023276Sgblack@eecs.umich.edu exec_template_base = 'Load') 5033276Sgblack@eecs.umich.edu}}; 5042SN/A 5052SN/A 5062SN/A// Note that the flags passed in apply only to the prefetch version 5075250Sksewell@umich.edudef format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5085222Sksewell@umich.edu mem_flags = [], pf_flags = [], inst_flags = []) {{ 5095222Sksewell@umich.edu # declare the load instruction object and generate the decode block 5105222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5115222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5125222Sksewell@umich.edu decode_template = LoadPrefetchCheckDecode, 5135222Sksewell@umich.edu exec_template_base = 'Load') 5145222Sksewell@umich.edu 5155222Sksewell@umich.edu # Declare the prefetch instruction object. 5165222Sksewell@umich.edu 5175222Sksewell@umich.edu # Make sure flag args are lists so we can mess with them. 5185222Sksewell@umich.edu mem_flags = makeList(mem_flags) 5195222Sksewell@umich.edu pf_flags = makeList(pf_flags) 5205222Sksewell@umich.edu inst_flags = makeList(inst_flags) 5215222Sksewell@umich.edu 5225222Sksewell@umich.edu pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 5235222Sksewell@umich.edu pf_inst_flags = inst_flags 5245222Sksewell@umich.edu 5255222Sksewell@umich.edu (pf_header_output, pf_decoder_output, _, pf_exec_output) = \ 5265222Sksewell@umich.edu LoadStoreBase(name, Name + 'Prefetch', ea_code, ';', 5275222Sksewell@umich.edu pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5285222Sksewell@umich.edu 5295222Sksewell@umich.edu header_output += pf_header_output 5305222Sksewell@umich.edu decoder_output += pf_decoder_output 5315222Sksewell@umich.edu exec_output += pf_exec_output 5325222Sksewell@umich.edu}}; 5335222Sksewell@umich.edu 5345222Sksewell@umich.edu 5355222Sksewell@umich.edudef format Store(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5365222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5375222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5385222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5395222Sksewell@umich.edu exec_template_base = 'Store') 5405250Sksewell@umich.edu}}; 541 542 543def format StoreCond(memacc_code, postacc_code, 544 ea_code = {{ EA = Rb + disp; }}, 545 mem_flags = [], inst_flags = []) {{ 546 (header_output, decoder_output, decode_block, exec_output) = \ 547 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 548 postacc_code, exec_template_base = 'StoreCond') 549}}; 550 551 552// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb 553def format MiscPrefetch(ea_code, memacc_code, 554 mem_flags = [], inst_flags = []) {{ 555 (header_output, decoder_output, decode_block, exec_output) = \ 556 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 557 base_class = 'MemoryNoDisp', exec_template_base = 'Misc') 558}}; 559 560 561