mem.isa revision 8442
11689SN/A// -*- mode:c++ -*- 22326SN/A 31689SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 41689SN/A// All rights reserved. 51689SN/A// 61689SN/A// Redistribution and use in source and binary forms, with or without 71689SN/A// modification, are permitted provided that the following conditions are 81689SN/A// met: redistributions of source code must retain the above copyright 91689SN/A// notice, this list of conditions and the following disclaimer; 101689SN/A// redistributions in binary form must reproduce the above copyright 111689SN/A// notice, this list of conditions and the following disclaimer in the 121689SN/A// documentation and/or other materials provided with the distribution; 131689SN/A// neither the name of the copyright holders nor the names of its 141689SN/A// contributors may be used to endorse or promote products derived from 151689SN/A// this software without specific prior written permission. 161689SN/A// 171689SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292831Sksewell@umich.edu// Authors: Steve Reinhardt 301689SN/A// Kevin Lim 311689SN/A 322064SN/A//////////////////////////////////////////////////////////////////// 331060SN/A// 341060SN/A// Memory-format instructions: LoadAddress, Load, Store 352292SN/A// 361717SN/A 374762Snate@binkert.orgoutput header {{ 386221Snate@binkert.org /** 394762Snate@binkert.org * Base class for general Alpha memory-format instructions. 401060SN/A */ 416221Snate@binkert.org class Memory : public AlphaStaticInst 425529Snate@binkert.org { 431061SN/A protected: 442292SN/A 455606Snate@binkert.org /// Memory request flags. See mem_req_base.hh. 465606Snate@binkert.org Request::Flags memAccessFlags; 475606Snate@binkert.org 481060SN/A /// Constructor 492292SN/A Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 502292SN/A : AlphaStaticInst(mnem, _machInst, __opClass) 512292SN/A { 522292SN/A } 532292SN/A 542292SN/A std::string 552292SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 562326SN/A }; 572292SN/A 582292SN/A /** 592292SN/A * Base class for memory-format instructions using a 32-bit 602292SN/A * displacement (i.e. most of them). 612292SN/A */ 622292SN/A class MemoryDisp32 : public Memory 635336Shines@cs.fsu.edu { 642292SN/A protected: 654873Sstever@eecs.umich.edu /// Displacement for EA calculation (signed). 662292SN/A int32_t disp; 672292SN/A 682292SN/A /// Constructor. 694329Sktlim@umich.edu MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 705529Snate@binkert.org : Memory(mnem, _machInst, __opClass), 714329Sktlim@umich.edu disp(MEMDISP) 724329Sktlim@umich.edu { 734329Sktlim@umich.edu } 742292SN/A }; 752292SN/A 762292SN/A 772292SN/A /** 782292SN/A * Base class for a few miscellaneous memory-format insts 792292SN/A * that don't interpret the disp field: wh64, fetch, fetch_m, ecb. 802292SN/A * None of these instructions has a destination register either. 812292SN/A */ 822307SN/A class MemoryNoDisp : public Memory 832307SN/A { 845529Snate@binkert.org protected: 851060SN/A /// Constructor 861060SN/A MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 871060SN/A : Memory(mnem, _machInst, __opClass) 881060SN/A { 891060SN/A } 901060SN/A 912326SN/A std::string 921060SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 931060SN/A }; 941060SN/A}}; 951060SN/A 962292SN/A 976221Snate@binkert.orgoutput decoder {{ 986221Snate@binkert.org std::string 996221Snate@binkert.org Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1001060SN/A { 1011060SN/A return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 1022307SN/A flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB); 1032292SN/A } 1042980Sgblack@eecs.umich.edu 1052292SN/A std::string 1062292SN/A MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1072292SN/A { 1082292SN/A return csprintf("%-10s (r%d)", mnemonic, RB); 1092292SN/A } 1102292SN/A}}; 1112292SN/A 1122292SN/Adef format LoadAddress(code) {{ 1132292SN/A iop = InstObjParams(name, Name, 'MemoryDisp32', code) 1142292SN/A header_output = BasicDeclare.subst(iop) 1156221Snate@binkert.org decoder_output = BasicConstructor.subst(iop) 1166221Snate@binkert.org decode_block = BasicDecode.subst(iop) 1172292SN/A exec_output = BasicExecute.subst(iop) 1182292SN/A}}; 1192292SN/A 1202292SN/A 1212292SN/Adef template LoadStoreDeclare {{ 1222292SN/A /** 1232292SN/A * Static instruction class for "%(mnemonic)s". 1242292SN/A */ 1252292SN/A class %(class_name)s : public %(base_class)s 1266221Snate@binkert.org { 1276221Snate@binkert.org public: 1282292SN/A 1292292SN/A /// Constructor. 1302831Sksewell@umich.edu %(class_name)s(ExtMachInst machInst); 1312292SN/A 1322292SN/A %(BasicExecDeclare)s 1332292SN/A 1342292SN/A %(EACompDeclare)s 1352292SN/A 1362292SN/A %(InitiateAccDeclare)s 1372292SN/A 1382292SN/A %(CompleteAccDeclare)s 1392292SN/A }; 1406221Snate@binkert.org}}; 1416221Snate@binkert.org 1422292SN/A 1432292SN/Adef template EACompDeclare {{ 1442831Sksewell@umich.edu Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1452292SN/A}}; 1462292SN/A 1472292SN/Adef template InitiateAccDeclare {{ 1482292SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1492292SN/A}}; 1502292SN/A 1512292SN/A 1522292SN/Adef template CompleteAccDeclare {{ 1532292SN/A Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, 1542292SN/A Trace::InstRecord *) const; 1552326SN/A}}; 1562348SN/A 1572326SN/Adef template LoadStoreConstructor {{ 1582326SN/A inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 1592348SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1602292SN/A { 1612292SN/A %(constructor)s; 1622292SN/A } 1632292SN/A}}; 1642292SN/A 1652292SN/Adef template EACompExecute {{ 1662292SN/A Fault %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 1671060SN/A Trace::InstRecord *traceData) const 1681060SN/A { 1691061SN/A Addr EA; 1701060SN/A Fault fault = NoFault; 1711062SN/A 1721062SN/A %(fp_enable_check)s; 1732301SN/A %(op_decl)s; 1741062SN/A %(op_rd)s; 1751062SN/A %(ea_code)s; 1761062SN/A 1771062SN/A if (fault == NoFault) { 1781062SN/A %(op_wb)s; 1791062SN/A xc->setEA(EA); 1801062SN/A } 1811062SN/A 1821062SN/A return fault; 1831062SN/A } 1842301SN/A}}; 1852301SN/A 1862301SN/A 1872301SN/Adef template LoadExecute {{ 1881062SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1891062SN/A Trace::InstRecord *traceData) const 1901062SN/A { 1911062SN/A Addr EA; 1921062SN/A Fault fault = NoFault; 1931062SN/A 1941062SN/A %(fp_enable_check)s; 1951062SN/A %(op_decl)s; 1961062SN/A %(op_rd)s; 1971062SN/A %(ea_code)s; 1981062SN/A 1991062SN/A if (fault == NoFault) { 2001062SN/A fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 2011062SN/A %(memacc_code)s; 2021062SN/A } 2031062SN/A 2041062SN/A if (fault == NoFault) { 2051062SN/A %(op_wb)s; 2061062SN/A } 2071062SN/A 2081062SN/A return fault; 2091062SN/A } 2101062SN/A}}; 2111062SN/A 2121062SN/A 2131062SN/Adef template LoadInitiateAcc {{ 2141062SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2151062SN/A Trace::InstRecord *traceData) const 2161062SN/A { 2171062SN/A Addr EA; 2181062SN/A Fault fault = NoFault; 2191062SN/A 2201062SN/A %(fp_enable_check)s; 2211062SN/A %(op_src_decl)s; 2221062SN/A %(op_rd)s; 2231062SN/A %(ea_code)s; 2241062SN/A 2251062SN/A if (fault == NoFault) { 2261062SN/A fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags); 2271062SN/A } 2281062SN/A 2291062SN/A return fault; 2301062SN/A } 2311062SN/A}}; 2321062SN/A 2331062SN/A 2341062SN/Adef template LoadCompleteAcc {{ 2352361SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, 2362326SN/A %(CPU_exec_context)s *xc, 2372301SN/A Trace::InstRecord *traceData) const 2382301SN/A { 2392301SN/A Fault fault = NoFault; 2402301SN/A 2412301SN/A %(fp_enable_check)s; 2422301SN/A %(op_decl)s; 2432326SN/A 2442301SN/A getMem(pkt, Mem, traceData); 2452361SN/A 2462326SN/A if (fault == NoFault) { 2472307SN/A %(memacc_code)s; 2482301SN/A } 2492301SN/A 2502307SN/A if (fault == NoFault) { 2512301SN/A %(op_wb)s; 2522301SN/A } 2532301SN/A 2542301SN/A return fault; 2552301SN/A } 2562301SN/A}}; 2572301SN/A 2582301SN/A 2592301SN/Adef template StoreExecute {{ 2602301SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2612301SN/A Trace::InstRecord *traceData) const 2622301SN/A { 2632326SN/A Addr EA; 2644762Snate@binkert.org Fault fault = NoFault; 2652301SN/A 2662301SN/A %(fp_enable_check)s; 2672301SN/A %(op_decl)s; 2682301SN/A %(op_rd)s; 2694762Snate@binkert.org %(ea_code)s; 2702301SN/A 2712301SN/A if (fault == NoFault) { 2722301SN/A %(memacc_code)s; 2732301SN/A } 2742361SN/A 2752326SN/A if (fault == NoFault) { 2762301SN/A fault = writeMemAtomic(xc, traceData, Mem, EA, 2772301SN/A memAccessFlags, NULL); 2782301SN/A } 2792301SN/A 2802301SN/A if (fault == NoFault) { 2812301SN/A %(postacc_code)s; 2822301SN/A } 2832980Sgblack@eecs.umich.edu 2842301SN/A if (fault == NoFault) { 2852326SN/A %(op_wb)s; 2862301SN/A } 2872361SN/A 2882326SN/A return fault; 2892301SN/A } 2902301SN/A}}; 2912301SN/A 2922301SN/Adef template StoreCondExecute {{ 2932326SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2942727Sktlim@umich.edu Trace::InstRecord *traceData) const 2952326SN/A { 2962301SN/A Addr EA; 2972301SN/A Fault fault = NoFault; 2982301SN/A uint64_t write_result = 0; 2992301SN/A 3002301SN/A %(fp_enable_check)s; 3012301SN/A %(op_decl)s; 3024762Snate@binkert.org %(op_rd)s; 3032301SN/A %(ea_code)s; 3042301SN/A 3052326SN/A if (fault == NoFault) { 3062301SN/A %(memacc_code)s; 3072301SN/A } 3082301SN/A 3092301SN/A if (fault == NoFault) { 3102301SN/A fault = writeMemAtomic(xc, traceData, Mem, EA, 3112301SN/A memAccessFlags, &write_result); 3122326SN/A } 3132301SN/A 3142301SN/A if (fault == NoFault) { 3152301SN/A %(postacc_code)s; 3162301SN/A } 3172326SN/A 3182301SN/A if (fault == NoFault) { 3196221Snate@binkert.org %(op_wb)s; 3202292SN/A } 3216221Snate@binkert.org 3222292SN/A return fault; 3231062SN/A } 3241062SN/A}}; 3251062SN/A 3261062SN/Adef template StoreInitiateAcc {{ 3272307SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3281060SN/A Trace::InstRecord *traceData) const 3292307SN/A { 3306221Snate@binkert.org Addr EA; 3316221Snate@binkert.org Fault fault = NoFault; 3326221Snate@binkert.org 3332307SN/A %(fp_enable_check)s; 3341060SN/A %(op_decl)s; 3352307SN/A %(op_rd)s; 3362307SN/A %(ea_code)s; 3372307SN/A 3382307SN/A if (fault == NoFault) { 3392307SN/A %(memacc_code)s; 3402307SN/A } 3412307SN/A 3422307SN/A if (fault == NoFault) { 3432307SN/A fault = writeMemTiming(xc, traceData, Mem, EA, 3442307SN/A memAccessFlags, NULL); 3452307SN/A } 3462307SN/A 3476221Snate@binkert.org return fault; 3486221Snate@binkert.org } 3492307SN/A}}; 3502307SN/A 3512307SN/A 3522307SN/Adef template StoreCompleteAcc {{ 3532307SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, 3542307SN/A %(CPU_exec_context)s *xc, 3552307SN/A Trace::InstRecord *traceData) const 3562307SN/A { 3572307SN/A return NoFault; 3582307SN/A } 3591060SN/A}}; 3601060SN/A 3611061SN/A 3621060SN/Adef template StoreCondCompleteAcc {{ 3636221Snate@binkert.org Fault %(class_name)s::completeAcc(PacketPtr pkt, 3641060SN/A %(CPU_exec_context)s *xc, 3652292SN/A Trace::InstRecord *traceData) const 3662064SN/A { 3672064SN/A Fault fault = NoFault; 3682064SN/A 3692064SN/A %(fp_enable_check)s; 3702292SN/A %(op_dest_decl)s; 3712064SN/A 3724318Sktlim@umich.edu uint64_t write_result = pkt->req->getExtraData(); 3731060SN/A 3741060SN/A if (fault == NoFault) { 3751061SN/A %(postacc_code)s; 3761060SN/A } 3771060SN/A 3781060SN/A if (fault == NoFault) { 3791060SN/A %(op_wb)s; 3801060SN/A } 3811060SN/A 3821060SN/A return fault; 3831060SN/A } 3841684SN/A}}; 3852307SN/A 3862307SN/A 3872307SN/Adef template MiscExecute {{ 3882367SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3892367SN/A Trace::InstRecord *traceData) const 3902367SN/A { 3912367SN/A Addr EA; 3922367SN/A Fault fault = NoFault; 3932367SN/A 3942367SN/A %(fp_enable_check)s; 3952307SN/A %(op_decl)s; 3962326SN/A %(op_rd)s; 3972367SN/A %(ea_code)s; 3982307SN/A 3996221Snate@binkert.org warn_once("Prefetch instructions in Alpha do not do anything\n"); 4006221Snate@binkert.org if (fault == NoFault) { 4012307SN/A %(memacc_code)s; 4022307SN/A } 4032307SN/A 4042307SN/A return NoFault; 4052307SN/A } 4062307SN/A}}; 4072307SN/A 4082307SN/A// Prefetches in Alpha don't actually do anything 4092307SN/A// They just build an effective address and complete 4102307SN/Adef template MiscInitiateAcc {{ 4112307SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4122292SN/A Trace::InstRecord *traceData) const 4136221Snate@binkert.org { 4142292SN/A warn("initiateAcc undefined: Misc instruction does not support split " 4152292SN/A "access method!"); 4162292SN/A return NoFault; 4172292SN/A } 4182292SN/A}}; 4192292SN/A 4202292SN/A 4212292SN/Adef template MiscCompleteAcc {{ 4222292SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, 4232292SN/A %(CPU_exec_context)s *xc, 4242292SN/A Trace::InstRecord *traceData) const 4252292SN/A { 4262292SN/A warn("completeAcc undefined: Misc instruction does not support split " 4272292SN/A "access method!"); 4283867Sbinkertn@umich.edu 4292292SN/A return NoFault; 4306221Snate@binkert.org } 4316221Snate@binkert.org}}; 4322292SN/A 4333867Sbinkertn@umich.edu 4346221Snate@binkert.org// load instructions use Ra as dest, so check for 4353867Sbinkertn@umich.edu// Ra == 31 to detect nops 4362292SN/Adef template LoadNopCheckDecode {{ 4373867Sbinkertn@umich.edu { 4382292SN/A AlphaStaticInst *i = new %(class_name)s(machInst); 4393867Sbinkertn@umich.edu if (RA == 31) { 4402292SN/A i = makeNop(i); 4412292SN/A } 4422292SN/A return i; 4432292SN/A } 4442292SN/A}}; 4452292SN/A 4461684SN/A 4471684SN/A// for some load instructions, Ra == 31 indicates a prefetch (not a nop) 4481684SN/Adef template LoadPrefetchCheckDecode {{ 4491684SN/A { 4501684SN/A if (RA != 31) { 4511684SN/A return new %(class_name)s(machInst); 4522292SN/A } 4532292SN/A else { 4546221Snate@binkert.org return new %(class_name)sPrefetch(machInst); 4552292SN/A } 4562292SN/A } 4572292SN/A}}; 4582292SN/A 4591060SN/A 4601060SN/Alet {{ 4611061SN/Adef LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4621060SN/A postacc_code = '', base_class = 'MemoryDisp32', 4631060SN/A decode_template = BasicDecode, exec_template_base = ''): 4641060SN/A # Make sure flags are in lists (convert to lists if not). 4651060SN/A mem_flags = makeList(mem_flags) 4661060SN/A inst_flags = makeList(inst_flags) 4671060SN/A 4681060SN/A # Some CPU models execute the memory operation as an atomic unit, 4691060SN/A # while others want to separate them into an effective address 4701060SN/A # computation and a memory access operation. As a result, we need 4711060SN/A # to generate three StaticInst objects. Note that the latter two 4721061SN/A # are nested inside the larger "atomic" one. 4732292SN/A 4746221Snate@binkert.org # Generate InstObjParams for each of the three objects. Note that 4752292SN/A # they differ only in the set of code objects contained (which in 4762292SN/A # turn affects the object's overall operand list). 4772292SN/A iop = InstObjParams(name, Name, base_class, 4782292SN/A { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 4792292SN/A inst_flags) 4802292SN/A memacc_iop = InstObjParams(name, Name, base_class, 4812292SN/A { 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 4822292SN/A inst_flags) 4832292SN/A 4842292SN/A if mem_flags: 4852292SN/A mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] 4862292SN/A s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 4872292SN/A iop.constructor += s 4882292SN/A memacc_iop.constructor += s 4892292SN/A 4902292SN/A # select templates 4912292SN/A 4922292SN/A # The InitiateAcc template is the same for StoreCond templates as the 4932292SN/A # corresponding Store template.. 4942292SN/A StoreCondInitiateAcc = StoreInitiateAcc 4952292SN/A 4962292SN/A fullExecTemplate = eval(exec_template_base + 'Execute') 4972292SN/A initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 4982292SN/A completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 4992292SN/A 5002292SN/A # (header_output, decoder_output, decode_block, exec_output) 5011060SN/A return (LoadStoreDeclare.subst(iop), 5021061SN/A LoadStoreConstructor.subst(iop), 5031060SN/A decode_template.subst(iop), 5041060SN/A fullExecTemplate.subst(iop) 5051060SN/A + EACompExecute.subst(iop) 5061060SN/A + initiateAccTemplate.subst(iop) 5072326SN/A + completeAccTemplate.subst(iop)) 5082326SN/A}}; 5091060SN/A 5101060SN/Adef format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5111060SN/A mem_flags = [], inst_flags = []) {{ 5122292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5131060SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5142064SN/A decode_template = LoadNopCheckDecode, 5151060SN/A exec_template_base = 'Load') 5162292SN/A}}; 5171060SN/A 5181060SN/A 5191060SN/A// Note that the flags passed in apply only to the prefetch version 5201060SN/Adef format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5211060SN/A mem_flags = [], pf_flags = [], inst_flags = []) {{ 5221060SN/A # declare the load instruction object and generate the decode block 5231060SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5242326SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5251060SN/A decode_template = LoadPrefetchCheckDecode, 5261061SN/A exec_template_base = 'Load') 5272292SN/A 5281062SN/A # Declare the prefetch instruction object. 5291062SN/A 5301061SN/A # Make sure flag args are lists so we can mess with them. 5311061SN/A mem_flags = makeList(mem_flags) 5321062SN/A pf_flags = makeList(pf_flags) 5331060SN/A inst_flags = makeList(inst_flags) 5342292SN/A 5352292SN/A pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 5361060SN/A pf_inst_flags = inst_flags 5371060SN/A 5381060SN/A (pf_header_output, pf_decoder_output, _, pf_exec_output) = \ 5391061SN/A LoadStoreBase(name, Name + 'Prefetch', ea_code, ';', 5401061SN/A pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5412292SN/A 5421061SN/A header_output += pf_header_output 5431061SN/A decoder_output += pf_decoder_output 5441061SN/A exec_output += pf_exec_output 5451061SN/A}}; 5462292SN/A 5471061SN/A 5482292SN/Adef format Store(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5491061SN/A mem_flags = [], inst_flags = []) {{ 5502326SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5512326SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5522326SN/A exec_template_base = 'Store') 5532064SN/A}}; 5541061SN/A 5551061SN/A 5562292SN/Adef format StoreCond(memacc_code, postacc_code, 5571061SN/A ea_code = {{ EA = Rb + disp; }}, 5582064SN/A mem_flags = [], inst_flags = []) {{ 5591061SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5602292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5611061SN/A postacc_code, exec_template_base = 'StoreCond') 5621061SN/A}}; 5631061SN/A 5642326SN/A 5651061SN/A// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb 5661061SN/Adef format MiscPrefetch(ea_code, memacc_code, 5671061SN/A mem_flags = [], inst_flags = []) {{ 5682292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5692292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5701061SN/A base_class = 'MemoryNoDisp', exec_template_base = 'Misc') 5711062SN/A}}; 5721062SN/A 5732292SN/A 5742292SN/A