mem.isa revision 7725
12068SN/A// -*- mode:c++ -*- 22068SN/A 32068SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 42068SN/A// All rights reserved. 52068SN/A// 62068SN/A// Redistribution and use in source and binary forms, with or without 72068SN/A// modification, are permitted provided that the following conditions are 82068SN/A// met: redistributions of source code must retain the above copyright 92068SN/A// notice, this list of conditions and the following disclaimer; 102068SN/A// redistributions in binary form must reproduce the above copyright 112068SN/A// notice, this list of conditions and the following disclaimer in the 122068SN/A// documentation and/or other materials provided with the distribution; 132068SN/A// neither the name of the copyright holders nor the names of its 142068SN/A// contributors may be used to endorse or promote products derived from 152068SN/A// this software without specific prior written permission. 162068SN/A// 172068SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182068SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192068SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202068SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212068SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222068SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232068SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242068SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252068SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262068SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272068SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292665Ssaidi@eecs.umich.edu// Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu// Kevin Lim 312068SN/A 322649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 332649Ssaidi@eecs.umich.edu// 342649Ssaidi@eecs.umich.edu// Memory-format instructions: LoadAddress, Load, Store 352649Ssaidi@eecs.umich.edu// 362649Ssaidi@eecs.umich.edu 372068SN/Aoutput header {{ 382068SN/A /** 392068SN/A * Base class for general Alpha memory-format instructions. 402068SN/A */ 412068SN/A class Memory : public AlphaStaticInst 422068SN/A { 432068SN/A protected: 442068SN/A 452068SN/A /// Memory request flags. See mem_req_base.hh. 465736Snate@binkert.org Request::Flags memAccessFlags; 472068SN/A 482068SN/A /// Constructor 496181Sksewell@umich.edu Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 506181Sksewell@umich.edu : AlphaStaticInst(mnem, _machInst, __opClass) 512068SN/A { 522068SN/A } 532068SN/A 542068SN/A std::string 552068SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 562068SN/A }; 572068SN/A 582068SN/A /** 592068SN/A * Base class for memory-format instructions using a 32-bit 602068SN/A * displacement (i.e. most of them). 612068SN/A */ 622068SN/A class MemoryDisp32 : public Memory 632068SN/A { 642068SN/A protected: 652068SN/A /// Displacement for EA calculation (signed). 662068SN/A int32_t disp; 672068SN/A 682068SN/A /// Constructor. 696181Sksewell@umich.edu MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 706181Sksewell@umich.edu : Memory(mnem, _machInst, __opClass), 712068SN/A disp(MEMDISP) 722068SN/A { 732068SN/A } 742068SN/A }; 752068SN/A 762068SN/A 772068SN/A /** 782068SN/A * Base class for a few miscellaneous memory-format insts 792068SN/A * that don't interpret the disp field: wh64, fetch, fetch_m, ecb. 802068SN/A * None of these instructions has a destination register either. 812068SN/A */ 822068SN/A class MemoryNoDisp : public Memory 832068SN/A { 842068SN/A protected: 852068SN/A /// Constructor 866181Sksewell@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 876181Sksewell@umich.edu : Memory(mnem, _machInst, __opClass) 882068SN/A { 892068SN/A } 902068SN/A 912068SN/A std::string 922068SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 932068SN/A }; 942068SN/A}}; 952068SN/A 962068SN/A 972068SN/Aoutput decoder {{ 982068SN/A std::string 992068SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1002068SN/A { 1012068SN/A return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 1022068SN/A flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB); 1032068SN/A } 1042068SN/A 1052068SN/A std::string 1062068SN/A MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1072068SN/A { 1082068SN/A return csprintf("%-10s (r%d)", mnemonic, RB); 1092068SN/A } 1102068SN/A}}; 1112068SN/A 1122068SN/Adef format LoadAddress(code) {{ 1133953Sstever@eecs.umich.edu iop = InstObjParams(name, Name, 'MemoryDisp32', code) 1142068SN/A header_output = BasicDeclare.subst(iop) 1152068SN/A decoder_output = BasicConstructor.subst(iop) 1162068SN/A decode_block = BasicDecode.subst(iop) 1172068SN/A exec_output = BasicExecute.subst(iop) 1182068SN/A}}; 1192068SN/A 1202068SN/A 1212068SN/Adef template LoadStoreDeclare {{ 1222068SN/A /** 1232068SN/A * Static instruction class for "%(mnemonic)s". 1242068SN/A */ 1252068SN/A class %(class_name)s : public %(base_class)s 1262068SN/A { 1272068SN/A public: 1282068SN/A 1292068SN/A /// Constructor. 1302227SN/A %(class_name)s(ExtMachInst machInst); 1312068SN/A 1322068SN/A %(BasicExecDeclare)s 1332095SN/A 1346181Sksewell@umich.edu %(EACompDeclare)s 1356181Sksewell@umich.edu 1362095SN/A %(InitiateAccDeclare)s 1372095SN/A 1382095SN/A %(CompleteAccDeclare)s 1392068SN/A }; 1402068SN/A}}; 1412068SN/A 1422095SN/A 1436181Sksewell@umich.edudef template EACompDeclare {{ 1446181Sksewell@umich.edu Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1456181Sksewell@umich.edu}}; 1466181Sksewell@umich.edu 1472095SN/Adef template InitiateAccDeclare {{ 1482132SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1492095SN/A}}; 1502095SN/A 1512095SN/A 1522095SN/Adef template CompleteAccDeclare {{ 1533349Sbinkertn@umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, 1542623SN/A Trace::InstRecord *) const; 1552095SN/A}}; 1562095SN/A 1576181Sksewell@umich.edudef template LoadStoreConstructor {{ 1586181Sksewell@umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 1596181Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1602068SN/A { 1613953Sstever@eecs.umich.edu %(constructor)s; 1622068SN/A } 1633953Sstever@eecs.umich.edu}}; 1642068SN/A 1652068SN/Adef template EACompExecute {{ 1666181Sksewell@umich.edu Fault %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 1676181Sksewell@umich.edu Trace::InstRecord *traceData) const 1682068SN/A { 1692068SN/A Addr EA; 1702132SN/A Fault fault = NoFault; 1712068SN/A 1722068SN/A %(fp_enable_check)s; 1732068SN/A %(op_decl)s; 1742068SN/A %(op_rd)s; 1753953Sstever@eecs.umich.edu %(ea_code)s; 1762068SN/A 1772090SN/A if (fault == NoFault) { 1782068SN/A %(op_wb)s; 1792068SN/A xc->setEA(EA); 1802068SN/A } 1812068SN/A 1822068SN/A return fault; 1832068SN/A } 1842068SN/A}}; 1852068SN/A 1862068SN/A 1872069SN/Adef template LoadExecute {{ 1882132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1892068SN/A Trace::InstRecord *traceData) const 1902068SN/A { 1912068SN/A Addr EA; 1922132SN/A Fault fault = NoFault; 1932068SN/A 1942068SN/A %(fp_enable_check)s; 1952068SN/A %(op_decl)s; 1962069SN/A %(op_rd)s; 1972068SN/A %(ea_code)s; 1982068SN/A 1992090SN/A if (fault == NoFault) { 2002069SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 2012068SN/A %(memacc_code)s; 2022068SN/A } 2032068SN/A 2042090SN/A if (fault == NoFault) { 2052069SN/A %(op_wb)s; 2062069SN/A } 2072069SN/A 2082069SN/A return fault; 2092069SN/A } 2102069SN/A}}; 2112069SN/A 2122069SN/A 2132095SN/Adef template LoadInitiateAcc {{ 2142132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2152095SN/A Trace::InstRecord *traceData) const 2162095SN/A { 2172095SN/A Addr EA; 2182132SN/A Fault fault = NoFault; 2192095SN/A 2202095SN/A %(fp_enable_check)s; 2212095SN/A %(op_src_decl)s; 2222095SN/A %(op_rd)s; 2232095SN/A %(ea_code)s; 2242095SN/A 2252098SN/A if (fault == NoFault) { 2262095SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 2272095SN/A } 2282095SN/A 2292095SN/A return fault; 2302095SN/A } 2312095SN/A}}; 2322095SN/A 2332095SN/A 2342095SN/Adef template LoadCompleteAcc {{ 2353349Sbinkertn@umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 2362095SN/A %(CPU_exec_context)s *xc, 2372095SN/A Trace::InstRecord *traceData) const 2382095SN/A { 2392132SN/A Fault fault = NoFault; 2402095SN/A 2412095SN/A %(fp_enable_check)s; 2422506SN/A %(op_decl)s; 2432095SN/A 2442623SN/A Mem = pkt->get<typeof(Mem)>(); 2452095SN/A 2462098SN/A if (fault == NoFault) { 2472095SN/A %(memacc_code)s; 2482095SN/A } 2492095SN/A 2502098SN/A if (fault == NoFault) { 2512095SN/A %(op_wb)s; 2522095SN/A } 2532095SN/A 2542095SN/A return fault; 2552095SN/A } 2562095SN/A}}; 2572095SN/A 2582095SN/A 2592069SN/Adef template StoreExecute {{ 2602132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2612069SN/A Trace::InstRecord *traceData) const 2622069SN/A { 2632069SN/A Addr EA; 2642132SN/A Fault fault = NoFault; 2654027Sstever@eecs.umich.edu 2664027Sstever@eecs.umich.edu %(fp_enable_check)s; 2674027Sstever@eecs.umich.edu %(op_decl)s; 2684027Sstever@eecs.umich.edu %(op_rd)s; 2694027Sstever@eecs.umich.edu %(ea_code)s; 2704027Sstever@eecs.umich.edu 2714027Sstever@eecs.umich.edu if (fault == NoFault) { 2724027Sstever@eecs.umich.edu %(memacc_code)s; 2734027Sstever@eecs.umich.edu } 2744027Sstever@eecs.umich.edu 2754027Sstever@eecs.umich.edu if (fault == NoFault) { 2764027Sstever@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2774027Sstever@eecs.umich.edu memAccessFlags, NULL); 2784027Sstever@eecs.umich.edu } 2794027Sstever@eecs.umich.edu 2804027Sstever@eecs.umich.edu if (fault == NoFault) { 2814027Sstever@eecs.umich.edu %(postacc_code)s; 2824027Sstever@eecs.umich.edu } 2834027Sstever@eecs.umich.edu 2844027Sstever@eecs.umich.edu if (fault == NoFault) { 2854027Sstever@eecs.umich.edu %(op_wb)s; 2864027Sstever@eecs.umich.edu } 2874027Sstever@eecs.umich.edu 2884027Sstever@eecs.umich.edu return fault; 2894027Sstever@eecs.umich.edu } 2904027Sstever@eecs.umich.edu}}; 2914027Sstever@eecs.umich.edu 2924027Sstever@eecs.umich.edudef template StoreCondExecute {{ 2934027Sstever@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2944027Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 2954027Sstever@eecs.umich.edu { 2964027Sstever@eecs.umich.edu Addr EA; 2974027Sstever@eecs.umich.edu Fault fault = NoFault; 2982069SN/A uint64_t write_result = 0; 2992069SN/A 3002069SN/A %(fp_enable_check)s; 3012069SN/A %(op_decl)s; 3022069SN/A %(op_rd)s; 3032069SN/A %(ea_code)s; 3042069SN/A 3052090SN/A if (fault == NoFault) { 3062069SN/A %(memacc_code)s; 3072069SN/A } 3082069SN/A 3092090SN/A if (fault == NoFault) { 3102069SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3112069SN/A memAccessFlags, &write_result); 3122069SN/A } 3132069SN/A 3142090SN/A if (fault == NoFault) { 3152069SN/A %(postacc_code)s; 3162069SN/A } 3172069SN/A 3182090SN/A if (fault == NoFault) { 3192069SN/A %(op_wb)s; 3202069SN/A } 3212069SN/A 3222069SN/A return fault; 3232069SN/A } 3242069SN/A}}; 3252069SN/A 3262095SN/Adef template StoreInitiateAcc {{ 3272132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3282095SN/A Trace::InstRecord *traceData) const 3292095SN/A { 3302095SN/A Addr EA; 3312132SN/A Fault fault = NoFault; 3322095SN/A 3332095SN/A %(fp_enable_check)s; 3342506SN/A %(op_decl)s; 3352095SN/A %(op_rd)s; 3362095SN/A %(ea_code)s; 3372095SN/A 3382098SN/A if (fault == NoFault) { 3392095SN/A %(memacc_code)s; 3402095SN/A } 3412095SN/A 3422098SN/A if (fault == NoFault) { 3432095SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3442623SN/A memAccessFlags, NULL); 3452095SN/A } 3462095SN/A 3472095SN/A return fault; 3482095SN/A } 3492095SN/A}}; 3502095SN/A 3512095SN/A 3522095SN/Adef template StoreCompleteAcc {{ 3533349Sbinkertn@umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 3542095SN/A %(CPU_exec_context)s *xc, 3552095SN/A Trace::InstRecord *traceData) const 3562095SN/A { 3577712Sgblack@eecs.umich.edu return NoFault; 3582623SN/A } 3592623SN/A}}; 3602623SN/A 3612623SN/A 3622623SN/Adef template StoreCondCompleteAcc {{ 3633349Sbinkertn@umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 3642623SN/A %(CPU_exec_context)s *xc, 3652623SN/A Trace::InstRecord *traceData) const 3662623SN/A { 3672623SN/A Fault fault = NoFault; 3682623SN/A 3692623SN/A %(fp_enable_check)s; 3702623SN/A %(op_dest_decl)s; 3712623SN/A 3724040Ssaidi@eecs.umich.edu uint64_t write_result = pkt->req->getExtraData(); 3732095SN/A 3742098SN/A if (fault == NoFault) { 3752095SN/A %(postacc_code)s; 3762095SN/A } 3772095SN/A 3782098SN/A if (fault == NoFault) { 3792095SN/A %(op_wb)s; 3802095SN/A } 3812095SN/A 3822095SN/A return fault; 3832095SN/A } 3842095SN/A}}; 3852095SN/A 3862069SN/A 3872069SN/Adef template MiscExecute {{ 3882132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3892068SN/A Trace::InstRecord *traceData) const 3902068SN/A { 3912068SN/A Addr EA; 3922132SN/A Fault fault = NoFault; 3932068SN/A 3942068SN/A %(fp_enable_check)s; 3952068SN/A %(op_decl)s; 3962069SN/A %(op_rd)s; 3972068SN/A %(ea_code)s; 3982068SN/A 3997725SAli.Saidi@ARM.com warn_once("Prefetch instrutions is Alpha do not do anything\n"); 4002090SN/A if (fault == NoFault) { 4012069SN/A %(memacc_code)s; 4022068SN/A } 4032068SN/A 4042090SN/A return NoFault; 4052068SN/A } 4062068SN/A}}; 4072068SN/A 4087725SAli.Saidi@ARM.com// Prefetches in Alpha don't actually do anything 4097725SAli.Saidi@ARM.com// They just build an effective address and complete 4102095SN/Adef template MiscInitiateAcc {{ 4112132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4122095SN/A Trace::InstRecord *traceData) const 4132095SN/A { 4146185Sksewell@umich.edu warn("initiateAcc undefined: Misc instruction does not support split " 4156185Sksewell@umich.edu "access method!"); 4162098SN/A return NoFault; 4172095SN/A } 4182095SN/A}}; 4192095SN/A 4202095SN/A 4212095SN/Adef template MiscCompleteAcc {{ 4223349Sbinkertn@umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 4232095SN/A %(CPU_exec_context)s *xc, 4242095SN/A Trace::InstRecord *traceData) const 4252095SN/A { 4266185Sksewell@umich.edu warn("completeAcc undefined: Misc instruction does not support split " 4276185Sksewell@umich.edu "access method!"); 4282110SN/A 4292098SN/A return NoFault; 4302095SN/A } 4312095SN/A}}; 4322095SN/A 4336179Sksewell@umich.edu 4342068SN/A// load instructions use Ra as dest, so check for 4352068SN/A// Ra == 31 to detect nops 4362068SN/Adef template LoadNopCheckDecode {{ 4372068SN/A { 4382068SN/A AlphaStaticInst *i = new %(class_name)s(machInst); 4392068SN/A if (RA == 31) { 4402068SN/A i = makeNop(i); 4412068SN/A } 4422068SN/A return i; 4432068SN/A } 4442068SN/A}}; 4452068SN/A 4462068SN/A 4472068SN/A// for some load instructions, Ra == 31 indicates a prefetch (not a nop) 4482068SN/Adef template LoadPrefetchCheckDecode {{ 4492068SN/A { 4502068SN/A if (RA != 31) { 4512068SN/A return new %(class_name)s(machInst); 4522068SN/A } 4532068SN/A else { 4542068SN/A return new %(class_name)sPrefetch(machInst); 4552068SN/A } 4562068SN/A } 4572068SN/A}}; 4582068SN/A 4592068SN/A 4602068SN/Alet {{ 4612075SN/Adef LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4622075SN/A postacc_code = '', base_class = 'MemoryDisp32', 4632069SN/A decode_template = BasicDecode, exec_template_base = ''): 4642075SN/A # Make sure flags are in lists (convert to lists if not). 4652075SN/A mem_flags = makeList(mem_flags) 4662075SN/A inst_flags = makeList(inst_flags) 4672068SN/A 4682068SN/A # Some CPU models execute the memory operation as an atomic unit, 4692068SN/A # while others want to separate them into an effective address 4702068SN/A # computation and a memory access operation. As a result, we need 4712068SN/A # to generate three StaticInst objects. Note that the latter two 4722068SN/A # are nested inside the larger "atomic" one. 4732068SN/A 4743953Sstever@eecs.umich.edu # Generate InstObjParams for each of the three objects. Note that 4753953Sstever@eecs.umich.edu # they differ only in the set of code objects contained (which in 4763953Sstever@eecs.umich.edu # turn affects the object's overall operand list). 4773953Sstever@eecs.umich.edu iop = InstObjParams(name, Name, base_class, 4783953Sstever@eecs.umich.edu { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 4793953Sstever@eecs.umich.edu inst_flags) 4803953Sstever@eecs.umich.edu memacc_iop = InstObjParams(name, Name, base_class, 4813953Sstever@eecs.umich.edu { 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 4823953Sstever@eecs.umich.edu inst_flags) 4832068SN/A 4842068SN/A if mem_flags: 4855736Snate@binkert.org mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] 4865745Snate@binkert.org s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 4872068SN/A iop.constructor += s 4882068SN/A memacc_iop.constructor += s 4892068SN/A 4902069SN/A # select templates 4912623SN/A 4924027Sstever@eecs.umich.edu # The InitiateAcc template is the same for StoreCond templates as the 4934027Sstever@eecs.umich.edu # corresponding Store template.. 4942623SN/A StoreCondInitiateAcc = StoreInitiateAcc 4952623SN/A 4962069SN/A fullExecTemplate = eval(exec_template_base + 'Execute') 4972095SN/A initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 4982095SN/A completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 4992069SN/A 5002068SN/A # (header_output, decoder_output, decode_block, exec_output) 5013953Sstever@eecs.umich.edu return (LoadStoreDeclare.subst(iop), 5026181Sksewell@umich.edu LoadStoreConstructor.subst(iop), 5032068SN/A decode_template.subst(iop), 5046181Sksewell@umich.edu fullExecTemplate.subst(iop) 5056181Sksewell@umich.edu + EACompExecute.subst(iop) 5063953Sstever@eecs.umich.edu + initiateAccTemplate.subst(iop) 5076192Sksewell@umich.edu + completeAccTemplate.subst(iop)) 5082068SN/A}}; 5092068SN/A 5102075SN/Adef format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5112075SN/A mem_flags = [], inst_flags = []) {{ 5122068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5132075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5142069SN/A decode_template = LoadNopCheckDecode, 5152069SN/A exec_template_base = 'Load') 5162068SN/A}}; 5172068SN/A 5182068SN/A 5192068SN/A// Note that the flags passed in apply only to the prefetch version 5202075SN/Adef format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5212075SN/A mem_flags = [], pf_flags = [], inst_flags = []) {{ 5222068SN/A # declare the load instruction object and generate the decode block 5232068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5242075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5252069SN/A decode_template = LoadPrefetchCheckDecode, 5262069SN/A exec_template_base = 'Load') 5272068SN/A 5282068SN/A # Declare the prefetch instruction object. 5292068SN/A 5302075SN/A # Make sure flag args are lists so we can mess with them. 5312075SN/A mem_flags = makeList(mem_flags) 5322075SN/A pf_flags = makeList(pf_flags) 5332075SN/A inst_flags = makeList(inst_flags) 5342075SN/A 5356739Sgblack@eecs.umich.edu pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 5367725SAli.Saidi@ARM.com pf_inst_flags = inst_flags 5372068SN/A 5382068SN/A (pf_header_output, pf_decoder_output, _, pf_exec_output) = \ 5397725SAli.Saidi@ARM.com LoadStoreBase(name, Name + 'Prefetch', ea_code, ';', 5402075SN/A pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5412068SN/A 5422068SN/A header_output += pf_header_output 5432068SN/A decoder_output += pf_decoder_output 5442068SN/A exec_output += pf_exec_output 5452068SN/A}}; 5462068SN/A 5472068SN/A 5482075SN/Adef format Store(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5492075SN/A mem_flags = [], inst_flags = []) {{ 5502068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5512075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5522069SN/A exec_template_base = 'Store') 5532068SN/A}}; 5542068SN/A 5552068SN/A 5562075SN/Adef format StoreCond(memacc_code, postacc_code, 5572075SN/A ea_code = {{ EA = Rb + disp; }}, 5582075SN/A mem_flags = [], inst_flags = []) {{ 5592068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5602075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5612623SN/A postacc_code, exec_template_base = 'StoreCond') 5622068SN/A}}; 5632068SN/A 5642068SN/A 5652068SN/A// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb 5662075SN/Adef format MiscPrefetch(ea_code, memacc_code, 5672075SN/A mem_flags = [], inst_flags = []) {{ 5682068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5692075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5702069SN/A base_class = 'MemoryNoDisp', exec_template_base = 'Misc') 5712068SN/A}}; 5722068SN/A 5732068SN/A 574