mem.isa revision 6185
12068SN/A// -*- mode:c++ -*- 22068SN/A 32068SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 42068SN/A// All rights reserved. 52068SN/A// 62068SN/A// Redistribution and use in source and binary forms, with or without 72068SN/A// modification, are permitted provided that the following conditions are 82068SN/A// met: redistributions of source code must retain the above copyright 92068SN/A// notice, this list of conditions and the following disclaimer; 102068SN/A// redistributions in binary form must reproduce the above copyright 112068SN/A// notice, this list of conditions and the following disclaimer in the 122068SN/A// documentation and/or other materials provided with the distribution; 132068SN/A// neither the name of the copyright holders nor the names of its 142068SN/A// contributors may be used to endorse or promote products derived from 152068SN/A// this software without specific prior written permission. 162068SN/A// 172068SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182068SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192068SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202068SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212068SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222068SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232068SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242068SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252068SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262068SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272068SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292665Ssaidi@eecs.umich.edu// Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu// Kevin Lim 312068SN/A 322649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 332649Ssaidi@eecs.umich.edu// 342649Ssaidi@eecs.umich.edu// Memory-format instructions: LoadAddress, Load, Store 352649Ssaidi@eecs.umich.edu// 362649Ssaidi@eecs.umich.edu 372068SN/Aoutput header {{ 382068SN/A /** 392068SN/A * Base class for general Alpha memory-format instructions. 402068SN/A */ 412068SN/A class Memory : public AlphaStaticInst 422068SN/A { 432068SN/A protected: 442068SN/A 452068SN/A /// Memory request flags. See mem_req_base.hh. 465736Snate@binkert.org Request::Flags memAccessFlags; 472068SN/A 482068SN/A /// Constructor 496181Sksewell@umich.edu Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 506181Sksewell@umich.edu : AlphaStaticInst(mnem, _machInst, __opClass) 512068SN/A { 522068SN/A } 532068SN/A 542068SN/A std::string 552068SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 562068SN/A 576181Sksewell@umich.edu public: 586179Sksewell@umich.edu 596179Sksewell@umich.edu Request::Flags memAccFlags() { return memAccessFlags; } 602068SN/A }; 612068SN/A 622068SN/A /** 632068SN/A * Base class for memory-format instructions using a 32-bit 642068SN/A * displacement (i.e. most of them). 652068SN/A */ 662068SN/A class MemoryDisp32 : public Memory 672068SN/A { 682068SN/A protected: 692068SN/A /// Displacement for EA calculation (signed). 702068SN/A int32_t disp; 712068SN/A 722068SN/A /// Constructor. 736181Sksewell@umich.edu MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 746181Sksewell@umich.edu : Memory(mnem, _machInst, __opClass), 752068SN/A disp(MEMDISP) 762068SN/A { 772068SN/A } 782068SN/A }; 792068SN/A 802068SN/A 812068SN/A /** 822068SN/A * Base class for a few miscellaneous memory-format insts 832068SN/A * that don't interpret the disp field: wh64, fetch, fetch_m, ecb. 842068SN/A * None of these instructions has a destination register either. 852068SN/A */ 862068SN/A class MemoryNoDisp : public Memory 872068SN/A { 882068SN/A protected: 892068SN/A /// Constructor 906181Sksewell@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 916181Sksewell@umich.edu : Memory(mnem, _machInst, __opClass) 922068SN/A { 932068SN/A } 942068SN/A 952068SN/A std::string 962068SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 972068SN/A }; 982068SN/A}}; 992068SN/A 1002068SN/A 1012068SN/Aoutput decoder {{ 1022068SN/A std::string 1032068SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1042068SN/A { 1052068SN/A return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 1062068SN/A flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB); 1072068SN/A } 1082068SN/A 1092068SN/A std::string 1102068SN/A MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1112068SN/A { 1122068SN/A return csprintf("%-10s (r%d)", mnemonic, RB); 1132068SN/A } 1142068SN/A}}; 1152068SN/A 1162068SN/Adef format LoadAddress(code) {{ 1173953Sstever@eecs.umich.edu iop = InstObjParams(name, Name, 'MemoryDisp32', code) 1182068SN/A header_output = BasicDeclare.subst(iop) 1192068SN/A decoder_output = BasicConstructor.subst(iop) 1202068SN/A decode_block = BasicDecode.subst(iop) 1212068SN/A exec_output = BasicExecute.subst(iop) 1222068SN/A}}; 1232068SN/A 1242068SN/A 1252068SN/Adef template LoadStoreDeclare {{ 1262068SN/A /** 1272068SN/A * Static instruction class for "%(mnemonic)s". 1282068SN/A */ 1292068SN/A class %(class_name)s : public %(base_class)s 1302068SN/A { 1312068SN/A public: 1322068SN/A 1332068SN/A /// Constructor. 1342227SN/A %(class_name)s(ExtMachInst machInst); 1352068SN/A 1362068SN/A %(BasicExecDeclare)s 1372095SN/A 1386181Sksewell@umich.edu %(EACompDeclare)s 1396181Sksewell@umich.edu 1402095SN/A %(InitiateAccDeclare)s 1412095SN/A 1422095SN/A %(CompleteAccDeclare)s 1436179Sksewell@umich.edu 1446179Sksewell@umich.edu %(MemAccSizeDeclare)s 1452068SN/A }; 1462068SN/A}}; 1472068SN/A 1482095SN/A 1496181Sksewell@umich.edudef template EACompDeclare {{ 1506181Sksewell@umich.edu Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1516181Sksewell@umich.edu}}; 1526181Sksewell@umich.edu 1532095SN/Adef template InitiateAccDeclare {{ 1542132SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1552095SN/A}}; 1562095SN/A 1572095SN/A 1582095SN/Adef template CompleteAccDeclare {{ 1593349Sbinkertn@umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, 1602623SN/A Trace::InstRecord *) const; 1612095SN/A}}; 1622095SN/A 1636179Sksewell@umich.edudef template MemAccSizeDeclare {{ 1646179Sksewell@umich.edu int memAccSize(%(CPU_exec_context)s *xc); 1656179Sksewell@umich.edu}}; 1666179Sksewell@umich.edu 1676179Sksewell@umich.edudef template LoadStoreMemAccSize {{ 1686179Sksewell@umich.edu int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) 1696179Sksewell@umich.edu { 1706179Sksewell@umich.edu // Return the memory access size in bytes 1716179Sksewell@umich.edu return (%(mem_acc_size)d / 8); 1726179Sksewell@umich.edu } 1736179Sksewell@umich.edu}}; 1742095SN/A 1756181Sksewell@umich.edu 1766181Sksewell@umich.edudef template LoadStoreConstructor {{ 1776181Sksewell@umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 1786181Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1792068SN/A { 1803953Sstever@eecs.umich.edu %(constructor)s; 1812068SN/A } 1823953Sstever@eecs.umich.edu}}; 1832068SN/A 1842068SN/Adef template EACompExecute {{ 1856181Sksewell@umich.edu Fault %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 1866181Sksewell@umich.edu Trace::InstRecord *traceData) const 1872068SN/A { 1882068SN/A Addr EA; 1892132SN/A Fault fault = NoFault; 1902068SN/A 1912068SN/A %(fp_enable_check)s; 1922068SN/A %(op_decl)s; 1932068SN/A %(op_rd)s; 1943953Sstever@eecs.umich.edu %(ea_code)s; 1952068SN/A 1962090SN/A if (fault == NoFault) { 1972068SN/A %(op_wb)s; 1982068SN/A xc->setEA(EA); 1992068SN/A } 2002068SN/A 2012068SN/A return fault; 2022068SN/A } 2032068SN/A}}; 2042068SN/A 2052068SN/A 2062069SN/Adef template LoadExecute {{ 2072132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2082068SN/A Trace::InstRecord *traceData) const 2092068SN/A { 2102068SN/A Addr EA; 2112132SN/A Fault fault = NoFault; 2122068SN/A 2132068SN/A %(fp_enable_check)s; 2142068SN/A %(op_decl)s; 2152069SN/A %(op_rd)s; 2162068SN/A %(ea_code)s; 2172068SN/A 2182090SN/A if (fault == NoFault) { 2192069SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 2202068SN/A %(memacc_code)s; 2212068SN/A } 2222068SN/A 2232090SN/A if (fault == NoFault) { 2242069SN/A %(op_wb)s; 2252069SN/A } 2262069SN/A 2272069SN/A return fault; 2282069SN/A } 2292069SN/A}}; 2302069SN/A 2312069SN/A 2322095SN/Adef template LoadInitiateAcc {{ 2332132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2342095SN/A Trace::InstRecord *traceData) const 2352095SN/A { 2362095SN/A Addr EA; 2372132SN/A Fault fault = NoFault; 2382095SN/A 2392095SN/A %(fp_enable_check)s; 2402095SN/A %(op_src_decl)s; 2412095SN/A %(op_rd)s; 2422095SN/A %(ea_code)s; 2432095SN/A 2442098SN/A if (fault == NoFault) { 2452095SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 2462095SN/A } 2472095SN/A 2482095SN/A return fault; 2492095SN/A } 2502095SN/A}}; 2512095SN/A 2522095SN/A 2532095SN/Adef template LoadCompleteAcc {{ 2543349Sbinkertn@umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 2552095SN/A %(CPU_exec_context)s *xc, 2562095SN/A Trace::InstRecord *traceData) const 2572095SN/A { 2582132SN/A Fault fault = NoFault; 2592095SN/A 2602095SN/A %(fp_enable_check)s; 2612506SN/A %(op_decl)s; 2622095SN/A 2632623SN/A Mem = pkt->get<typeof(Mem)>(); 2642095SN/A 2652098SN/A if (fault == NoFault) { 2662095SN/A %(memacc_code)s; 2672095SN/A } 2682095SN/A 2692098SN/A if (fault == NoFault) { 2702095SN/A %(op_wb)s; 2712095SN/A } 2722095SN/A 2732095SN/A return fault; 2742095SN/A } 2752095SN/A}}; 2762095SN/A 2772095SN/A 2782069SN/Adef template StoreExecute {{ 2792132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2802069SN/A Trace::InstRecord *traceData) const 2812069SN/A { 2822069SN/A Addr EA; 2832132SN/A Fault fault = NoFault; 2844027Sstever@eecs.umich.edu 2854027Sstever@eecs.umich.edu %(fp_enable_check)s; 2864027Sstever@eecs.umich.edu %(op_decl)s; 2874027Sstever@eecs.umich.edu %(op_rd)s; 2884027Sstever@eecs.umich.edu %(ea_code)s; 2894027Sstever@eecs.umich.edu 2904027Sstever@eecs.umich.edu if (fault == NoFault) { 2914027Sstever@eecs.umich.edu %(memacc_code)s; 2924027Sstever@eecs.umich.edu } 2934027Sstever@eecs.umich.edu 2944027Sstever@eecs.umich.edu if (fault == NoFault) { 2954027Sstever@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2964027Sstever@eecs.umich.edu memAccessFlags, NULL); 2974027Sstever@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 2984027Sstever@eecs.umich.edu } 2994027Sstever@eecs.umich.edu 3004027Sstever@eecs.umich.edu if (fault == NoFault) { 3014027Sstever@eecs.umich.edu %(postacc_code)s; 3024027Sstever@eecs.umich.edu } 3034027Sstever@eecs.umich.edu 3044027Sstever@eecs.umich.edu if (fault == NoFault) { 3054027Sstever@eecs.umich.edu %(op_wb)s; 3064027Sstever@eecs.umich.edu } 3074027Sstever@eecs.umich.edu 3084027Sstever@eecs.umich.edu return fault; 3094027Sstever@eecs.umich.edu } 3104027Sstever@eecs.umich.edu}}; 3114027Sstever@eecs.umich.edu 3124027Sstever@eecs.umich.edudef template StoreCondExecute {{ 3134027Sstever@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3144027Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 3154027Sstever@eecs.umich.edu { 3164027Sstever@eecs.umich.edu Addr EA; 3174027Sstever@eecs.umich.edu Fault fault = NoFault; 3182069SN/A uint64_t write_result = 0; 3192069SN/A 3202069SN/A %(fp_enable_check)s; 3212069SN/A %(op_decl)s; 3222069SN/A %(op_rd)s; 3232069SN/A %(ea_code)s; 3242069SN/A 3252090SN/A if (fault == NoFault) { 3262069SN/A %(memacc_code)s; 3272069SN/A } 3282069SN/A 3292090SN/A if (fault == NoFault) { 3302069SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3312069SN/A memAccessFlags, &write_result); 3322069SN/A if (traceData) { traceData->setData(Mem); } 3332069SN/A } 3342069SN/A 3352090SN/A if (fault == NoFault) { 3362069SN/A %(postacc_code)s; 3372069SN/A } 3382069SN/A 3392090SN/A if (fault == NoFault) { 3402069SN/A %(op_wb)s; 3412069SN/A } 3422069SN/A 3432069SN/A return fault; 3442069SN/A } 3452069SN/A}}; 3462069SN/A 3472095SN/Adef template StoreInitiateAcc {{ 3482132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3492095SN/A Trace::InstRecord *traceData) const 3502095SN/A { 3512095SN/A Addr EA; 3522132SN/A Fault fault = NoFault; 3532095SN/A 3542095SN/A %(fp_enable_check)s; 3552506SN/A %(op_decl)s; 3562095SN/A %(op_rd)s; 3572095SN/A %(ea_code)s; 3582095SN/A 3592098SN/A if (fault == NoFault) { 3602095SN/A %(memacc_code)s; 3612095SN/A } 3622095SN/A 3632098SN/A if (fault == NoFault) { 3642095SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3652623SN/A memAccessFlags, NULL); 3662095SN/A if (traceData) { traceData->setData(Mem); } 3672095SN/A } 3682095SN/A 3692095SN/A return fault; 3702095SN/A } 3712095SN/A}}; 3722095SN/A 3732095SN/A 3742095SN/Adef template StoreCompleteAcc {{ 3753349Sbinkertn@umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 3762095SN/A %(CPU_exec_context)s *xc, 3772095SN/A Trace::InstRecord *traceData) const 3782095SN/A { 3792132SN/A Fault fault = NoFault; 3802095SN/A 3812095SN/A %(fp_enable_check)s; 3822095SN/A %(op_dest_decl)s; 3832095SN/A 3842623SN/A if (fault == NoFault) { 3852623SN/A %(postacc_code)s; 3862623SN/A } 3872623SN/A 3882623SN/A if (fault == NoFault) { 3892623SN/A %(op_wb)s; 3902623SN/A } 3912623SN/A 3922623SN/A return fault; 3932623SN/A } 3942623SN/A}}; 3952623SN/A 3962623SN/A 3972623SN/Adef template StoreCondCompleteAcc {{ 3983349Sbinkertn@umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 3992623SN/A %(CPU_exec_context)s *xc, 4002623SN/A Trace::InstRecord *traceData) const 4012623SN/A { 4022623SN/A Fault fault = NoFault; 4032623SN/A 4042623SN/A %(fp_enable_check)s; 4052623SN/A %(op_dest_decl)s; 4062623SN/A 4074040Ssaidi@eecs.umich.edu uint64_t write_result = pkt->req->getExtraData(); 4082095SN/A 4092098SN/A if (fault == NoFault) { 4102095SN/A %(postacc_code)s; 4112095SN/A } 4122095SN/A 4132098SN/A if (fault == NoFault) { 4142095SN/A %(op_wb)s; 4152095SN/A } 4162095SN/A 4172095SN/A return fault; 4182095SN/A } 4192095SN/A}}; 4202095SN/A 4212069SN/A 4222069SN/Adef template MiscExecute {{ 4232132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 4242068SN/A Trace::InstRecord *traceData) const 4252068SN/A { 4262068SN/A Addr EA; 4272132SN/A Fault fault = NoFault; 4282068SN/A 4292068SN/A %(fp_enable_check)s; 4302068SN/A %(op_decl)s; 4312069SN/A %(op_rd)s; 4322068SN/A %(ea_code)s; 4332068SN/A 4342090SN/A if (fault == NoFault) { 4352069SN/A %(memacc_code)s; 4362068SN/A } 4372068SN/A 4382090SN/A return NoFault; 4392068SN/A } 4402068SN/A}}; 4412068SN/A 4422095SN/Adef template MiscInitiateAcc {{ 4432132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4442095SN/A Trace::InstRecord *traceData) const 4452095SN/A { 4466185Sksewell@umich.edu warn("initiateAcc undefined: Misc instruction does not support split " 4476185Sksewell@umich.edu "access method!"); 4482098SN/A return NoFault; 4492095SN/A } 4502095SN/A}}; 4512095SN/A 4522095SN/A 4532095SN/Adef template MiscCompleteAcc {{ 4543349Sbinkertn@umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 4552095SN/A %(CPU_exec_context)s *xc, 4562095SN/A Trace::InstRecord *traceData) const 4572095SN/A { 4586185Sksewell@umich.edu warn("completeAcc undefined: Misc instruction does not support split " 4596185Sksewell@umich.edu "access method!"); 4602110SN/A 4612098SN/A return NoFault; 4622095SN/A } 4632095SN/A}}; 4642095SN/A 4656179Sksewell@umich.edudef template MiscMemAccSize {{ 4666179Sksewell@umich.edu int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc) 4676179Sksewell@umich.edu { 4686185Sksewell@umich.edu return (%(mem_acc_size)d / 8); 4696185Sksewell@umich.edu panic("memAccSize undefined: Misc instruction does not support split " 4706185Sksewell@umich.edu "access method!"); 4716179Sksewell@umich.edu return 0; 4726179Sksewell@umich.edu } 4736179Sksewell@umich.edu}}; 4746179Sksewell@umich.edu 4752068SN/A// load instructions use Ra as dest, so check for 4762068SN/A// Ra == 31 to detect nops 4772068SN/Adef template LoadNopCheckDecode {{ 4782068SN/A { 4792068SN/A AlphaStaticInst *i = new %(class_name)s(machInst); 4802068SN/A if (RA == 31) { 4812068SN/A i = makeNop(i); 4822068SN/A } 4832068SN/A return i; 4842068SN/A } 4852068SN/A}}; 4862068SN/A 4872068SN/A 4882068SN/A// for some load instructions, Ra == 31 indicates a prefetch (not a nop) 4892068SN/Adef template LoadPrefetchCheckDecode {{ 4902068SN/A { 4912068SN/A if (RA != 31) { 4922068SN/A return new %(class_name)s(machInst); 4932068SN/A } 4942068SN/A else { 4952068SN/A return new %(class_name)sPrefetch(machInst); 4962068SN/A } 4972068SN/A } 4982068SN/A}}; 4992068SN/A 5002068SN/A 5012068SN/Alet {{ 5022075SN/Adef LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5032075SN/A postacc_code = '', base_class = 'MemoryDisp32', 5042069SN/A decode_template = BasicDecode, exec_template_base = ''): 5052075SN/A # Make sure flags are in lists (convert to lists if not). 5062075SN/A mem_flags = makeList(mem_flags) 5072075SN/A inst_flags = makeList(inst_flags) 5082068SN/A 5092068SN/A # add hook to get effective addresses into execution trace output. 5102068SN/A ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' 5112068SN/A 5122068SN/A # Some CPU models execute the memory operation as an atomic unit, 5132068SN/A # while others want to separate them into an effective address 5142068SN/A # computation and a memory access operation. As a result, we need 5152068SN/A # to generate three StaticInst objects. Note that the latter two 5162068SN/A # are nested inside the larger "atomic" one. 5172068SN/A 5183953Sstever@eecs.umich.edu # Generate InstObjParams for each of the three objects. Note that 5193953Sstever@eecs.umich.edu # they differ only in the set of code objects contained (which in 5203953Sstever@eecs.umich.edu # turn affects the object's overall operand list). 5213953Sstever@eecs.umich.edu iop = InstObjParams(name, Name, base_class, 5223953Sstever@eecs.umich.edu { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 5233953Sstever@eecs.umich.edu inst_flags) 5243953Sstever@eecs.umich.edu memacc_iop = InstObjParams(name, Name, base_class, 5253953Sstever@eecs.umich.edu { 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 5263953Sstever@eecs.umich.edu inst_flags) 5272068SN/A 5282068SN/A if mem_flags: 5295736Snate@binkert.org mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] 5305745Snate@binkert.org s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 5312068SN/A iop.constructor += s 5322068SN/A memacc_iop.constructor += s 5332068SN/A 5342069SN/A # select templates 5352623SN/A 5364027Sstever@eecs.umich.edu # The InitiateAcc template is the same for StoreCond templates as the 5374027Sstever@eecs.umich.edu # corresponding Store template.. 5382623SN/A StoreCondInitiateAcc = StoreInitiateAcc 5392623SN/A 5402069SN/A fullExecTemplate = eval(exec_template_base + 'Execute') 5412095SN/A initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 5422095SN/A completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 5432069SN/A 5446179Sksewell@umich.edu if (exec_template_base == 'Load' or exec_template_base == 'Store'): 5456179Sksewell@umich.edu memAccSizeTemplate = eval('LoadStoreMemAccSize') 5466179Sksewell@umich.edu else: 5476179Sksewell@umich.edu memAccSizeTemplate = eval('MiscMemAccSize') 5486179Sksewell@umich.edu 5492068SN/A # (header_output, decoder_output, decode_block, exec_output) 5503953Sstever@eecs.umich.edu return (LoadStoreDeclare.subst(iop), 5516181Sksewell@umich.edu LoadStoreConstructor.subst(iop), 5522068SN/A decode_template.subst(iop), 5536181Sksewell@umich.edu fullExecTemplate.subst(iop) 5546181Sksewell@umich.edu + EACompExecute.subst(iop) 5553953Sstever@eecs.umich.edu + initiateAccTemplate.subst(iop) 5566179Sksewell@umich.edu + completeAccTemplate.subst(iop) 5576179Sksewell@umich.edu + memAccSizeTemplate.subst(memacc_iop)) 5582068SN/A}}; 5592068SN/A 5602075SN/Adef format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5612075SN/A mem_flags = [], inst_flags = []) {{ 5622068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5632075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5642069SN/A decode_template = LoadNopCheckDecode, 5652069SN/A exec_template_base = 'Load') 5662068SN/A}}; 5672068SN/A 5682068SN/A 5692068SN/A// Note that the flags passed in apply only to the prefetch version 5702075SN/Adef format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5712075SN/A mem_flags = [], pf_flags = [], inst_flags = []) {{ 5722068SN/A # declare the load instruction object and generate the decode block 5732068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5742075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5752069SN/A decode_template = LoadPrefetchCheckDecode, 5762069SN/A exec_template_base = 'Load') 5772068SN/A 5782068SN/A # Declare the prefetch instruction object. 5792068SN/A 5802075SN/A # Make sure flag args are lists so we can mess with them. 5812075SN/A mem_flags = makeList(mem_flags) 5822075SN/A pf_flags = makeList(pf_flags) 5832075SN/A inst_flags = makeList(inst_flags) 5842075SN/A 5852075SN/A pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT'] 5862075SN/A pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', 5872075SN/A 'IsDataPrefetch', 'MemReadOp'] 5882068SN/A 5892068SN/A (pf_header_output, pf_decoder_output, _, pf_exec_output) = \ 5902069SN/A LoadStoreBase(name, Name + 'Prefetch', ea_code, 5912069SN/A 'xc->prefetch(EA, memAccessFlags);', 5922075SN/A pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5932068SN/A 5942068SN/A header_output += pf_header_output 5952068SN/A decoder_output += pf_decoder_output 5962068SN/A exec_output += pf_exec_output 5972068SN/A}}; 5982068SN/A 5992068SN/A 6002075SN/Adef format Store(memacc_code, ea_code = {{ EA = Rb + disp; }}, 6012075SN/A mem_flags = [], inst_flags = []) {{ 6022068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 6032075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 6042069SN/A exec_template_base = 'Store') 6052068SN/A}}; 6062068SN/A 6072068SN/A 6082075SN/Adef format StoreCond(memacc_code, postacc_code, 6092075SN/A ea_code = {{ EA = Rb + disp; }}, 6102075SN/A mem_flags = [], inst_flags = []) {{ 6112068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 6122075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 6132623SN/A postacc_code, exec_template_base = 'StoreCond') 6142068SN/A}}; 6152068SN/A 6162068SN/A 6172068SN/A// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb 6182075SN/Adef format MiscPrefetch(ea_code, memacc_code, 6192075SN/A mem_flags = [], inst_flags = []) {{ 6202068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 6212075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 6222069SN/A base_class = 'MemoryNoDisp', exec_template_base = 'Misc') 6232068SN/A}}; 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