mem.isa revision 2110
1720SN/A// -*- mode:c++ -*- 21762SN/A 3720SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 4720SN/A// All rights reserved. 5720SN/A// 6720SN/A// Redistribution and use in source and binary forms, with or without 7720SN/A// modification, are permitted provided that the following conditions are 8720SN/A// met: redistributions of source code must retain the above copyright 9720SN/A// notice, this list of conditions and the following disclaimer; 10720SN/A// redistributions in binary form must reproduce the above copyright 11720SN/A// notice, this list of conditions and the following disclaimer in the 12720SN/A// documentation and/or other materials provided with the distribution; 13720SN/A// neither the name of the copyright holders nor the names of its 14720SN/A// contributors may be used to endorse or promote products derived from 15720SN/A// this software without specific prior written permission. 16720SN/A// 17720SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18720SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19720SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20720SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21720SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22720SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23720SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24720SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25720SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26720SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.eduoutput header {{ 30720SN/A /** 31720SN/A * Base class for general Alpha memory-format instructions. 32720SN/A */ 33720SN/A class Memory : public AlphaStaticInst 34720SN/A { 351885SN/A protected: 361885SN/A 37720SN/A /// Memory request flags. See mem_req_base.hh. 38720SN/A unsigned memAccessFlags; 39720SN/A /// Pointer to EAComp object. 40720SN/A const StaticInstPtr<AlphaISA> eaCompPtr; 41720SN/A /// Pointer to MemAcc object. 421885SN/A const StaticInstPtr<AlphaISA> memAccPtr; 431885SN/A 441885SN/A /// Constructor 45720SN/A Memory(const char *mnem, MachInst _machInst, OpClass __opClass, 46720SN/A StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr, 47720SN/A StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr) 48720SN/A : AlphaStaticInst(mnem, _machInst, __opClass), 49720SN/A memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr) 50720SN/A { 511885SN/A } 521885SN/A 53720SN/A std::string 54720SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 55720SN/A 56720SN/A public: 57720SN/A 581070SN/A const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; } 59720SN/A const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; } 60720SN/A }; 611070SN/A 621070SN/A /** 631070SN/A * Base class for memory-format instructions using a 32-bit 641885SN/A * displacement (i.e. most of them). 651885SN/A */ 661070SN/A class MemoryDisp32 : public Memory 671070SN/A { 681070SN/A protected: 691082SN/A /// Displacement for EA calculation (signed). 701082SN/A int32_t disp; 711082SN/A 721082SN/A /// Constructor. 731885SN/A MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass, 741885SN/A StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr, 751082SN/A StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr) 761082SN/A : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr), 771082SN/A disp(MEMDISP) 781082SN/A { 791082SN/A } 801082SN/A }; 811082SN/A 821885SN/A 831885SN/A /** 841082SN/A * Base class for a few miscellaneous memory-format insts 851082SN/A * that don't interpret the disp field: wh64, fetch, fetch_m, ecb. 861082SN/A * None of these instructions has a destination register either. 871082SN/A */ 881082SN/A class MemoryNoDisp : public Memory 89720SN/A { 90 protected: 91 /// Constructor 92 MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass, 93 StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr, 94 StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr) 95 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr) 96 { 97 } 98 99 std::string 100 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 101 }; 102}}; 103 104 105output decoder {{ 106 std::string 107 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 108 { 109 return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 110 flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB); 111 } 112 113 std::string 114 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 115 { 116 return csprintf("%-10s (r%d)", mnemonic, RB); 117 } 118}}; 119 120def format LoadAddress(code) {{ 121 iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code)) 122 header_output = BasicDeclare.subst(iop) 123 decoder_output = BasicConstructor.subst(iop) 124 decode_block = BasicDecode.subst(iop) 125 exec_output = BasicExecute.subst(iop) 126}}; 127 128 129def template LoadStoreDeclare {{ 130 /** 131 * Static instruction class for "%(mnemonic)s". 132 */ 133 class %(class_name)s : public %(base_class)s 134 { 135 protected: 136 137 /** 138 * "Fake" effective address computation class for "%(mnemonic)s". 139 */ 140 class EAComp : public %(base_class)s 141 { 142 public: 143 /// Constructor 144 EAComp(MachInst machInst); 145 146 %(BasicExecDeclare)s 147 }; 148 149 /** 150 * "Fake" memory access instruction class for "%(mnemonic)s". 151 */ 152 class MemAcc : public %(base_class)s 153 { 154 public: 155 /// Constructor 156 MemAcc(MachInst machInst); 157 158 %(BasicExecDeclare)s 159 }; 160 161 public: 162 163 /// Constructor. 164 %(class_name)s(MachInst machInst); 165 166 %(BasicExecDeclare)s 167 168 %(InitiateAccDeclare)s 169 170 %(CompleteAccDeclare)s 171 }; 172}}; 173 174 175def template InitiateAccDeclare {{ 176 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 177}}; 178 179 180def template CompleteAccDeclare {{ 181 Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 182}}; 183 184 185def template LoadStoreConstructor {{ 186 /** TODO: change op_class to AddrGenOp or something (requires 187 * creating new member of OpClass enum in op_class.hh, updating 188 * config files, etc.). */ 189 inline %(class_name)s::EAComp::EAComp(MachInst machInst) 190 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) 191 { 192 %(ea_constructor)s; 193 } 194 195 inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) 196 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) 197 { 198 %(memacc_constructor)s; 199 } 200 201 inline %(class_name)s::%(class_name)s(MachInst machInst) 202 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 203 new EAComp(machInst), new MemAcc(machInst)) 204 { 205 %(constructor)s; 206 } 207}}; 208 209 210def template EACompExecute {{ 211 Fault 212 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, 213 Trace::InstRecord *traceData) const 214 { 215 Addr EA; 216 Fault fault = No_Fault; 217 218 %(fp_enable_check)s; 219 %(op_decl)s; 220 %(op_rd)s; 221 %(code)s; 222 223 if (fault == No_Fault) { 224 %(op_wb)s; 225 xc->setEA(EA); 226 } 227 228 return fault; 229 } 230}}; 231 232def template LoadMemAccExecute {{ 233 Fault 234 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 235 Trace::InstRecord *traceData) const 236 { 237 Addr EA; 238 Fault fault = No_Fault; 239 240 %(fp_enable_check)s; 241 %(op_decl)s; 242 %(op_rd)s; 243 EA = xc->getEA(); 244 245 if (fault == No_Fault) { 246 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 247 %(code)s; 248 } 249 250 if (fault == No_Fault) { 251 %(op_wb)s; 252 } 253 254 return fault; 255 } 256}}; 257 258 259def template LoadExecute {{ 260 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 261 Trace::InstRecord *traceData) const 262 { 263 Addr EA; 264 Fault fault = No_Fault; 265 266 %(fp_enable_check)s; 267 %(op_decl)s; 268 %(op_rd)s; 269 %(ea_code)s; 270 271 if (fault == No_Fault) { 272 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 273 %(memacc_code)s; 274 } 275 276 if (fault == No_Fault) { 277 %(op_wb)s; 278 } 279 280 return fault; 281 } 282}}; 283 284 285def template LoadInitiateAcc {{ 286 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 287 Trace::InstRecord *traceData) const 288 { 289 Addr EA; 290 Fault fault = No_Fault; 291 292 %(fp_enable_check)s; 293 %(op_src_decl)s; 294 %(op_rd)s; 295 %(ea_code)s; 296 297 if (fault == No_Fault) { 298 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 299 } 300 301 return fault; 302 } 303}}; 304 305 306def template LoadCompleteAcc {{ 307 Fault %(class_name)s::completeAcc(uint8_t *data, 308 %(CPU_exec_context)s *xc, 309 Trace::InstRecord *traceData) const 310 { 311 Fault fault = No_Fault; 312 313 %(fp_enable_check)s; 314 %(op_src_decl)s; 315 %(op_dest_decl)s; 316 317 memcpy(&Mem, data, sizeof(Mem)); 318 319 if (fault == No_Fault) { 320 %(memacc_code)s; 321 } 322 323 if (fault == No_Fault) { 324 %(op_wb)s; 325 } 326 327 return fault; 328 } 329}}; 330 331 332def template StoreMemAccExecute {{ 333 Fault 334 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 335 Trace::InstRecord *traceData) const 336 { 337 Addr EA; 338 Fault fault = No_Fault; 339 uint64_t write_result = 0; 340 341 %(fp_enable_check)s; 342 %(op_decl)s; 343 %(op_rd)s; 344 EA = xc->getEA(); 345 346 if (fault == No_Fault) { 347 %(code)s; 348 } 349 350 if (fault == No_Fault) { 351 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 352 memAccessFlags, &write_result); 353 if (traceData) { traceData->setData(Mem); } 354 } 355 356 if (fault == No_Fault) { 357 %(postacc_code)s; 358 } 359 360 if (fault == No_Fault) { 361 %(op_wb)s; 362 } 363 364 return fault; 365 } 366}}; 367 368 369def template StoreExecute {{ 370 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 371 Trace::InstRecord *traceData) const 372 { 373 Addr EA; 374 Fault fault = No_Fault; 375 uint64_t write_result = 0; 376 377 %(fp_enable_check)s; 378 %(op_decl)s; 379 %(op_rd)s; 380 %(ea_code)s; 381 382 if (fault == No_Fault) { 383 %(memacc_code)s; 384 } 385 386 if (fault == No_Fault) { 387 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 388 memAccessFlags, &write_result); 389 if (traceData) { traceData->setData(Mem); } 390 } 391 392 if (fault == No_Fault) { 393 %(postacc_code)s; 394 } 395 396 if (fault == No_Fault) { 397 %(op_wb)s; 398 } 399 400 return fault; 401 } 402}}; 403 404def template StoreInitiateAcc {{ 405 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 406 Trace::InstRecord *traceData) const 407 { 408 Addr EA; 409 Fault fault = No_Fault; 410 uint64_t write_result = 0; 411 412 %(fp_enable_check)s; 413 %(op_src_decl)s; 414 %(op_dest_decl)s; 415 %(op_rd)s; 416 %(ea_code)s; 417 418 if (fault == No_Fault) { 419 %(memacc_code)s; 420 } 421 422 if (fault == No_Fault) { 423 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 424 memAccessFlags, &write_result); 425 if (traceData) { traceData->setData(Mem); } 426 } 427 428 return fault; 429 } 430}}; 431 432 433def template StoreCompleteAcc {{ 434 Fault %(class_name)s::completeAcc(uint8_t *data, 435 %(CPU_exec_context)s *xc, 436 Trace::InstRecord *traceData) const 437 { 438 Fault fault = No_Fault; 439 uint64_t write_result = 0; 440 441 %(fp_enable_check)s; 442 %(op_dest_decl)s; 443 444 memcpy(&write_result, data, sizeof(write_result)); 445 446 if (fault == No_Fault) { 447 %(postacc_code)s; 448 } 449 450 if (fault == No_Fault) { 451 %(op_wb)s; 452 } 453 454 return fault; 455 } 456}}; 457 458 459def template MiscMemAccExecute {{ 460 Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 461 Trace::InstRecord *traceData) const 462 { 463 Addr EA; 464 Fault fault = No_Fault; 465 466 %(fp_enable_check)s; 467 %(op_decl)s; 468 %(op_rd)s; 469 EA = xc->getEA(); 470 471 if (fault == No_Fault) { 472 %(code)s; 473 } 474 475 return No_Fault; 476 } 477}}; 478 479def template MiscExecute {{ 480 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 481 Trace::InstRecord *traceData) const 482 { 483 Addr EA; 484 Fault fault = No_Fault; 485 486 %(fp_enable_check)s; 487 %(op_decl)s; 488 %(op_rd)s; 489 %(ea_code)s; 490 491 if (fault == No_Fault) { 492 %(memacc_code)s; 493 } 494 495 return No_Fault; 496 } 497}}; 498 499def template MiscInitiateAcc {{ 500 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 501 Trace::InstRecord *traceData) const 502 { 503 panic("Misc instruction does not support split access method!"); 504 505 return No_Fault; 506 } 507}}; 508 509 510def template MiscCompleteAcc {{ 511 Fault %(class_name)s::completeAcc(uint8_t *data, 512 %(CPU_exec_context)s *xc, 513 Trace::InstRecord *traceData) const 514 { 515 panic("Misc instruction does not support split access method!"); 516 517 return No_Fault; 518 } 519}}; 520 521// load instructions use Ra as dest, so check for 522// Ra == 31 to detect nops 523def template LoadNopCheckDecode {{ 524 { 525 AlphaStaticInst *i = new %(class_name)s(machInst); 526 if (RA == 31) { 527 i = makeNop(i); 528 } 529 return i; 530 } 531}}; 532 533 534// for some load instructions, Ra == 31 indicates a prefetch (not a nop) 535def template LoadPrefetchCheckDecode {{ 536 { 537 if (RA != 31) { 538 return new %(class_name)s(machInst); 539 } 540 else { 541 return new %(class_name)sPrefetch(machInst); 542 } 543 } 544}}; 545 546 547let {{ 548def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 549 postacc_code = '', base_class = 'MemoryDisp32', 550 decode_template = BasicDecode, exec_template_base = ''): 551 # Make sure flags are in lists (convert to lists if not). 552 mem_flags = makeList(mem_flags) 553 inst_flags = makeList(inst_flags) 554 555 # add hook to get effective addresses into execution trace output. 556 ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' 557 558 # generate code block objects 559 ea_cblk = CodeBlock(ea_code) 560 memacc_cblk = CodeBlock(memacc_code) 561 postacc_cblk = CodeBlock(postacc_code) 562 563 # Some CPU models execute the memory operation as an atomic unit, 564 # while others want to separate them into an effective address 565 # computation and a memory access operation. As a result, we need 566 # to generate three StaticInst objects. Note that the latter two 567 # are nested inside the larger "atomic" one. 568 569 # generate InstObjParams for EAComp object 570 ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags) 571 572 # generate InstObjParams for MemAcc object 573 memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags) 574 # in the split execution model, the MemAcc portion is responsible 575 # for the post-access code. 576 memacc_iop.postacc_code = postacc_cblk.code 577 578 # generate InstObjParams for InitiateAcc, CompleteAcc object 579 # The code used depends on the template being used 580 if (exec_template_base == 'Load'): 581 initiateacc_cblk = CodeBlock(ea_code + memacc_code) 582 completeacc_cblk = CodeBlock(memacc_code + postacc_code) 583 elif (exec_template_base == 'Store'): 584 initiateacc_cblk = CodeBlock(ea_code + memacc_code) 585 completeacc_cblk = CodeBlock(postacc_code) 586 else: 587 initiateacc_cblk = '' 588 completeacc_cblk = '' 589 590 initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk, 591 inst_flags) 592 593 completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk, 594 inst_flags) 595 596 if (exec_template_base == 'Load'): 597 initiateacc_iop.ea_code = ea_cblk.code 598 initiateacc_iop.memacc_code = memacc_cblk.code 599 completeacc_iop.memacc_code = memacc_cblk.code 600 completeacc_iop.postacc_code = postacc_cblk.code 601 elif (exec_template_base == 'Store'): 602 initiateacc_iop.ea_code = ea_cblk.code 603 initiateacc_iop.memacc_code = memacc_cblk.code 604 completeacc_iop.postacc_code = postacc_cblk.code 605 606 # generate InstObjParams for unified execution 607 cblk = CodeBlock(ea_code + memacc_code + postacc_code) 608 iop = InstObjParams(name, Name, base_class, cblk, inst_flags) 609 610 iop.ea_constructor = ea_cblk.constructor 611 iop.ea_code = ea_cblk.code 612 iop.memacc_constructor = memacc_cblk.constructor 613 iop.memacc_code = memacc_cblk.code 614 iop.postacc_code = postacc_cblk.code 615 616 if mem_flags: 617 s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 618 iop.constructor += s 619 memacc_iop.constructor += s 620 621 # select templates 622 memAccExecTemplate = eval(exec_template_base + 'MemAccExecute') 623 fullExecTemplate = eval(exec_template_base + 'Execute') 624 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 625 completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 626 627 # (header_output, decoder_output, decode_block, exec_output) 628 return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop), 629 decode_template.subst(iop), 630 EACompExecute.subst(ea_iop) 631 + memAccExecTemplate.subst(memacc_iop) 632 + fullExecTemplate.subst(iop) 633 + initiateAccTemplate.subst(initiateacc_iop) 634 + completeAccTemplate.subst(completeacc_iop)) 635}}; 636 637 638def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }}, 639 mem_flags = [], inst_flags = []) {{ 640 (header_output, decoder_output, decode_block, exec_output) = \ 641 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 642 decode_template = LoadNopCheckDecode, 643 exec_template_base = 'Load') 644}}; 645 646 647// Note that the flags passed in apply only to the prefetch version 648def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }}, 649 mem_flags = [], pf_flags = [], inst_flags = []) {{ 650 # declare the load instruction object and generate the decode block 651 (header_output, decoder_output, decode_block, exec_output) = \ 652 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 653 decode_template = LoadPrefetchCheckDecode, 654 exec_template_base = 'Load') 655 656 # Declare the prefetch instruction object. 657 658 # Make sure flag args are lists so we can mess with them. 659 mem_flags = makeList(mem_flags) 660 pf_flags = makeList(pf_flags) 661 inst_flags = makeList(inst_flags) 662 663 pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT'] 664 pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', 665 'IsDataPrefetch', 'MemReadOp'] 666 667 (pf_header_output, pf_decoder_output, _, pf_exec_output) = \ 668 LoadStoreBase(name, Name + 'Prefetch', ea_code, 669 'xc->prefetch(EA, memAccessFlags);', 670 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 671 672 header_output += pf_header_output 673 decoder_output += pf_decoder_output 674 exec_output += pf_exec_output 675}}; 676 677 678def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }}, 679 mem_flags = [], inst_flags = []) {{ 680 (header_output, decoder_output, decode_block, exec_output) = \ 681 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 682 exec_template_base = 'Store') 683}}; 684 685 686def format StoreCond(memacc_code, postacc_code, 687 ea_code = {{ EA = Rb + disp; }}, 688 mem_flags = [], inst_flags = []) {{ 689 (header_output, decoder_output, decode_block, exec_output) = \ 690 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 691 postacc_code, exec_template_base = 'Store') 692}}; 693 694 695// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb 696def format MiscPrefetch(ea_code, memacc_code, 697 mem_flags = [], inst_flags = []) {{ 698 (header_output, decoder_output, decode_block, exec_output) = \ 699 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 700 base_class = 'MemoryNoDisp', exec_template_base = 'Misc') 701}}; 702 703 704