mem.isa revision 2090
17639Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27639Sgblack@eecs.umich.edu 310829Sandreas.hansson@arm.com// Copyright (c) 2003-2005 The Regents of The University of Michigan 47639Sgblack@eecs.umich.edu// All rights reserved. 57639Sgblack@eecs.umich.edu// 67639Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 77639Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 87639Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 97639Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 107639Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 117639Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 127639Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 137639Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 147639Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 157639Sgblack@eecs.umich.edu// this software without specific prior written permission. 167639Sgblack@eecs.umich.edu// 177639Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 187639Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 197639Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 207639Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 217639Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 227639Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 237639Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 247639Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 257639Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 267639Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 277639Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 287639Sgblack@eecs.umich.edu 297639Sgblack@eecs.umich.eduoutput header {{ 307639Sgblack@eecs.umich.edu /** 317639Sgblack@eecs.umich.edu * Base class for general Alpha memory-format instructions. 327639Sgblack@eecs.umich.edu */ 337639Sgblack@eecs.umich.edu class Memory : public AlphaStaticInst 347639Sgblack@eecs.umich.edu { 357639Sgblack@eecs.umich.edu protected: 367639Sgblack@eecs.umich.edu 377639Sgblack@eecs.umich.edu /// Memory request flags. See mem_req_base.hh. 387639Sgblack@eecs.umich.edu unsigned memAccessFlags; 397639Sgblack@eecs.umich.edu /// Pointer to EAComp object. 407639Sgblack@eecs.umich.edu const StaticInstPtr<AlphaISA> eaCompPtr; 417639Sgblack@eecs.umich.edu /// Pointer to MemAcc object. 427639Sgblack@eecs.umich.edu const StaticInstPtr<AlphaISA> memAccPtr; 437639Sgblack@eecs.umich.edu 447639Sgblack@eecs.umich.edu /// Constructor 457639Sgblack@eecs.umich.edu Memory(const char *mnem, MachInst _machInst, OpClass __opClass, 467639Sgblack@eecs.umich.edu StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr, 477639Sgblack@eecs.umich.edu StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr) 487639Sgblack@eecs.umich.edu : AlphaStaticInst(mnem, _machInst, __opClass), 497639Sgblack@eecs.umich.edu memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr) 507639Sgblack@eecs.umich.edu { 517639Sgblack@eecs.umich.edu } 527639Sgblack@eecs.umich.edu 537639Sgblack@eecs.umich.edu std::string 547639Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 557639Sgblack@eecs.umich.edu 567639Sgblack@eecs.umich.edu public: 577639Sgblack@eecs.umich.edu 587639Sgblack@eecs.umich.edu const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; } 597639Sgblack@eecs.umich.edu const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; } 607639Sgblack@eecs.umich.edu }; 617639Sgblack@eecs.umich.edu 627639Sgblack@eecs.umich.edu /** 637639Sgblack@eecs.umich.edu * Base class for memory-format instructions using a 32-bit 647639Sgblack@eecs.umich.edu * displacement (i.e. most of them). 657639Sgblack@eecs.umich.edu */ 667639Sgblack@eecs.umich.edu class MemoryDisp32 : public Memory 677639Sgblack@eecs.umich.edu { 687639Sgblack@eecs.umich.edu protected: 697639Sgblack@eecs.umich.edu /// Displacement for EA calculation (signed). 707639Sgblack@eecs.umich.edu int32_t disp; 717639Sgblack@eecs.umich.edu 727639Sgblack@eecs.umich.edu /// Constructor. 737639Sgblack@eecs.umich.edu MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass, 747639Sgblack@eecs.umich.edu StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr, 757639Sgblack@eecs.umich.edu StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr) 767639Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr), 777639Sgblack@eecs.umich.edu disp(MEMDISP) 787639Sgblack@eecs.umich.edu { 797639Sgblack@eecs.umich.edu } 807639Sgblack@eecs.umich.edu }; 817639Sgblack@eecs.umich.edu 827639Sgblack@eecs.umich.edu 837639Sgblack@eecs.umich.edu /** 847639Sgblack@eecs.umich.edu * Base class for a few miscellaneous memory-format insts 857639Sgblack@eecs.umich.edu * that don't interpret the disp field: wh64, fetch, fetch_m, ecb. 867639Sgblack@eecs.umich.edu * None of these instructions has a destination register either. 877639Sgblack@eecs.umich.edu */ 887639Sgblack@eecs.umich.edu class MemoryNoDisp : public Memory 897639Sgblack@eecs.umich.edu { 907639Sgblack@eecs.umich.edu protected: 917639Sgblack@eecs.umich.edu /// Constructor 927639Sgblack@eecs.umich.edu MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass, 937639Sgblack@eecs.umich.edu StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr, 947639Sgblack@eecs.umich.edu StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr) 957639Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr) 967639Sgblack@eecs.umich.edu { 9710037SARM gem5 Developers } 9810037SARM gem5 Developers 997639Sgblack@eecs.umich.edu std::string 1007639Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1017639Sgblack@eecs.umich.edu }; 1027639Sgblack@eecs.umich.edu}}; 1037639Sgblack@eecs.umich.edu 1047639Sgblack@eecs.umich.edu 1057639Sgblack@eecs.umich.eduoutput decoder {{ 1067639Sgblack@eecs.umich.edu std::string 1077639Sgblack@eecs.umich.edu Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1087639Sgblack@eecs.umich.edu { 1097639Sgblack@eecs.umich.edu return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 1107639Sgblack@eecs.umich.edu flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB); 1117639Sgblack@eecs.umich.edu } 1127639Sgblack@eecs.umich.edu 1137639Sgblack@eecs.umich.edu std::string 1147639Sgblack@eecs.umich.edu MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 11510037SARM gem5 Developers { 11610037SARM gem5 Developers return csprintf("%-10s (r%d)", mnemonic, RB); 1177639Sgblack@eecs.umich.edu } 1187639Sgblack@eecs.umich.edu}}; 1197639Sgblack@eecs.umich.edu 1207639Sgblack@eecs.umich.edudef format LoadAddress(code) {{ 1217639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code)) 1227639Sgblack@eecs.umich.edu header_output = BasicDeclare.subst(iop) 1237639Sgblack@eecs.umich.edu decoder_output = BasicConstructor.subst(iop) 1247639Sgblack@eecs.umich.edu decode_block = BasicDecode.subst(iop) 1257639Sgblack@eecs.umich.edu exec_output = BasicExecute.subst(iop) 1267639Sgblack@eecs.umich.edu}}; 1277639Sgblack@eecs.umich.edu 1287639Sgblack@eecs.umich.edu 1297639Sgblack@eecs.umich.edudef template LoadStoreDeclare {{ 1307639Sgblack@eecs.umich.edu /** 1317639Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 13210037SARM gem5 Developers */ 13310037SARM gem5 Developers class %(class_name)s : public %(base_class)s 13410037SARM gem5 Developers { 13510037SARM gem5 Developers protected: 13610037SARM gem5 Developers 13710037SARM gem5 Developers /** 13810037SARM gem5 Developers * "Fake" effective address computation class for "%(mnemonic)s". 13910037SARM gem5 Developers */ 14010037SARM gem5 Developers class EAComp : public %(base_class)s 14110037SARM gem5 Developers { 14210037SARM gem5 Developers public: 14310037SARM gem5 Developers /// Constructor 14410037SARM gem5 Developers EAComp(MachInst machInst); 14510037SARM gem5 Developers 14610037SARM gem5 Developers %(BasicExecDeclare)s 14710037SARM gem5 Developers }; 14810037SARM gem5 Developers 14910037SARM gem5 Developers /** 15010037SARM gem5 Developers * "Fake" memory access instruction class for "%(mnemonic)s". 15110037SARM gem5 Developers */ 15210037SARM gem5 Developers class MemAcc : public %(base_class)s 15310037SARM gem5 Developers { 15410037SARM gem5 Developers public: 15510037SARM gem5 Developers /// Constructor 15610037SARM gem5 Developers MemAcc(MachInst machInst); 15710037SARM gem5 Developers 15810037SARM gem5 Developers %(BasicExecDeclare)s 15910037SARM gem5 Developers }; 16010037SARM gem5 Developers 16110037SARM gem5 Developers public: 16210037SARM gem5 Developers 16310037SARM gem5 Developers /// Constructor. 1647639Sgblack@eecs.umich.edu %(class_name)s(MachInst machInst); 1657639Sgblack@eecs.umich.edu 1667639Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1677639Sgblack@eecs.umich.edu }; 1687639Sgblack@eecs.umich.edu}}; 1697639Sgblack@eecs.umich.edu 1707639Sgblack@eecs.umich.edudef template LoadStoreConstructor {{ 1717639Sgblack@eecs.umich.edu /** TODO: change op_class to AddrGenOp or something (requires 1727639Sgblack@eecs.umich.edu * creating new member of OpClass enum in op_class.hh, updating 1737639Sgblack@eecs.umich.edu * config files, etc.). */ 1747639Sgblack@eecs.umich.edu inline %(class_name)s::EAComp::EAComp(MachInst machInst) 1757639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) 1767639Sgblack@eecs.umich.edu { 1777639Sgblack@eecs.umich.edu %(ea_constructor)s; 1787639Sgblack@eecs.umich.edu } 1797639Sgblack@eecs.umich.edu 1807639Sgblack@eecs.umich.edu inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) 1817639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) 1827639Sgblack@eecs.umich.edu { 1837639Sgblack@eecs.umich.edu %(memacc_constructor)s; 1847639Sgblack@eecs.umich.edu } 1857639Sgblack@eecs.umich.edu 1867639Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s(MachInst machInst) 1877639Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1887639Sgblack@eecs.umich.edu new EAComp(machInst), new MemAcc(machInst)) 1897639Sgblack@eecs.umich.edu { 1907639Sgblack@eecs.umich.edu %(constructor)s; 1917639Sgblack@eecs.umich.edu } 1927639Sgblack@eecs.umich.edu}}; 1937639Sgblack@eecs.umich.edu 1947639Sgblack@eecs.umich.edu 1957639Sgblack@eecs.umich.edudef template EACompExecute {{ 1967639Sgblack@eecs.umich.edu Fault * 1977639Sgblack@eecs.umich.edu %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, 1987639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1997639Sgblack@eecs.umich.edu { 2007639Sgblack@eecs.umich.edu Addr EA; 2017639Sgblack@eecs.umich.edu Fault * fault = NoFault; 2027639Sgblack@eecs.umich.edu 2037639Sgblack@eecs.umich.edu %(fp_enable_check)s; 2047639Sgblack@eecs.umich.edu %(op_decl)s; 2057639Sgblack@eecs.umich.edu %(op_rd)s; 2067639Sgblack@eecs.umich.edu %(code)s; 2077639Sgblack@eecs.umich.edu 2087639Sgblack@eecs.umich.edu if (fault == NoFault) { 2097639Sgblack@eecs.umich.edu %(op_wb)s; 2107639Sgblack@eecs.umich.edu xc->setEA(EA); 2117639Sgblack@eecs.umich.edu } 21210037SARM gem5 Developers 21310037SARM gem5 Developers return fault; 21410037SARM gem5 Developers } 21510037SARM gem5 Developers}}; 21610037SARM gem5 Developers 21710037SARM gem5 Developersdef template LoadMemAccExecute {{ 21810037SARM gem5 Developers Fault * 21910037SARM gem5 Developers %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 22010037SARM gem5 Developers Trace::InstRecord *traceData) const 22110037SARM gem5 Developers { 22210037SARM gem5 Developers Addr EA; 22310037SARM gem5 Developers Fault * fault = NoFault; 22410037SARM gem5 Developers 22510037SARM gem5 Developers %(fp_enable_check)s; 22610037SARM gem5 Developers %(op_decl)s; 22710037SARM gem5 Developers %(op_rd)s; 22810037SARM gem5 Developers EA = xc->getEA(); 22910037SARM gem5 Developers 23010037SARM gem5 Developers if (fault == NoFault) { 23110037SARM gem5 Developers fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 23210037SARM gem5 Developers %(code)s; 23310037SARM gem5 Developers } 23410037SARM gem5 Developers 23510037SARM gem5 Developers if (fault == NoFault) { 23610037SARM gem5 Developers %(op_wb)s; 23710037SARM gem5 Developers } 23810037SARM gem5 Developers 23910037SARM gem5 Developers return fault; 24010037SARM gem5 Developers } 24110037SARM gem5 Developers}}; 24210037SARM gem5 Developers 24310037SARM gem5 Developers 2447639Sgblack@eecs.umich.edudef template LoadExecute {{ 2457639Sgblack@eecs.umich.edu Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc, 2467639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2477639Sgblack@eecs.umich.edu { 2487639Sgblack@eecs.umich.edu Addr EA; 2497639Sgblack@eecs.umich.edu Fault * fault = NoFault; 2507639Sgblack@eecs.umich.edu 2517639Sgblack@eecs.umich.edu %(fp_enable_check)s; 2527639Sgblack@eecs.umich.edu %(op_decl)s; 2537639Sgblack@eecs.umich.edu %(op_rd)s; 2547639Sgblack@eecs.umich.edu %(ea_code)s; 2557639Sgblack@eecs.umich.edu 2567639Sgblack@eecs.umich.edu if (fault == NoFault) { 2577639Sgblack@eecs.umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 2587639Sgblack@eecs.umich.edu %(memacc_code)s; 2597639Sgblack@eecs.umich.edu } 2607639Sgblack@eecs.umich.edu 2617639Sgblack@eecs.umich.edu if (fault == NoFault) { 2627639Sgblack@eecs.umich.edu %(op_wb)s; 2637639Sgblack@eecs.umich.edu } 2647639Sgblack@eecs.umich.edu 2657639Sgblack@eecs.umich.edu return fault; 2667639Sgblack@eecs.umich.edu } 2677639Sgblack@eecs.umich.edu}}; 2687639Sgblack@eecs.umich.edu 2697639Sgblack@eecs.umich.edu 2707639Sgblack@eecs.umich.edudef template StoreMemAccExecute {{ 2717639Sgblack@eecs.umich.edu Fault * 2727639Sgblack@eecs.umich.edu %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 2737639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2747639Sgblack@eecs.umich.edu { 2757639Sgblack@eecs.umich.edu Addr EA; 2767639Sgblack@eecs.umich.edu Fault * fault = NoFault; 2777639Sgblack@eecs.umich.edu uint64_t write_result = 0; 2787639Sgblack@eecs.umich.edu 2797639Sgblack@eecs.umich.edu %(fp_enable_check)s; 2807639Sgblack@eecs.umich.edu %(op_decl)s; 2817639Sgblack@eecs.umich.edu %(op_rd)s; 2827639Sgblack@eecs.umich.edu EA = xc->getEA(); 2837639Sgblack@eecs.umich.edu 2847639Sgblack@eecs.umich.edu if (fault == NoFault) { 2857639Sgblack@eecs.umich.edu %(code)s; 2867639Sgblack@eecs.umich.edu } 2877639Sgblack@eecs.umich.edu 2887639Sgblack@eecs.umich.edu if (fault == NoFault) { 2897639Sgblack@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 2907639Sgblack@eecs.umich.edu memAccessFlags, &write_result); 2917639Sgblack@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 2927639Sgblack@eecs.umich.edu } 2937639Sgblack@eecs.umich.edu 2947639Sgblack@eecs.umich.edu if (fault == NoFault) { 2957639Sgblack@eecs.umich.edu %(postacc_code)s; 2967639Sgblack@eecs.umich.edu } 2977639Sgblack@eecs.umich.edu 2987639Sgblack@eecs.umich.edu if (fault == NoFault) { 2997639Sgblack@eecs.umich.edu %(op_wb)s; 3007639Sgblack@eecs.umich.edu } 3017639Sgblack@eecs.umich.edu 3027639Sgblack@eecs.umich.edu return fault; 3037639Sgblack@eecs.umich.edu } 3047639Sgblack@eecs.umich.edu}}; 3057639Sgblack@eecs.umich.edu 3067639Sgblack@eecs.umich.edu 3077639Sgblack@eecs.umich.edudef template StoreExecute {{ 30810037SARM gem5 Developers Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc, 30910037SARM gem5 Developers Trace::InstRecord *traceData) const 31010037SARM gem5 Developers { 31110037SARM gem5 Developers Addr EA; 31210037SARM gem5 Developers Fault * fault = NoFault; 31310037SARM gem5 Developers uint64_t write_result = 0; 31410037SARM gem5 Developers 31510037SARM gem5 Developers %(fp_enable_check)s; 31610037SARM gem5 Developers %(op_decl)s; 31710037SARM gem5 Developers %(op_rd)s; 31810037SARM gem5 Developers %(ea_code)s; 31910037SARM gem5 Developers 32010037SARM gem5 Developers if (fault == NoFault) { 32110037SARM gem5 Developers %(memacc_code)s; 32210037SARM gem5 Developers } 32310037SARM gem5 Developers 32410037SARM gem5 Developers if (fault == NoFault) { 32510037SARM gem5 Developers fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 32610037SARM gem5 Developers memAccessFlags, &write_result); 32710037SARM gem5 Developers if (traceData) { traceData->setData(Mem); } 32810037SARM gem5 Developers } 32910037SARM gem5 Developers 33010037SARM gem5 Developers if (fault == NoFault) { 33110037SARM gem5 Developers %(postacc_code)s; 33210037SARM gem5 Developers } 33310037SARM gem5 Developers 33410037SARM gem5 Developers if (fault == NoFault) { 33510037SARM gem5 Developers %(op_wb)s; 33610037SARM gem5 Developers } 33710037SARM gem5 Developers 33810037SARM gem5 Developers return fault; 33910037SARM gem5 Developers } 34010037SARM gem5 Developers}}; 34110037SARM gem5 Developers 34210037SARM gem5 Developers 34310037SARM gem5 Developersdef template MiscMemAccExecute {{ 34410037SARM gem5 Developers Fault * %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 34510037SARM gem5 Developers Trace::InstRecord *traceData) const 34610037SARM gem5 Developers { 34710037SARM gem5 Developers Addr EA; 34810037SARM gem5 Developers Fault * fault = NoFault; 34910037SARM gem5 Developers 35010037SARM gem5 Developers %(fp_enable_check)s; 35110037SARM gem5 Developers %(op_decl)s; 35210037SARM gem5 Developers %(op_rd)s; 35310037SARM gem5 Developers EA = xc->getEA(); 35410037SARM gem5 Developers 35510037SARM gem5 Developers if (fault == NoFault) { 35610037SARM gem5 Developers %(code)s; 35710037SARM gem5 Developers } 35810037SARM gem5 Developers 35910037SARM gem5 Developers return NoFault; 36010037SARM gem5 Developers } 36110037SARM gem5 Developers}}; 36210037SARM gem5 Developers 36310037SARM gem5 Developersdef template MiscExecute {{ 36410037SARM gem5 Developers Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc, 36510037SARM gem5 Developers Trace::InstRecord *traceData) const 36610037SARM gem5 Developers { 36710037SARM gem5 Developers Addr EA; 36810037SARM gem5 Developers Fault * fault = NoFault; 36910037SARM gem5 Developers 37010037SARM gem5 Developers %(fp_enable_check)s; 37110037SARM gem5 Developers %(op_decl)s; 37210037SARM gem5 Developers %(op_rd)s; 37310037SARM gem5 Developers %(ea_code)s; 37410037SARM gem5 Developers 37510037SARM gem5 Developers if (fault == NoFault) { 37610037SARM gem5 Developers %(memacc_code)s; 37710037SARM gem5 Developers } 37810037SARM gem5 Developers 37910037SARM gem5 Developers return NoFault; 38010037SARM gem5 Developers } 38110037SARM gem5 Developers}}; 38210037SARM gem5 Developers 38310037SARM gem5 Developers// load instructions use Ra as dest, so check for 38410037SARM gem5 Developers// Ra == 31 to detect nops 38510037SARM gem5 Developersdef template LoadNopCheckDecode {{ 38610037SARM gem5 Developers { 38710037SARM gem5 Developers AlphaStaticInst *i = new %(class_name)s(machInst); 38810037SARM gem5 Developers if (RA == 31) { 38910037SARM gem5 Developers i = makeNop(i); 39010037SARM gem5 Developers } 39110037SARM gem5 Developers return i; 39210037SARM gem5 Developers } 39310037SARM gem5 Developers}}; 39410037SARM gem5 Developers 39510037SARM gem5 Developers 39610037SARM gem5 Developers// for some load instructions, Ra == 31 indicates a prefetch (not a nop) 39710037SARM gem5 Developersdef template LoadPrefetchCheckDecode {{ 39810037SARM gem5 Developers { 39910037SARM gem5 Developers if (RA != 31) { 40010037SARM gem5 Developers return new %(class_name)s(machInst); 40110037SARM gem5 Developers } 40210037SARM gem5 Developers else { 40310037SARM gem5 Developers return new %(class_name)sPrefetch(machInst); 40410037SARM gem5 Developers } 40510037SARM gem5 Developers } 40610037SARM gem5 Developers}}; 40710037SARM gem5 Developers 40810037SARM gem5 Developers 40910037SARM gem5 Developerslet {{ 41010037SARM gem5 Developersdef LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 41110037SARM gem5 Developers postacc_code = '', base_class = 'MemoryDisp32', 41210037SARM gem5 Developers decode_template = BasicDecode, exec_template_base = ''): 41310037SARM gem5 Developers # Make sure flags are in lists (convert to lists if not). 41410037SARM gem5 Developers mem_flags = makeList(mem_flags) 41510037SARM gem5 Developers inst_flags = makeList(inst_flags) 41610037SARM gem5 Developers 41710037SARM gem5 Developers # add hook to get effective addresses into execution trace output. 41810037SARM gem5 Developers ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' 41910037SARM gem5 Developers 42010037SARM gem5 Developers # generate code block objects 42110037SARM gem5 Developers ea_cblk = CodeBlock(ea_code) 42210037SARM gem5 Developers memacc_cblk = CodeBlock(memacc_code) 42310037SARM gem5 Developers postacc_cblk = CodeBlock(postacc_code) 42410037SARM gem5 Developers 42510037SARM gem5 Developers # Some CPU models execute the memory operation as an atomic unit, 4267639Sgblack@eecs.umich.edu # while others want to separate them into an effective address 4277639Sgblack@eecs.umich.edu # computation and a memory access operation. As a result, we need 4287639Sgblack@eecs.umich.edu # to generate three StaticInst objects. Note that the latter two 4297639Sgblack@eecs.umich.edu # are nested inside the larger "atomic" one. 4307639Sgblack@eecs.umich.edu 4317639Sgblack@eecs.umich.edu # generate InstObjParams for EAComp object 4327639Sgblack@eecs.umich.edu ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags) 4337639Sgblack@eecs.umich.edu 4347639Sgblack@eecs.umich.edu # generate InstObjParams for MemAcc object 4357639Sgblack@eecs.umich.edu memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags) 4367639Sgblack@eecs.umich.edu # in the split execution model, the MemAcc portion is responsible 4377639Sgblack@eecs.umich.edu # for the post-access code. 4387639Sgblack@eecs.umich.edu memacc_iop.postacc_code = postacc_cblk.code 4397639Sgblack@eecs.umich.edu 4407639Sgblack@eecs.umich.edu # generate InstObjParams for unified execution 4417639Sgblack@eecs.umich.edu cblk = CodeBlock(ea_code + memacc_code + postacc_code) 4427639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, base_class, cblk, inst_flags) 4437639Sgblack@eecs.umich.edu 4447639Sgblack@eecs.umich.edu iop.ea_constructor = ea_cblk.constructor 4457639Sgblack@eecs.umich.edu iop.ea_code = ea_cblk.code 4467639Sgblack@eecs.umich.edu iop.memacc_constructor = memacc_cblk.constructor 4477639Sgblack@eecs.umich.edu iop.memacc_code = memacc_cblk.code 4487639Sgblack@eecs.umich.edu iop.postacc_code = postacc_cblk.code 4497639Sgblack@eecs.umich.edu 4507639Sgblack@eecs.umich.edu if mem_flags: 4517639Sgblack@eecs.umich.edu s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 4527639Sgblack@eecs.umich.edu iop.constructor += s 4537639Sgblack@eecs.umich.edu memacc_iop.constructor += s 4547639Sgblack@eecs.umich.edu 4557639Sgblack@eecs.umich.edu # select templates 4567639Sgblack@eecs.umich.edu memAccExecTemplate = eval(exec_template_base + 'MemAccExecute') 4577639Sgblack@eecs.umich.edu fullExecTemplate = eval(exec_template_base + 'Execute') 4587639Sgblack@eecs.umich.edu 4597639Sgblack@eecs.umich.edu # (header_output, decoder_output, decode_block, exec_output) 4607639Sgblack@eecs.umich.edu return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop), 4617639Sgblack@eecs.umich.edu decode_template.subst(iop), 4627639Sgblack@eecs.umich.edu EACompExecute.subst(ea_iop) 4637639Sgblack@eecs.umich.edu + memAccExecTemplate.subst(memacc_iop) 4647639Sgblack@eecs.umich.edu + fullExecTemplate.subst(iop)) 4657639Sgblack@eecs.umich.edu}}; 4667639Sgblack@eecs.umich.edu 4677639Sgblack@eecs.umich.edu 4687639Sgblack@eecs.umich.edudef format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }}, 4697639Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 4707639Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 4717639Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4727639Sgblack@eecs.umich.edu decode_template = LoadNopCheckDecode, 4737639Sgblack@eecs.umich.edu exec_template_base = 'Load') 4747639Sgblack@eecs.umich.edu}}; 4757639Sgblack@eecs.umich.edu 4767639Sgblack@eecs.umich.edu 4777639Sgblack@eecs.umich.edu// Note that the flags passed in apply only to the prefetch version 4787639Sgblack@eecs.umich.edudef format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }}, 4797639Sgblack@eecs.umich.edu mem_flags = [], pf_flags = [], inst_flags = []) {{ 4807639Sgblack@eecs.umich.edu # declare the load instruction object and generate the decode block 4817639Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 4827639Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4837639Sgblack@eecs.umich.edu decode_template = LoadPrefetchCheckDecode, 4847639Sgblack@eecs.umich.edu exec_template_base = 'Load') 4857639Sgblack@eecs.umich.edu 4867639Sgblack@eecs.umich.edu # Declare the prefetch instruction object. 4877639Sgblack@eecs.umich.edu 4887639Sgblack@eecs.umich.edu # Make sure flag args are lists so we can mess with them. 4897639Sgblack@eecs.umich.edu mem_flags = makeList(mem_flags) 4907639Sgblack@eecs.umich.edu pf_flags = makeList(pf_flags) 4917639Sgblack@eecs.umich.edu inst_flags = makeList(inst_flags) 4927639Sgblack@eecs.umich.edu 4937639Sgblack@eecs.umich.edu pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT'] 4947639Sgblack@eecs.umich.edu pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', 4957639Sgblack@eecs.umich.edu 'IsDataPrefetch', 'MemReadOp'] 4967639Sgblack@eecs.umich.edu 4977639Sgblack@eecs.umich.edu (pf_header_output, pf_decoder_output, _, pf_exec_output) = \ 4987639Sgblack@eecs.umich.edu LoadStoreBase(name, Name + 'Prefetch', ea_code, 4997639Sgblack@eecs.umich.edu 'xc->prefetch(EA, memAccessFlags);', 5007639Sgblack@eecs.umich.edu pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5017639Sgblack@eecs.umich.edu 5027639Sgblack@eecs.umich.edu header_output += pf_header_output 5037639Sgblack@eecs.umich.edu decoder_output += pf_decoder_output 5047639Sgblack@eecs.umich.edu exec_output += pf_exec_output 5057639Sgblack@eecs.umich.edu}}; 5067639Sgblack@eecs.umich.edu 5077639Sgblack@eecs.umich.edu 5087639Sgblack@eecs.umich.edudef format Store(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5097639Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 5107639Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5117639Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5127639Sgblack@eecs.umich.edu exec_template_base = 'Store') 5137639Sgblack@eecs.umich.edu}}; 5147639Sgblack@eecs.umich.edu 5157639Sgblack@eecs.umich.edu 5167639Sgblack@eecs.umich.edudef format StoreCond(memacc_code, postacc_code, 5177639Sgblack@eecs.umich.edu ea_code = {{ EA = Rb + disp; }}, 5187639Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 5197639Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5207639Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5217639Sgblack@eecs.umich.edu postacc_code, exec_template_base = 'Store') 5227639Sgblack@eecs.umich.edu}}; 5237639Sgblack@eecs.umich.edu 5247639Sgblack@eecs.umich.edu 5257639Sgblack@eecs.umich.edu// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb 5267639Sgblack@eecs.umich.edudef format MiscPrefetch(ea_code, memacc_code, 5277639Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 5287639Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5297639Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 53010037SARM gem5 Developers base_class = 'MemoryNoDisp', exec_template_base = 'Misc') 53110037SARM gem5 Developers}}; 53210037SARM gem5 Developers 53310037SARM gem5 Developers 53410037SARM gem5 Developers