mem.isa revision 12234
12068SN/A// -*- mode:c++ -*- 22068SN/A 32068SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 42068SN/A// All rights reserved. 52068SN/A// 62068SN/A// Redistribution and use in source and binary forms, with or without 72068SN/A// modification, are permitted provided that the following conditions are 82068SN/A// met: redistributions of source code must retain the above copyright 92068SN/A// notice, this list of conditions and the following disclaimer; 102068SN/A// redistributions in binary form must reproduce the above copyright 112068SN/A// notice, this list of conditions and the following disclaimer in the 122068SN/A// documentation and/or other materials provided with the distribution; 132068SN/A// neither the name of the copyright holders nor the names of its 142068SN/A// contributors may be used to endorse or promote products derived from 152068SN/A// this software without specific prior written permission. 162068SN/A// 172068SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182068SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192068SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202068SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212068SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222068SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232068SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242068SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252068SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262068SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272068SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292665Ssaidi@eecs.umich.edu// Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu// Kevin Lim 312068SN/A 322649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 332649Ssaidi@eecs.umich.edu// 342649Ssaidi@eecs.umich.edu// Memory-format instructions: LoadAddress, Load, Store 352649Ssaidi@eecs.umich.edu// 362649Ssaidi@eecs.umich.edu 372068SN/Aoutput header {{ 382068SN/A /** 392068SN/A * Base class for general Alpha memory-format instructions. 402068SN/A */ 412068SN/A class Memory : public AlphaStaticInst 422068SN/A { 432068SN/A protected: 442068SN/A 452068SN/A /// Memory request flags. See mem_req_base.hh. 465736Snate@binkert.org Request::Flags memAccessFlags; 472068SN/A 482068SN/A /// Constructor 496181Sksewell@umich.edu Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 506181Sksewell@umich.edu : AlphaStaticInst(mnem, _machInst, __opClass) 512068SN/A { 522068SN/A } 532068SN/A 542068SN/A std::string 552068SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 562068SN/A }; 572068SN/A 582068SN/A /** 592068SN/A * Base class for memory-format instructions using a 32-bit 602068SN/A * displacement (i.e. most of them). 612068SN/A */ 622068SN/A class MemoryDisp32 : public Memory 632068SN/A { 642068SN/A protected: 652068SN/A /// Displacement for EA calculation (signed). 662068SN/A int32_t disp; 672068SN/A 682068SN/A /// Constructor. 696181Sksewell@umich.edu MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 706181Sksewell@umich.edu : Memory(mnem, _machInst, __opClass), 712068SN/A disp(MEMDISP) 722068SN/A { 732068SN/A } 742068SN/A }; 752068SN/A 762068SN/A 772068SN/A /** 782068SN/A * Base class for a few miscellaneous memory-format insts 792068SN/A * that don't interpret the disp field: wh64, fetch, fetch_m, ecb. 802068SN/A * None of these instructions has a destination register either. 812068SN/A */ 822068SN/A class MemoryNoDisp : public Memory 832068SN/A { 842068SN/A protected: 852068SN/A /// Constructor 866181Sksewell@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 876181Sksewell@umich.edu : Memory(mnem, _machInst, __opClass) 882068SN/A { 892068SN/A } 902068SN/A 912068SN/A std::string 922068SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 932068SN/A }; 942068SN/A}}; 952068SN/A 962068SN/A 972068SN/Aoutput decoder {{ 982068SN/A std::string 992068SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1002068SN/A { 1012068SN/A return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 1022068SN/A flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB); 1032068SN/A } 1042068SN/A 1052068SN/A std::string 1062068SN/A MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1072068SN/A { 1082068SN/A return csprintf("%-10s (r%d)", mnemonic, RB); 1092068SN/A } 1102068SN/A}}; 1112068SN/A 1122068SN/Adef format LoadAddress(code) {{ 1133953Sstever@eecs.umich.edu iop = InstObjParams(name, Name, 'MemoryDisp32', code) 1142068SN/A header_output = BasicDeclare.subst(iop) 1152068SN/A decoder_output = BasicConstructor.subst(iop) 1162068SN/A decode_block = BasicDecode.subst(iop) 1172068SN/A exec_output = BasicExecute.subst(iop) 1182068SN/A}}; 1192068SN/A 1202068SN/A 1212068SN/Adef template LoadStoreDeclare {{ 1222068SN/A /** 1232068SN/A * Static instruction class for "%(mnemonic)s". 1242068SN/A */ 1252068SN/A class %(class_name)s : public %(base_class)s 1262068SN/A { 1272068SN/A public: 1282068SN/A 1292068SN/A /// Constructor. 1302227SN/A %(class_name)s(ExtMachInst machInst); 1312068SN/A 1322068SN/A %(BasicExecDeclare)s 1332095SN/A 1346181Sksewell@umich.edu %(EACompDeclare)s 1356181Sksewell@umich.edu 1362095SN/A %(InitiateAccDeclare)s 1372095SN/A 1382095SN/A %(CompleteAccDeclare)s 1392068SN/A }; 1402068SN/A}}; 1412068SN/A 1422095SN/A 1436181Sksewell@umich.edudef template EACompDeclare {{ 14412234Sgabeblack@google.com Fault eaComp(ExecContext *, Trace::InstRecord *) const; 1456181Sksewell@umich.edu}}; 1466181Sksewell@umich.edu 1472095SN/Adef template InitiateAccDeclare {{ 14812234Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 1492095SN/A}}; 1502095SN/A 1512095SN/A 1522095SN/Adef template CompleteAccDeclare {{ 15312234Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; 1542095SN/A}}; 1552095SN/A 1566181Sksewell@umich.edudef template LoadStoreConstructor {{ 15710184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst) 1586181Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1592068SN/A { 1603953Sstever@eecs.umich.edu %(constructor)s; 1612068SN/A } 1623953Sstever@eecs.umich.edu}}; 1632068SN/A 1642068SN/Adef template EACompExecute {{ 16512234Sgabeblack@google.com Fault %(class_name)s::eaComp(ExecContext *xc, 16612234Sgabeblack@google.com Trace::InstRecord *traceData) const 1672068SN/A { 1682068SN/A Addr EA; 1692132SN/A Fault fault = NoFault; 1702068SN/A 1712068SN/A %(fp_enable_check)s; 1722068SN/A %(op_decl)s; 1732068SN/A %(op_rd)s; 1743953Sstever@eecs.umich.edu %(ea_code)s; 1752068SN/A 1762090SN/A if (fault == NoFault) { 1772068SN/A %(op_wb)s; 1782068SN/A xc->setEA(EA); 1792068SN/A } 1802068SN/A 1812068SN/A return fault; 1822068SN/A } 1832068SN/A}}; 1842068SN/A 1852068SN/A 1862069SN/Adef template LoadExecute {{ 18712234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 1882068SN/A Trace::InstRecord *traceData) const 1892068SN/A { 1902068SN/A Addr EA; 1912132SN/A Fault fault = NoFault; 1922068SN/A 1932068SN/A %(fp_enable_check)s; 1942068SN/A %(op_decl)s; 1952069SN/A %(op_rd)s; 1962068SN/A %(ea_code)s; 1972068SN/A 1982090SN/A if (fault == NoFault) { 1998442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 2002068SN/A %(memacc_code)s; 2012068SN/A } 2022068SN/A 2032090SN/A if (fault == NoFault) { 2042069SN/A %(op_wb)s; 2052069SN/A } 2062069SN/A 2072069SN/A return fault; 2082069SN/A } 2092069SN/A}}; 2102069SN/A 2112069SN/A 2122095SN/Adef template LoadInitiateAcc {{ 21312234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 2142095SN/A Trace::InstRecord *traceData) const 2152095SN/A { 2162095SN/A Addr EA; 2172132SN/A Fault fault = NoFault; 2182095SN/A 2192095SN/A %(fp_enable_check)s; 2202095SN/A %(op_src_decl)s; 2212095SN/A %(op_rd)s; 2222095SN/A %(ea_code)s; 2232095SN/A 2242098SN/A if (fault == NoFault) { 22511303Ssteve.reinhardt@amd.com fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags); 2262095SN/A } 2272095SN/A 2282095SN/A return fault; 2292095SN/A } 2302095SN/A}}; 2312095SN/A 2322095SN/A 2332095SN/Adef template LoadCompleteAcc {{ 23412234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 2352095SN/A Trace::InstRecord *traceData) const 2362095SN/A { 2372132SN/A Fault fault = NoFault; 2382095SN/A 2392095SN/A %(fp_enable_check)s; 2402506SN/A %(op_decl)s; 2412095SN/A 2428442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 2432095SN/A 2442098SN/A if (fault == NoFault) { 2452095SN/A %(memacc_code)s; 2462095SN/A } 2472095SN/A 2482098SN/A if (fault == NoFault) { 2492095SN/A %(op_wb)s; 2502095SN/A } 2512095SN/A 2522095SN/A return fault; 2532095SN/A } 2542095SN/A}}; 2552095SN/A 2562095SN/A 2572069SN/Adef template StoreExecute {{ 25812234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2592069SN/A Trace::InstRecord *traceData) const 2602069SN/A { 2612069SN/A Addr EA; 2622132SN/A Fault fault = NoFault; 2634027Sstever@eecs.umich.edu 2644027Sstever@eecs.umich.edu %(fp_enable_check)s; 2654027Sstever@eecs.umich.edu %(op_decl)s; 2664027Sstever@eecs.umich.edu %(op_rd)s; 2674027Sstever@eecs.umich.edu %(ea_code)s; 2684027Sstever@eecs.umich.edu 2694027Sstever@eecs.umich.edu if (fault == NoFault) { 2704027Sstever@eecs.umich.edu %(memacc_code)s; 2714027Sstever@eecs.umich.edu } 2724027Sstever@eecs.umich.edu 2734027Sstever@eecs.umich.edu if (fault == NoFault) { 2748442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, 2758442Sgblack@eecs.umich.edu memAccessFlags, NULL); 2764027Sstever@eecs.umich.edu } 2774027Sstever@eecs.umich.edu 2784027Sstever@eecs.umich.edu if (fault == NoFault) { 2794027Sstever@eecs.umich.edu %(postacc_code)s; 2804027Sstever@eecs.umich.edu } 2814027Sstever@eecs.umich.edu 2824027Sstever@eecs.umich.edu if (fault == NoFault) { 2834027Sstever@eecs.umich.edu %(op_wb)s; 2844027Sstever@eecs.umich.edu } 2854027Sstever@eecs.umich.edu 2864027Sstever@eecs.umich.edu return fault; 2874027Sstever@eecs.umich.edu } 2884027Sstever@eecs.umich.edu}}; 2894027Sstever@eecs.umich.edu 2904027Sstever@eecs.umich.edudef template StoreCondExecute {{ 29112234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2924027Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 2934027Sstever@eecs.umich.edu { 2944027Sstever@eecs.umich.edu Addr EA; 2954027Sstever@eecs.umich.edu Fault fault = NoFault; 2962069SN/A uint64_t write_result = 0; 2972069SN/A 2982069SN/A %(fp_enable_check)s; 2992069SN/A %(op_decl)s; 3002069SN/A %(op_rd)s; 3012069SN/A %(ea_code)s; 3022069SN/A 3032090SN/A if (fault == NoFault) { 3042069SN/A %(memacc_code)s; 3052069SN/A } 3062069SN/A 3072090SN/A if (fault == NoFault) { 3088442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, 3098442Sgblack@eecs.umich.edu memAccessFlags, &write_result); 3102069SN/A } 3112069SN/A 3122090SN/A if (fault == NoFault) { 3132069SN/A %(postacc_code)s; 3142069SN/A } 3152069SN/A 3162090SN/A if (fault == NoFault) { 3172069SN/A %(op_wb)s; 3182069SN/A } 3192069SN/A 3202069SN/A return fault; 3212069SN/A } 3222069SN/A}}; 3232069SN/A 3242095SN/Adef template StoreInitiateAcc {{ 32512234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 3262095SN/A Trace::InstRecord *traceData) const 3272095SN/A { 3282095SN/A Addr EA; 3292132SN/A Fault fault = NoFault; 3302095SN/A 3312095SN/A %(fp_enable_check)s; 3322506SN/A %(op_decl)s; 3332095SN/A %(op_rd)s; 3342095SN/A %(ea_code)s; 3352095SN/A 3362098SN/A if (fault == NoFault) { 3372095SN/A %(memacc_code)s; 3382095SN/A } 3392095SN/A 3402098SN/A if (fault == NoFault) { 3418442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, 3428442Sgblack@eecs.umich.edu memAccessFlags, NULL); 3432095SN/A } 3442095SN/A 3452095SN/A return fault; 3462095SN/A } 3472095SN/A}}; 3482095SN/A 3492095SN/A 3502095SN/Adef template StoreCompleteAcc {{ 35112234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 3522095SN/A Trace::InstRecord *traceData) const 3532095SN/A { 3547712Sgblack@eecs.umich.edu return NoFault; 3552623SN/A } 3562623SN/A}}; 3572623SN/A 3582623SN/A 3592623SN/Adef template StoreCondCompleteAcc {{ 36012234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 3612623SN/A Trace::InstRecord *traceData) const 3622623SN/A { 3632623SN/A Fault fault = NoFault; 3642623SN/A 3652623SN/A %(fp_enable_check)s; 3662623SN/A %(op_dest_decl)s; 3672623SN/A 3684040Ssaidi@eecs.umich.edu uint64_t write_result = pkt->req->getExtraData(); 3692095SN/A 3702098SN/A if (fault == NoFault) { 3712095SN/A %(postacc_code)s; 3722095SN/A } 3732095SN/A 3742098SN/A if (fault == NoFault) { 3752095SN/A %(op_wb)s; 3762095SN/A } 3772095SN/A 3782095SN/A return fault; 3792095SN/A } 3802095SN/A}}; 3812095SN/A 3822069SN/A 3832069SN/Adef template MiscExecute {{ 38412234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 3852068SN/A Trace::InstRecord *traceData) const 3862068SN/A { 3878607Sgblack@eecs.umich.edu Addr EA M5_VAR_USED; 3882132SN/A Fault fault = NoFault; 3892068SN/A 3902068SN/A %(fp_enable_check)s; 3912068SN/A %(op_decl)s; 3922069SN/A %(op_rd)s; 3932068SN/A %(ea_code)s; 3942068SN/A 3958406Sksewell@umich.edu warn_once("Prefetch instructions in Alpha do not do anything\n"); 3962090SN/A if (fault == NoFault) { 3972069SN/A %(memacc_code)s; 3982068SN/A } 3992068SN/A 4002090SN/A return NoFault; 4012068SN/A } 4022068SN/A}}; 4032068SN/A 4047725SAli.Saidi@ARM.com// Prefetches in Alpha don't actually do anything 4057725SAli.Saidi@ARM.com// They just build an effective address and complete 4062095SN/Adef template MiscInitiateAcc {{ 40712234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 4082095SN/A Trace::InstRecord *traceData) const 4092095SN/A { 4106185Sksewell@umich.edu warn("initiateAcc undefined: Misc instruction does not support split " 4116185Sksewell@umich.edu "access method!"); 4122098SN/A return NoFault; 4132095SN/A } 4142095SN/A}}; 4152095SN/A 4162095SN/A 4172095SN/Adef template MiscCompleteAcc {{ 41812234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 4192095SN/A Trace::InstRecord *traceData) const 4202095SN/A { 4216185Sksewell@umich.edu warn("completeAcc undefined: Misc instruction does not support split " 4226185Sksewell@umich.edu "access method!"); 4232110SN/A 4242098SN/A return NoFault; 4252095SN/A } 4262095SN/A}}; 4272095SN/A 4286179Sksewell@umich.edu 4292068SN/A// load instructions use Ra as dest, so check for 4302068SN/A// Ra == 31 to detect nops 4312068SN/Adef template LoadNopCheckDecode {{ 4322068SN/A { 4332068SN/A AlphaStaticInst *i = new %(class_name)s(machInst); 4342068SN/A if (RA == 31) { 4352068SN/A i = makeNop(i); 4362068SN/A } 4372068SN/A return i; 4382068SN/A } 4392068SN/A}}; 4402068SN/A 4412068SN/A 4422068SN/A// for some load instructions, Ra == 31 indicates a prefetch (not a nop) 4432068SN/Adef template LoadPrefetchCheckDecode {{ 4442068SN/A { 4452068SN/A if (RA != 31) { 4462068SN/A return new %(class_name)s(machInst); 4472068SN/A } 4482068SN/A else { 4492068SN/A return new %(class_name)sPrefetch(machInst); 4502068SN/A } 4512068SN/A } 4522068SN/A}}; 4532068SN/A 4542068SN/A 4552068SN/Alet {{ 4562075SN/Adef LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4572075SN/A postacc_code = '', base_class = 'MemoryDisp32', 4582069SN/A decode_template = BasicDecode, exec_template_base = ''): 4592075SN/A # Make sure flags are in lists (convert to lists if not). 4602075SN/A mem_flags = makeList(mem_flags) 4612075SN/A inst_flags = makeList(inst_flags) 4622068SN/A 4633953Sstever@eecs.umich.edu iop = InstObjParams(name, Name, base_class, 4643953Sstever@eecs.umich.edu { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 4653953Sstever@eecs.umich.edu inst_flags) 4662068SN/A 4672068SN/A if mem_flags: 4685736Snate@binkert.org mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] 4695745Snate@binkert.org s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 4702068SN/A iop.constructor += s 4712068SN/A 4722069SN/A # select templates 4732623SN/A 4744027Sstever@eecs.umich.edu # The InitiateAcc template is the same for StoreCond templates as the 4754027Sstever@eecs.umich.edu # corresponding Store template.. 4762623SN/A StoreCondInitiateAcc = StoreInitiateAcc 4772623SN/A 4782069SN/A fullExecTemplate = eval(exec_template_base + 'Execute') 4792095SN/A initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 4802095SN/A completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 4812069SN/A 4822068SN/A # (header_output, decoder_output, decode_block, exec_output) 4833953Sstever@eecs.umich.edu return (LoadStoreDeclare.subst(iop), 4846181Sksewell@umich.edu LoadStoreConstructor.subst(iop), 4852068SN/A decode_template.subst(iop), 4866181Sksewell@umich.edu fullExecTemplate.subst(iop) 4876181Sksewell@umich.edu + EACompExecute.subst(iop) 4883953Sstever@eecs.umich.edu + initiateAccTemplate.subst(iop) 4896192Sksewell@umich.edu + completeAccTemplate.subst(iop)) 4902068SN/A}}; 4912068SN/A 4922075SN/Adef format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }}, 4932075SN/A mem_flags = [], inst_flags = []) {{ 4942068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4952075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4962069SN/A decode_template = LoadNopCheckDecode, 4972069SN/A exec_template_base = 'Load') 4982068SN/A}}; 4992068SN/A 5002068SN/A 5012068SN/A// Note that the flags passed in apply only to the prefetch version 5022075SN/Adef format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5032075SN/A mem_flags = [], pf_flags = [], inst_flags = []) {{ 5042068SN/A # declare the load instruction object and generate the decode block 5052068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5062075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5072069SN/A decode_template = LoadPrefetchCheckDecode, 5082069SN/A exec_template_base = 'Load') 5092068SN/A 5102068SN/A # Declare the prefetch instruction object. 5112068SN/A 5122075SN/A # Make sure flag args are lists so we can mess with them. 5132075SN/A mem_flags = makeList(mem_flags) 5142075SN/A pf_flags = makeList(pf_flags) 5152075SN/A inst_flags = makeList(inst_flags) 5162075SN/A 5176739Sgblack@eecs.umich.edu pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 5187725SAli.Saidi@ARM.com pf_inst_flags = inst_flags 5192068SN/A 5202068SN/A (pf_header_output, pf_decoder_output, _, pf_exec_output) = \ 5217725SAli.Saidi@ARM.com LoadStoreBase(name, Name + 'Prefetch', ea_code, ';', 5222075SN/A pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5232068SN/A 5242068SN/A header_output += pf_header_output 5252068SN/A decoder_output += pf_decoder_output 5262068SN/A exec_output += pf_exec_output 5272068SN/A}}; 5282068SN/A 5292068SN/A 5302075SN/Adef format Store(memacc_code, ea_code = {{ EA = Rb + disp; }}, 5312075SN/A mem_flags = [], inst_flags = []) {{ 5322068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5332075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5342069SN/A exec_template_base = 'Store') 5352068SN/A}}; 5362068SN/A 5372068SN/A 5382075SN/Adef format StoreCond(memacc_code, postacc_code, 5392075SN/A ea_code = {{ EA = Rb + disp; }}, 5402075SN/A mem_flags = [], inst_flags = []) {{ 5412068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5422075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5432623SN/A postacc_code, exec_template_base = 'StoreCond') 5442068SN/A}}; 5452068SN/A 5462068SN/A 5472068SN/A// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb 5482075SN/Adef format MiscPrefetch(ea_code, memacc_code, 5492075SN/A mem_flags = [], inst_flags = []) {{ 5502068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5512075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5522069SN/A base_class = 'MemoryNoDisp', exec_template_base = 'Misc') 5532068SN/A}}; 5542068SN/A 5552068SN/A 556