main.isa revision 13903:d9aa8d18d6ff
1// -*- mode:c++ -*- 2 3// Copyright (c) 2003-2005 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// Alpha ISA description file. 34// 35//////////////////////////////////////////////////////////////////// 36 37 38//////////////////////////////////////////////////////////////////// 39// 40// Output include file directives. 41// 42 43output header {{ 44#include <iomanip> 45#include <iostream> 46#include <sstream> 47 48#include "arch/alpha/faults.hh" 49#include "arch/alpha/types.hh" 50#include "config/ss_compatible_fp.hh" 51#include "cpu/static_inst.hh" 52#include "mem/packet.hh" 53#include "mem/request.hh" // some constructors use MemReq flags 54#include "sim/byteswap.hh" 55 56}}; 57 58output decoder {{ 59#include <cmath> 60 61#include "arch/alpha/decoder.hh" 62#include "arch/alpha/registers.hh" 63#include "arch/alpha/regredir.hh" 64#include "base/cprintf.hh" 65#include "base/fenv.hh" 66#include "base/loader/symtab.hh" 67#include "config/ss_compatible_fp.hh" 68#include "cpu/thread_context.hh" // for Jump::branchTarget() 69#include "mem/packet.hh" 70#include "sim/full_system.hh" 71 72using namespace AlphaISA; 73}}; 74 75output exec {{ 76#include <cmath> 77 78#include "arch/alpha/decoder.hh" 79#include "arch/alpha/kernel_stats.hh" 80#include "arch/alpha/registers.hh" 81#include "arch/alpha/regredir.hh" 82#include "arch/generic/memhelpers.hh" 83#include "base/cp_annotate.hh" 84#include "base/fenv.hh" 85#include "config/ss_compatible_fp.hh" 86#include "cpu/base.hh" 87#include "cpu/exetrace.hh" 88#include "mem/packet.hh" 89#include "mem/packet_access.hh" 90#include "sim/full_system.hh" 91#include "sim/pseudo_inst.hh" 92#include "sim/sim_exit.hh" 93 94using namespace AlphaISA; 95}}; 96 97//////////////////////////////////////////////////////////////////// 98// 99// Namespace statement. Everything below this line will be in the 100// AlphaISAInst namespace. 101// 102 103 104namespace AlphaISA; 105 106//////////////////////////////////////////////////////////////////// 107// 108// Bitfield definitions. 109// 110 111// Universal (format-independent) fields 112def bitfield PALMODE <32:32>; 113def bitfield OPCODE <31:26>; 114def bitfield RA <25:21>; 115def bitfield RB <20:16>; 116 117// Memory format 118def signed bitfield MEMDISP <15: 0>; // displacement 119def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned) 120 121// Memory-format jumps 122def bitfield JMPFUNC <15:14>; // function code (disp<15:14>) 123def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>) 124 125// Branch format 126def signed bitfield BRDISP <20: 0>; // displacement 127 128// Integer operate format(s>; 129def bitfield INTIMM <20:13>; // integer immediate (literal) 130def bitfield IMM <12:12>; // immediate flag 131def bitfield INTFUNC <11: 5>; // function code 132def bitfield RC < 4: 0>; // dest reg 133 134// Floating-point operate format 135def bitfield FA <25:21>; 136def bitfield FB <20:16>; 137def bitfield FP_FULLFUNC <15: 5>; // complete function code 138 def bitfield FP_TRAPMODE <15:13>; // trapping mode 139 def bitfield FP_ROUNDMODE <12:11>; // rounding mode 140 def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding 141 def bitfield FP_SRCTYPE <10: 9>; // source reg type 142 def bitfield FP_SHORTFUNC < 8: 5>; // short function code 143 def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code 144def bitfield FC < 4: 0>; // dest reg 145 146// PALcode format 147def bitfield PALFUNC <25: 0>; // function code 148 149// EV5 PAL instructions: 150// HW_LD/HW_ST 151def bitfield HW_LDST_PHYS <15>; // address is physical 152def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR 153def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc 154def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b 155def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch 156def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked 157def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional 158def signed bitfield HW_LDST_DISP <9:0>; // signed displacement 159 160// HW_REI 161def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk 162def bitfield HW_REI_MBZ <13: 0>; // must be zero 163 164// HW_MTPR/MW_MFPR 165def bitfield HW_IPR_IDX <15:0>; // IPR index 166 167// M5 instructions 168def bitfield M5FUNC <7:0>; 169 170def operand_types {{ 171 'sb' : 'int8_t', 172 'ub' : 'uint8_t', 173 'sw' : 'int16_t', 174 'uw' : 'uint16_t', 175 'sl' : 'int32_t', 176 'ul' : 'uint32_t', 177 'sq' : 'int64_t', 178 'uq' : 'uint64_t', 179 'sf' : 'float', 180 'df' : 'double' 181}}; 182 183def operands {{ 184 # Int regs default to unsigned, but code should not count on this. 185 # For clarity, descriptions that depend on unsigned behavior should 186 # explicitly specify '_uq'. 187 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA', 188 'IsInteger', 1), 189 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB', 190 'IsInteger', 2), 191 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC', 192 'IsInteger', 3), 193 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), 194 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 195 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 196 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 197 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4), 198 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4), 199 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1), 200 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1), 201 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1), 202 'LockFlag': ('ControlReg', 'uq', 'MISCREG_LOCKFLAG', None, 1), 203 'IprExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1), 204 # The next two are hacks for non-full-system call-pal emulation 205 'R0': ('IntReg', 'uq', '0', None, 1), 206 'R16': ('IntReg', 'uq', '16', None, 1), 207 'R17': ('IntReg', 'uq', '17', None, 1), 208 'R18': ('IntReg', 'uq', '18', None, 1) 209}}; 210 211//////////////////////////////////////////////////////////////////// 212// 213// Basic instruction classes/templates/formats etc. 214// 215 216output header {{ 217// uncomment the following to get SimpleScalar-compatible disassembly 218// (useful for diffing output traces). 219// #define SS_COMPATIBLE_DISASSEMBLY 220 221 /** 222 * Base class for all Alpha static instructions. 223 */ 224 class AlphaStaticInst : public StaticInst 225 { 226 protected: 227 /// Constructor. 228 AlphaStaticInst(const char *mnem, ExtMachInst _machInst, 229 OpClass __opClass) 230 : StaticInst(mnem, _machInst, __opClass) 231 { 232 } 233 234 /// Print a register name for disassembly given the unique 235 /// dependence tag number (FP or int). 236 void printReg(std::ostream &os, RegId reg) const; 237 238 std::string generateDisassembly( 239 Addr pc, const SymbolTable *symtab) const override; 240 241 void 242 advancePC(AlphaISA::PCState &pcState) const override 243 { 244 pcState.advance(); 245 } 246 247 public: 248 size_t 249 asBytes(void *buf, size_t max_size) override 250 { 251 return simpleAsBytes(buf, max_size, machInst); 252 } 253 }; 254}}; 255 256output decoder {{ 257 void 258 AlphaStaticInst::printReg(std::ostream &os, RegId reg) const 259 { 260 if (reg.isIntReg()) { 261 ccprintf(os, "r%d", reg.index()); 262 } 263 else { 264 ccprintf(os, "f%d", reg.index()); 265 } 266 } 267 268 std::string 269 AlphaStaticInst::generateDisassembly( 270 Addr pc, const SymbolTable *symtab) const 271 { 272 std::stringstream ss; 273 274 ccprintf(ss, "%-10s ", mnemonic); 275 276 // just print the first two source regs... if there's 277 // a third one, it's a read-modify-write dest (Rc), 278 // e.g. for CMOVxx 279 if (_numSrcRegs > 0) { 280 printReg(ss, _srcRegIdx[0]); 281 } 282 if (_numSrcRegs > 1) { 283 ss << ","; 284 printReg(ss, _srcRegIdx[1]); 285 } 286 287 // just print the first dest... if there's a second one, 288 // it's generally implicit 289 if (_numDestRegs > 0) { 290 if (_numSrcRegs > 0) 291 ss << ","; 292 printReg(ss, _destRegIdx[0]); 293 } 294 295 return ss.str(); 296 } 297}}; 298 299// Basic instruction class declaration template. 300def template BasicDeclare {{ 301 /** 302 * Static instruction class for "%(mnemonic)s". 303 */ 304 class %(class_name)s : public %(base_class)s 305 { 306 public: 307 /// Constructor. 308 %(class_name)s(ExtMachInst machInst); 309 310 Fault execute(ExecContext *, Trace::InstRecord *) const override; 311 }; 312}}; 313 314// Basic instruction class constructor template. 315def template BasicConstructor {{ 316 %(class_name)s::%(class_name)s(ExtMachInst machInst) 317 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 318 { 319 %(constructor)s; 320 } 321}}; 322 323// Basic instruction class execute method template. 324def template BasicExecute {{ 325 Fault %(class_name)s::execute(ExecContext *xc, 326 Trace::InstRecord *traceData) const 327 { 328 Fault fault = NoFault; 329 330 %(fp_enable_check)s; 331 %(op_decl)s; 332 %(op_rd)s; 333 %(code)s; 334 335 if (fault == NoFault) { 336 %(op_wb)s; 337 } 338 339 return fault; 340 } 341}}; 342 343// Basic decode template. 344def template BasicDecode {{ 345 return new %(class_name)s(machInst); 346}}; 347 348// Basic decode template, passing mnemonic in as string arg to constructor. 349def template BasicDecodeWithMnemonic {{ 350 return new %(class_name)s("%(mnemonic)s", machInst); 351}}; 352 353// The most basic instruction format... used only for a few misc. insts 354def format BasicOperate(code, *flags) {{ 355 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags) 356 header_output = BasicDeclare.subst(iop) 357 decoder_output = BasicConstructor.subst(iop) 358 decode_block = BasicDecode.subst(iop) 359 exec_output = BasicExecute.subst(iop) 360}}; 361 362 363 364//////////////////////////////////////////////////////////////////// 365// 366// Nop 367// 368 369output header {{ 370 /** 371 * Static instruction class for no-ops. This is a leaf class. 372 */ 373 class Nop : public AlphaStaticInst 374 { 375 /// Disassembly of original instruction. 376 const std::string originalDisassembly; 377 378 public: 379 /// Constructor 380 Nop(const std::string _originalDisassembly, ExtMachInst _machInst) 381 : AlphaStaticInst("nop", _machInst, No_OpClass), 382 originalDisassembly(_originalDisassembly) 383 { 384 flags[IsNop] = true; 385 } 386 387 ~Nop() { } 388 389 std::string generateDisassembly( 390 Addr pc, const SymbolTable *symtab) const override; 391 392 Fault execute(ExecContext *, Trace::InstRecord *) const override; 393 }; 394 395 /// Helper function for decoding nops. Substitute Nop object 396 /// for original inst passed in as arg (and delete latter). 397 static inline 398 AlphaStaticInst * 399 makeNop(AlphaStaticInst *inst) 400 { 401 AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst); 402 delete inst; 403 return nop; 404 } 405}}; 406 407output decoder {{ 408 std::string Nop::generateDisassembly(Addr pc, 409 const SymbolTable *symtab) const 410 { 411#ifdef SS_COMPATIBLE_DISASSEMBLY 412 return originalDisassembly; 413#else 414 return csprintf("%-10s (%s)", "nop", originalDisassembly); 415#endif 416 } 417}}; 418 419output exec {{ 420 Fault 421 Nop::execute(ExecContext *, Trace::InstRecord *) const 422 { 423 return NoFault; 424 } 425}}; 426 427// integer & FP operate instructions use Rc as dest, so check for 428// Rc == 31 to detect nops 429def template OperateNopCheckDecode {{ 430 { 431 AlphaStaticInst *i = new %(class_name)s(machInst); 432 if (RC == 31) { 433 i = makeNop(i); 434 } 435 return i; 436 } 437}}; 438 439// Like BasicOperate format, but generates NOP if RC/FC == 31 440def format BasicOperateWithNopCheck(code, *opt_args) {{ 441 iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args) 442 header_output = BasicDeclare.subst(iop) 443 decoder_output = BasicConstructor.subst(iop) 444 decode_block = OperateNopCheckDecode.subst(iop) 445 exec_output = BasicExecute.subst(iop) 446}}; 447 448// Integer instruction templates, formats, etc. 449##include "int.isa" 450 451// Floating-point instruction templates, formats, etc. 452##include "fp.isa" 453 454// Memory instruction templates, formats, etc. 455##include "mem.isa" 456 457// Branch/jump instruction templates, formats, etc. 458##include "branch.isa" 459 460// PAL instruction templates, formats, etc. 461##include "pal.isa" 462 463// Opcdec fault instruction templates, formats, etc. 464##include "opcdec.isa" 465 466// Unimplemented instruction templates, formats, etc. 467##include "unimp.isa" 468 469// Unknown instruction templates, formats, etc. 470##include "unknown.isa" 471 472// Execution utility functions 473##include "util.isa" 474 475// The actual decoder 476##include "decoder.isa" 477