int.isa revision 2649
12068SN/A// -*- mode:c++ -*- 22068SN/A 32068SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 42068SN/A// All rights reserved. 52068SN/A// 62068SN/A// Redistribution and use in source and binary forms, with or without 72068SN/A// modification, are permitted provided that the following conditions are 82068SN/A// met: redistributions of source code must retain the above copyright 92068SN/A// notice, this list of conditions and the following disclaimer; 102068SN/A// redistributions in binary form must reproduce the above copyright 112068SN/A// notice, this list of conditions and the following disclaimer in the 122068SN/A// documentation and/or other materials provided with the distribution; 132068SN/A// neither the name of the copyright holders nor the names of its 142068SN/A// contributors may be used to endorse or promote products derived from 152068SN/A// this software without specific prior written permission. 162068SN/A// 172068SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182068SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192068SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202068SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212068SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222068SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232068SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242068SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252068SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262068SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272068SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282068SN/A 292649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 302649Ssaidi@eecs.umich.edu// 312649Ssaidi@eecs.umich.edu// Integer operate instructions 322649Ssaidi@eecs.umich.edu// 332649Ssaidi@eecs.umich.edu 342068SN/Aoutput header {{ 352068SN/A /** 362068SN/A * Base class for integer immediate instructions. 372068SN/A */ 382068SN/A class IntegerImm : public AlphaStaticInst 392068SN/A { 402068SN/A protected: 412068SN/A /// Immediate operand value (unsigned 8-bit int). 422068SN/A uint8_t imm; 432068SN/A 442068SN/A /// Constructor 452227SN/A IntegerImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 462068SN/A : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM) 472068SN/A { 482068SN/A } 492068SN/A 502068SN/A std::string 512068SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 522068SN/A }; 532068SN/A}}; 542068SN/A 552068SN/Aoutput decoder {{ 562068SN/A std::string 572068SN/A IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const 582068SN/A { 592068SN/A std::stringstream ss; 602068SN/A 612068SN/A ccprintf(ss, "%-10s ", mnemonic); 622068SN/A 632068SN/A // just print the first source reg... if there's 642068SN/A // a second one, it's a read-modify-write dest (Rc), 652068SN/A // e.g. for CMOVxx 662068SN/A if (_numSrcRegs > 0) { 672068SN/A printReg(ss, _srcRegIdx[0]); 682068SN/A ss << ","; 692068SN/A } 702068SN/A 712068SN/A ss << (int)imm; 722068SN/A 732068SN/A if (_numDestRegs > 0) { 742068SN/A ss << ","; 752068SN/A printReg(ss, _destRegIdx[0]); 762068SN/A } 772068SN/A 782068SN/A return ss.str(); 792068SN/A } 802068SN/A}}; 812068SN/A 822068SN/A 832068SN/Adef template RegOrImmDecode {{ 842068SN/A { 852068SN/A AlphaStaticInst *i = 862068SN/A (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst) 872068SN/A : (AlphaStaticInst *)new %(class_name)s(machInst); 882068SN/A if (RC == 31) { 892068SN/A i = makeNop(i); 902068SN/A } 912068SN/A return i; 922068SN/A } 932068SN/A}}; 942068SN/A 952068SN/A// Primary format for integer operate instructions: 962068SN/A// - Generates both reg-reg and reg-imm versions if Rb_or_imm is used. 972068SN/A// - Generates NOP if RC == 31. 982068SN/Adef format IntegerOperate(code, *opt_flags) {{ 992068SN/A # If the code block contains 'Rb_or_imm', we define two instructions, 1002068SN/A # one using 'Rb' and one using 'imm', and have the decoder select 1012068SN/A # the right one. 1022068SN/A uses_imm = (code.find('Rb_or_imm') != -1) 1032068SN/A if uses_imm: 1042068SN/A orig_code = code 1052068SN/A # base code is reg version: 1062068SN/A # rewrite by substituting 'Rb' for 'Rb_or_imm' 1072068SN/A code = re.sub(r'Rb_or_imm', 'Rb', orig_code) 1082068SN/A # generate immediate version by substituting 'imm' 1092068SN/A # note that imm takes no extenstion, so we extend 1102068SN/A # the regexp to replace any extension as well 1112068SN/A imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code) 1122068SN/A 1132068SN/A # generate declaration for register version 1142068SN/A cblk = CodeBlock(code) 1152068SN/A iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags) 1162068SN/A header_output = BasicDeclare.subst(iop) 1172068SN/A decoder_output = BasicConstructor.subst(iop) 1182068SN/A exec_output = BasicExecute.subst(iop) 1192068SN/A 1202068SN/A if uses_imm: 1212068SN/A # append declaration for imm version 1222068SN/A imm_cblk = CodeBlock(imm_code) 1232068SN/A imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk, 1242068SN/A opt_flags) 1252068SN/A header_output += BasicDeclare.subst(imm_iop) 1262068SN/A decoder_output += BasicConstructor.subst(imm_iop) 1272068SN/A exec_output += BasicExecute.subst(imm_iop) 1282068SN/A # decode checks IMM bit to pick correct version 1292068SN/A decode_block = RegOrImmDecode.subst(iop) 1302068SN/A else: 1312068SN/A # no imm version: just check for nop 1322068SN/A decode_block = OperateNopCheckDecode.subst(iop) 1332068SN/A}}; 134