decoder.isa revision 9829
12292SN/A// -*- mode:c++ -*- 22329SN/A 32292SN/A// Copyright (c) 2013 ARM Limited 42292SN/A// All rights reserved 52292SN/A// 62292SN/A// The license below extends only to copyright in the software and shall 72292SN/A// not be construed as granting a license to any other intellectual 82292SN/A// property including but not limited to intellectual property relating 92292SN/A// to a hardware implementation of the functionality of the software 102292SN/A// licensed hereunder. You may use the software subject to the license 112292SN/A// terms below provided that you ensure that this notice is replicated 122292SN/A// unmodified and in its entirety in all distributions of the software, 132292SN/A// modified or unmodified, in source code or in binary form. 142292SN/A// 152292SN/A// Copyright (c) 2003-2006 The Regents of The University of Michigan 162292SN/A// All rights reserved. 172292SN/A// 182292SN/A// Redistribution and use in source and binary forms, with or without 192292SN/A// modification, are permitted provided that the following conditions are 202292SN/A// met: redistributions of source code must retain the above copyright 212292SN/A// notice, this list of conditions and the following disclaimer; 222292SN/A// redistributions in binary form must reproduce the above copyright 232292SN/A// notice, this list of conditions and the following disclaimer in the 242292SN/A// documentation and/or other materials provided with the distribution; 252292SN/A// neither the name of the copyright holders nor the names of its 262292SN/A// contributors may be used to endorse or promote products derived from 272689Sktlim@umich.edu// this software without specific prior written permission. 282689Sktlim@umich.edu// 292689Sktlim@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302292SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312292SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322292SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332292SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342292SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352329SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364395Ssaidi@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372292SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382292SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392292SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 408591Sgblack@eecs.umich.edu// 418506Sgblack@eecs.umich.edu// Authors: Steve Reinhardt 423326Sktlim@umich.edu 438481Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 448229Snate@binkert.org// 458229Snate@binkert.org// The actual decoder specification 466658Snate@binkert.org// 472292SN/A 488230Snate@binkert.orgdecode OPCODE default Unknown::unknown() { 498232Snate@binkert.org 503348Sbinkertn@umich.edu format LoadAddress { 512669Sktlim@umich.edu 0x08: lda({{ Ra = Rb + disp; }}); 528817Sgblack@eecs.umich.edu 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 532292SN/A } 548737Skoansin.tan@gmail.com 555529Snate@binkert.org format LoadOrNop { 562292SN/A 0x0a: ldbu({{ Ra_uq = Mem_ub; }}); 572329SN/A 0x0c: ldwu({{ Ra_uq = Mem_uw; }}); 582329SN/A 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 592329SN/A 0x23: ldt({{ Fa = Mem_df; }}); 602329SN/A 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC); 612329SN/A 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC); 622329SN/A } 632329SN/A 642329SN/A format LoadOrPrefetch { 652329SN/A 0x28: ldl({{ Ra_sl = Mem_sl; }}); 662329SN/A 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT); 672292SN/A // IsFloating flag on lds gets the prefetch to disassemble 682292SN/A // using f31 instead of r31... funcitonally it's unnecessary 692292SN/A 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }}, 702292SN/A pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 712733Sktlim@umich.edu } 722292SN/A 732292SN/A format Store { 742907Sktlim@umich.edu 0x0e: stb({{ Mem_ub = Ra<7:0>; }}); 752292SN/A 0x0d: stw({{ Mem_uw = Ra<15:0>; }}); 762292SN/A 0x2c: stl({{ Mem_ul = Ra<31:0>; }}); 772292SN/A 0x2d: stq({{ Mem_uq = Ra_uq; }}); 782292SN/A 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }}); 792292SN/A 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }}); 802292SN/A 0x27: stt({{ Mem_df = Fa; }}); 812292SN/A } 825529Snate@binkert.org 835529Snate@binkert.org format StoreCond { 845529Snate@binkert.org 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }}, 852292SN/A {{ 862292SN/A uint64_t tmp = write_result; 872292SN/A // see stq_c 882292SN/A Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 892727Sktlim@umich.edu if (tmp == 1) { 902727Sktlim@umich.edu xc->setStCondFailures(0); 912727Sktlim@umich.edu } 922907Sktlim@umich.edu }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 938922Swilliam.wang@arm.com 0x2f: stq_c({{ Mem_uq = Ra; }}, 942907Sktlim@umich.edu {{ 952348SN/A uint64_t tmp = write_result; 962307SN/A // If the write operation returns 0 or 1, then 972307SN/A // this was a conventional store conditional, 982348SN/A // and the value indicates the success/failure 992307SN/A // of the operation. If another value is 1002307SN/A // returned, then this was a Turbolaser 1012348SN/A // mailbox access, and we don't update the 1022307SN/A // result register at all. 1032307SN/A Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 1042292SN/A if (tmp == 1) { 1052292SN/A // clear failure counter... this is 1062292SN/A // non-architectural and for debugging 1072292SN/A // only. 1082292SN/A xc->setStCondFailures(0); 1092292SN/A } 1102292SN/A }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 1112292SN/A } 1122292SN/A 1132292SN/A format IntegerOperate { 1142292SN/A 1152292SN/A 0x10: decode INTFUNC { // integer arithmetic operations 1162292SN/A 1172292SN/A 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }}); 1188545Ssaidi@eecs.umich.edu 0x40: addlv({{ 1198545Ssaidi@eecs.umich.edu int32_t tmp = Ra_sl + Rb_or_imm_sl; 1208545Ssaidi@eecs.umich.edu // signed overflow occurs when operands have same sign 1218199SAli.Saidi@ARM.com // and sign of result does not match. 1228199SAli.Saidi@ARM.com if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>) 1238199SAli.Saidi@ARM.com fault = new IntegerOverflowFault; 1248199SAli.Saidi@ARM.com Rc_sl = tmp; 1258199SAli.Saidi@ARM.com }}); 1268545Ssaidi@eecs.umich.edu 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }}); 1278545Ssaidi@eecs.umich.edu 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }}); 1288545Ssaidi@eecs.umich.edu 1298545Ssaidi@eecs.umich.edu 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 1308545Ssaidi@eecs.umich.edu 0x60: addqv({{ 1318545Ssaidi@eecs.umich.edu uint64_t tmp = Ra + Rb_or_imm; 1322292SN/A // signed overflow occurs when operands have same sign 1332292SN/A // and sign of result does not match. 1342292SN/A if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1352329SN/A fault = new IntegerOverflowFault; 1362292SN/A Rc = tmp; 1372292SN/A }}); 1382292SN/A 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 1392292SN/A 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 1402292SN/A 1412292SN/A 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }}); 1422292SN/A 0x49: sublv({{ 1432292SN/A int32_t tmp = Ra_sl - Rb_or_imm_sl; 1442292SN/A // signed overflow detection is same as for add, 1452292SN/A // except we need to look at the *complemented* 1462292SN/A // sign bit of the subtrahend (Rb), i.e., if the initial 1472292SN/A // signs are the *same* then no overflow can occur 1482292SN/A if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>) 1492292SN/A fault = new IntegerOverflowFault; 1502790Sktlim@umich.edu Rc_sl = tmp; 1512790Sktlim@umich.edu }}); 1522669Sktlim@umich.edu 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }}); 1532669Sktlim@umich.edu 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }}); 1542292SN/A 1552292SN/A 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 1562292SN/A 0x69: subqv({{ 1572292SN/A uint64_t tmp = Ra - Rb_or_imm; 1582292SN/A // signed overflow detection is same as for add, 1592292SN/A // except we need to look at the *complemented* 1602292SN/A // sign bit of the subtrahend (Rb), i.e., if the initial 1612292SN/A // signs are the *same* then no overflow can occur 1622292SN/A if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1632292SN/A fault = new IntegerOverflowFault; 1642292SN/A Rc = tmp; 1652292SN/A }}); 1662292SN/A 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 1672292SN/A 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 1682292SN/A 1692292SN/A 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 1702292SN/A 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }}); 1712292SN/A 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }}); 1722292SN/A 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }}); 1732292SN/A 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }}); 1742292SN/A 1752292SN/A 0x0f: cmpbge({{ 1762292SN/A int hi = 7; 1772329SN/A int lo = 0; 1782292SN/A uint64_t tmp = 0; 1792292SN/A for (int i = 0; i < 8; ++i) { 1802292SN/A tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i; 1812348SN/A hi += 8; 1822292SN/A lo += 8; 1832292SN/A } 1842292SN/A Rc = tmp; 1852348SN/A }}); 1862292SN/A } 1872292SN/A 1882292SN/A 0x11: decode INTFUNC { // integer logical operations 1892348SN/A 1902292SN/A 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 1912292SN/A 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 1922292SN/A 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 1932292SN/A 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 1942292SN/A 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 1952292SN/A 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 1962292SN/A 1972292SN/A // conditional moves 1982292SN/A 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 1992292SN/A 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 2002292SN/A 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 2012292SN/A 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 2022292SN/A 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }}); 2032292SN/A 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }}); 2042292SN/A 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }}); 2052292SN/A 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }}); 2062292SN/A 2072292SN/A // For AMASK, RA must be R31. 2082292SN/A 0x61: decode RA { 2092292SN/A 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 2102292SN/A } 2112292SN/A 2122292SN/A // For IMPLVER, RA must be R31 and the B operand 2132292SN/A // must be the immediate value 1. 2142292SN/A 0x6c: decode RA { 2152292SN/A 31: decode IMM { 2162292SN/A 1: decode INTIMM { 2172292SN/A // return EV5 for FullSystem and EV6 otherwise 2182292SN/A 1: implver({{ Rc = FullSystem ? 1 : 2 }}); 2192292SN/A } 2202292SN/A } 2212292SN/A } 2222292SN/A 2232292SN/A // The mysterious 11.25... 2242292SN/A 0x25: WarnUnimpl::eleven25(); 2252678Sktlim@umich.edu } 2262678Sktlim@umich.edu 2272292SN/A 0x12: decode INTFUNC { 2282907Sktlim@umich.edu 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 2292907Sktlim@umich.edu 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }}); 2302907Sktlim@umich.edu 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }}); 2312292SN/A 2322698Sktlim@umich.edu 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 2332678Sktlim@umich.edu 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 2342678Sktlim@umich.edu 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 2356974Stjones1@inf.ed.ac.uk 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 2366974Stjones1@inf.ed.ac.uk 2376974Stjones1@inf.ed.ac.uk 0x52: mskwh({{ 2382698Sktlim@umich.edu int bv = Rb_or_imm<2:0>; 2393349Sbinkertn@umich.edu Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 2402693Sktlim@umich.edu }}); 2412292SN/A 0x62: msklh({{ 2422292SN/A int bv = Rb_or_imm<2:0>; 2432292SN/A Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 2446974Stjones1@inf.ed.ac.uk }}); 2456974Stjones1@inf.ed.ac.uk 0x72: mskqh({{ 2466974Stjones1@inf.ed.ac.uk int bv = Rb_or_imm<2:0>; 2472292SN/A Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 2482292SN/A }}); 2492292SN/A 2502292SN/A 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 2512292SN/A 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 2522292SN/A 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 2532292SN/A 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }}); 2542292SN/A 2552292SN/A 0x5a: extwh({{ 2562329SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 2572329SN/A 0x6a: extlh({{ 2582329SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 2592329SN/A 0x7a: extqh({{ 2602292SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 2612292SN/A 2622733Sktlim@umich.edu 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 2632292SN/A 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 2642292SN/A 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 2652292SN/A 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 2662292SN/A 2672907Sktlim@umich.edu 0x57: inswh({{ 2682907Sktlim@umich.edu int bv = Rb_or_imm<2:0>; 2692669Sktlim@umich.edu Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0; 2702907Sktlim@umich.edu }}); 2718922Swilliam.wang@arm.com 0x67: inslh({{ 2722292SN/A int bv = Rb_or_imm<2:0>; 2732698Sktlim@umich.edu Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0; 2745386Sstever@gmail.com }}); 2752678Sktlim@umich.edu 0x77: insqh({{ 2762678Sktlim@umich.edu int bv = Rb_or_imm<2:0>; 2772698Sktlim@umich.edu Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0; 2782678Sktlim@umich.edu }}); 2796974Stjones1@inf.ed.ac.uk 2806974Stjones1@inf.ed.ac.uk 0x30: zap({{ 2812678Sktlim@umich.edu uint64_t zapmask = 0; 2822678Sktlim@umich.edu for (int i = 0; i < 8; ++i) { 2832698Sktlim@umich.edu if (Rb_or_imm<i:>) 2842678Sktlim@umich.edu zapmask |= (mask(8) << (i * 8)); 2852698Sktlim@umich.edu } 2862678Sktlim@umich.edu Rc = Ra & ~zapmask; 2872698Sktlim@umich.edu }}); 2882678Sktlim@umich.edu 0x31: zapnot({{ 2892698Sktlim@umich.edu uint64_t zapmask = 0; 2902678Sktlim@umich.edu for (int i = 0; i < 8; ++i) { 2916974Stjones1@inf.ed.ac.uk if (!Rb_or_imm<i:>) 2926974Stjones1@inf.ed.ac.uk zapmask |= (mask(8) << (i * 8)); 2936974Stjones1@inf.ed.ac.uk } 2946974Stjones1@inf.ed.ac.uk Rc = Ra & ~zapmask; 2956974Stjones1@inf.ed.ac.uk }}); 2966974Stjones1@inf.ed.ac.uk } 2976974Stjones1@inf.ed.ac.uk 2986974Stjones1@inf.ed.ac.uk 0x13: decode INTFUNC { // integer multiplies 2996974Stjones1@inf.ed.ac.uk 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp); 3006974Stjones1@inf.ed.ac.uk 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 3016974Stjones1@inf.ed.ac.uk 0x30: umulh({{ 3026974Stjones1@inf.ed.ac.uk uint64_t hi, lo; 3036974Stjones1@inf.ed.ac.uk mul128(Ra, Rb_or_imm, hi, lo); 3042678Sktlim@umich.edu Rc = hi; 3052678Sktlim@umich.edu }}, IntMultOp); 3062698Sktlim@umich.edu 0x40: mullv({{ 3072678Sktlim@umich.edu // 32-bit multiply with trap on overflow 3082678Sktlim@umich.edu int64_t Rax = Ra_sl; // sign extended version of Ra_sl 3092678Sktlim@umich.edu int64_t Rbx = Rb_or_imm_sl; 3102678Sktlim@umich.edu int64_t tmp = Rax * Rbx; 3112678Sktlim@umich.edu // To avoid overflow, all the upper 32 bits must match 3122678Sktlim@umich.edu // the sign bit of the lower 32. We code this as 3132678Sktlim@umich.edu // checking the upper 33 bits for all 0s or all 1s. 3142678Sktlim@umich.edu uint64_t sign_bits = tmp<63:31>; 3152678Sktlim@umich.edu if (sign_bits != 0 && sign_bits != mask(33)) 3165336Shines@cs.fsu.edu fault = new IntegerOverflowFault; 3172678Sktlim@umich.edu Rc_sl = tmp<31:0>; 3182678Sktlim@umich.edu }}, IntMultOp); 3192698Sktlim@umich.edu 0x60: mulqv({{ 3202678Sktlim@umich.edu // 64-bit multiply with trap on overflow 3212678Sktlim@umich.edu uint64_t hi, lo; 3222698Sktlim@umich.edu mul128(Ra, Rb_or_imm, hi, lo); 3232678Sktlim@umich.edu // all the upper 64 bits must match the sign bit of 3242678Sktlim@umich.edu // the lower 64 3252678Sktlim@umich.edu if (!((hi == 0 && lo<63:> == 0) || 3262678Sktlim@umich.edu (hi == mask(64) && lo<63:> == 1))) 3272678Sktlim@umich.edu fault = new IntegerOverflowFault; 3282678Sktlim@umich.edu Rc = lo; 3292292SN/A }}, IntMultOp); 3302292SN/A } 3312292SN/A 3322292SN/A 0x1c: decode INTFUNC { 3334326Sgblack@eecs.umich.edu 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); } 3342292SN/A 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); } 3354326Sgblack@eecs.umich.edu 3364395Ssaidi@eecs.umich.edu 0x30: ctpop({{ 3374326Sgblack@eecs.umich.edu uint64_t count = 0; 3382292SN/A for (int i = 0; Rb<63:i>; ++i) { 3392292SN/A if (Rb<i:i> == 0x1) 3402292SN/A ++count; 3416974Stjones1@inf.ed.ac.uk } 3426974Stjones1@inf.ed.ac.uk Rc = count; 3434326Sgblack@eecs.umich.edu }}, IntAluOp); 3444395Ssaidi@eecs.umich.edu 3454326Sgblack@eecs.umich.edu 0x31: perr({{ 3462292SN/A uint64_t temp = 0; 3472292SN/A int hi = 7; 3482292SN/A int lo = 0; 3492669Sktlim@umich.edu for (int i = 0; i < 8; ++i) { 3502669Sktlim@umich.edu uint8_t ra_ub = Ra_uq<hi:lo>; 3516974Stjones1@inf.ed.ac.uk uint8_t rb_ub = Rb_uq<hi:lo>; 3526974Stjones1@inf.ed.ac.uk temp += (ra_ub >= rb_ub) ? 3536974Stjones1@inf.ed.ac.uk (ra_ub - rb_ub) : (rb_ub - ra_ub); 3542292SN/A hi += 8; 3552292SN/A lo += 8; 3562292SN/A } 3577786SAli.Saidi@ARM.com Rc = temp; 3586974Stjones1@inf.ed.ac.uk }}); 3596974Stjones1@inf.ed.ac.uk 3602292SN/A 0x32: ctlz({{ 3612292SN/A uint64_t count = 0; 3622292SN/A uint64_t temp = Rb; 3632292SN/A if (temp<63:32>) temp >>= 32; else count += 32; 3642292SN/A if (temp<31:16>) temp >>= 16; else count += 16; 3652292SN/A if (temp<15:8>) temp >>= 8; else count += 8; 3662292SN/A if (temp<7:4>) temp >>= 4; else count += 4; 3672329SN/A if (temp<3:2>) temp >>= 2; else count += 2; 3682292SN/A if (temp<1:1>) temp >>= 1; else count += 1; 3692292SN/A if ((temp<0:0>) != 0x1) count += 1; 3706221Snate@binkert.org Rc = count; 3712292SN/A }}, IntAluOp); 3722292SN/A 3732292SN/A 0x33: cttz({{ 3742292SN/A uint64_t count = 0; 3752292SN/A uint64_t temp = Rb; 3762292SN/A if (!(temp<31:0>)) { temp >>= 32; count += 32; } 3772292SN/A if (!(temp<15:0>)) { temp >>= 16; count += 16; } 3782329SN/A if (!(temp<7:0>)) { temp >>= 8; count += 8; } 3792329SN/A if (!(temp<3:0>)) { temp >>= 4; count += 4; } 3802329SN/A if (!(temp<1:0>)) { temp >>= 2; count += 2; } 3812292SN/A if (!(temp<0:0> & ULL(0x1))) { 3822329SN/A temp >>= 1; count += 1; 3832329SN/A } 3842329SN/A if (!(temp<0:0> & ULL(0x1))) count += 1; 3852292SN/A Rc = count; 3862292SN/A }}, IntAluOp); 3878199SAli.Saidi@ARM.com 3888199SAli.Saidi@ARM.com 3898199SAli.Saidi@ARM.com 0x34: unpkbw({{ 3908199SAli.Saidi@ARM.com Rc = (Rb_uq<7:0> 3918199SAli.Saidi@ARM.com | (Rb_uq<15:8> << 16) 3928199SAli.Saidi@ARM.com | (Rb_uq<23:16> << 32) 3938199SAli.Saidi@ARM.com | (Rb_uq<31:24> << 48)); 3948199SAli.Saidi@ARM.com }}, IntAluOp); 3952292SN/A 3962292SN/A 0x35: unpkbl({{ 3972329SN/A Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32)); 3982292SN/A }}, IntAluOp); 3992292SN/A 4002292SN/A 0x36: pkwb({{ 4012292SN/A Rc = (Rb_uq<7:0> 4022292SN/A | (Rb_uq<23:16> << 8) 4032292SN/A | (Rb_uq<39:32> << 16) 4042292SN/A | (Rb_uq<55:48> << 24)); 4052292SN/A }}, IntAluOp); 4062292SN/A 4072292SN/A 0x37: pklb({{ 4082292SN/A Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8)); 4092329SN/A }}, IntAluOp); 4102329SN/A 4112292SN/A 0x38: minsb8({{ 4122292SN/A uint64_t temp = 0; 4132292SN/A int hi = 63; 4142292SN/A int lo = 56; 4152292SN/A for (int i = 7; i >= 0; --i) { 4162292SN/A int8_t ra_sb = Ra_uq<hi:lo>; 4172292SN/A int8_t rb_sb = Rb_uq<hi:lo>; 4182292SN/A temp = ((temp << 8) 4192292SN/A | ((ra_sb < rb_sb) ? Ra_uq<hi:lo> 4202292SN/A : Rb_uq<hi:lo>)); 4212292SN/A hi -= 8; 4222292SN/A lo -= 8; 4232348SN/A } 4242307SN/A Rc = temp; 4252307SN/A }}); 4262292SN/A 4272292SN/A 0x39: minsw4({{ 4288545Ssaidi@eecs.umich.edu uint64_t temp = 0; 4298545Ssaidi@eecs.umich.edu int hi = 63; 4308545Ssaidi@eecs.umich.edu int lo = 48; 4312292SN/A for (int i = 3; i >= 0; --i) { 4322292SN/A int16_t ra_sw = Ra_uq<hi:lo>; 4332292SN/A int16_t rb_sw = Rb_uq<hi:lo>; 4342292SN/A temp = ((temp << 16) 4352292SN/A | ((ra_sw < rb_sw) ? Ra_uq<hi:lo> 4362292SN/A : Rb_uq<hi:lo>)); 4372292SN/A hi -= 16; 4382292SN/A lo -= 16; 4392292SN/A } 4402292SN/A Rc = temp; 4412292SN/A }}); 4422292SN/A 4432698Sktlim@umich.edu 0x3a: minub8({{ 4442698Sktlim@umich.edu uint64_t temp = 0; 4452693Sktlim@umich.edu int hi = 63; 4462698Sktlim@umich.edu int lo = 56; 4472678Sktlim@umich.edu for (int i = 7; i >= 0; --i) { 4482678Sktlim@umich.edu uint8_t ra_ub = Ra_uq<hi:lo>; 4492329SN/A uint8_t rb_ub = Rb_uq<hi:lo>; 4502292SN/A temp = ((temp << 8) 4512292SN/A | ((ra_ub < rb_ub) ? Ra_uq<hi:lo> 4522348SN/A : Rb_uq<hi:lo>)); 4532292SN/A hi -= 8; 4542292SN/A lo -= 8; 4558727Snilay@cs.wisc.edu } 4568727Snilay@cs.wisc.edu Rc = temp; 4578727Snilay@cs.wisc.edu }}); 4582348SN/A 4592292SN/A 0x3b: minuw4({{ 4602292SN/A uint64_t temp = 0; 4612292SN/A int hi = 63; 4622292SN/A int lo = 48; 4632292SN/A for (int i = 3; i >= 0; --i) { 4646974Stjones1@inf.ed.ac.uk uint16_t ra_sw = Ra_uq<hi:lo>; 4656974Stjones1@inf.ed.ac.uk uint16_t rb_sw = Rb_uq<hi:lo>; 4666974Stjones1@inf.ed.ac.uk temp = ((temp << 16) 4676974Stjones1@inf.ed.ac.uk | ((ra_sw < rb_sw) ? Ra_uq<hi:lo> 4686974Stjones1@inf.ed.ac.uk : Rb_uq<hi:lo>)); 4696974Stjones1@inf.ed.ac.uk hi -= 16; 4706974Stjones1@inf.ed.ac.uk lo -= 16; 4718727Snilay@cs.wisc.edu } 4728727Snilay@cs.wisc.edu Rc = temp; 4738727Snilay@cs.wisc.edu }}); 4742292SN/A 4752292SN/A 0x3c: maxub8({{ 4762292SN/A uint64_t temp = 0; 4772727Sktlim@umich.edu int hi = 63; 4785999Snate@binkert.org int lo = 56; 4792307SN/A for (int i = 7; i >= 0; --i) { 4803126Sktlim@umich.edu uint8_t ra_ub = Ra_uq<hi:lo>; 4815999Snate@binkert.org uint8_t rb_ub = Rb_uq<hi:lo>; 4823126Sktlim@umich.edu temp = ((temp << 8) 4833126Sktlim@umich.edu | ((ra_ub > rb_ub) ? Ra_uq<hi:lo> 4845999Snate@binkert.org : Rb_uq<hi:lo>)); 4853126Sktlim@umich.edu hi -= 8; 4863126Sktlim@umich.edu lo -= 8; 4873126Sktlim@umich.edu } 4885999Snate@binkert.org Rc = temp; 4893126Sktlim@umich.edu }}); 4903126Sktlim@umich.edu 4915999Snate@binkert.org 0x3d: maxuw4({{ 4923126Sktlim@umich.edu uint64_t temp = 0; 4932727Sktlim@umich.edu int hi = 63; 4945999Snate@binkert.org int lo = 48; 4952727Sktlim@umich.edu for (int i = 3; i >= 0; --i) { 4962727Sktlim@umich.edu uint16_t ra_uw = Ra_uq<hi:lo>; 4975999Snate@binkert.org uint16_t rb_uw = Rb_uq<hi:lo>; 4982727Sktlim@umich.edu temp = ((temp << 16) 4992727Sktlim@umich.edu | ((ra_uw > rb_uw) ? Ra_uq<hi:lo> 5005999Snate@binkert.org : Rb_uq<hi:lo>)); 5012727Sktlim@umich.edu hi -= 16; 5022727Sktlim@umich.edu lo -= 16; 5035999Snate@binkert.org } 5042727Sktlim@umich.edu Rc = temp; 5052727Sktlim@umich.edu }}); 5065999Snate@binkert.org 5072727Sktlim@umich.edu 0x3e: maxsb8({{ 5082292SN/A uint64_t temp = 0; 5092292SN/A int hi = 63; 5107520Sgblack@eecs.umich.edu int lo = 56; 5117520Sgblack@eecs.umich.edu for (int i = 7; i >= 0; --i) { 5122292SN/A int8_t ra_sb = Ra_uq<hi:lo>; 5132292SN/A int8_t rb_sb = Rb_uq<hi:lo>; 5147520Sgblack@eecs.umich.edu temp = ((temp << 8) 5157520Sgblack@eecs.umich.edu | ((ra_sb > rb_sb) ? Ra_uq<hi:lo> 5162292SN/A : Rb_uq<hi:lo>)); 5172292SN/A hi -= 8; 5182292SN/A lo -= 8; 5192292SN/A } 5202292SN/A Rc = temp; 5212292SN/A }}); 5222292SN/A 5232292SN/A 0x3f: maxsw4({{ 5242292SN/A uint64_t temp = 0; 5252292SN/A int hi = 63; 5262292SN/A int lo = 48; 5272292SN/A for (int i = 3; i >= 0; --i) { 5282292SN/A int16_t ra_sw = Ra_uq<hi:lo>; 5292292SN/A int16_t rb_sw = Rb_uq<hi:lo>; 5302292SN/A temp = ((temp << 16) 5312292SN/A | ((ra_sw > rb_sw) ? Ra_uq<hi:lo> 5322292SN/A : Rb_uq<hi:lo>)); 5332292SN/A hi -= 16; 5342292SN/A lo -= 16; 5352292SN/A } 5362292SN/A Rc = temp; 5372292SN/A }}); 5382292SN/A 5392292SN/A format BasicOperateWithNopCheck { 5402292SN/A 0x70: decode RB { 5412292SN/A 31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp); 5422292SN/A } 5432292SN/A 0x78: decode RB { 5442292SN/A 31: ftois({{ Rc_sl = t_to_s(Fa_uq); }}, 5452292SN/A FloatCvtOp); 5462292SN/A } 5472292SN/A } 5482292SN/A } 5496974Stjones1@inf.ed.ac.uk } 5507520Sgblack@eecs.umich.edu 5512292SN/A // Conditional branches. 5522669Sktlim@umich.edu format CondBranch { 5532292SN/A 0x39: beq({{ cond = (Ra == 0); }}); 5542669Sktlim@umich.edu 0x3d: bne({{ cond = (Ra != 0); }}); 5552669Sktlim@umich.edu 0x3e: bge({{ cond = (Ra_sq >= 0); }}); 5562669Sktlim@umich.edu 0x3f: bgt({{ cond = (Ra_sq > 0); }}); 5572292SN/A 0x3b: ble({{ cond = (Ra_sq <= 0); }}); 5582292SN/A 0x3a: blt({{ cond = (Ra_sq < 0); }}); 5592292SN/A 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 5602292SN/A 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 5612292SN/A 5623172Sstever@eecs.umich.edu 0x31: fbeq({{ cond = (Fa == 0); }}); 5632731Sktlim@umich.edu 0x35: fbne({{ cond = (Fa != 0); }}); 5642669Sktlim@umich.edu 0x36: fbge({{ cond = (Fa >= 0); }}); 5652727Sktlim@umich.edu 0x37: fbgt({{ cond = (Fa > 0); }}); 5667720Sgblack@eecs.umich.edu 0x33: fble({{ cond = (Fa <= 0); }}); 5677720Sgblack@eecs.umich.edu 0x32: fblt({{ cond = (Fa < 0); }}); 5684032Sktlim@umich.edu } 5694032Sktlim@umich.edu 5704032Sktlim@umich.edu // unconditional branches 5714032Sktlim@umich.edu format UncondBranch { 5724032Sktlim@umich.edu 0x30: br(); 5736974Stjones1@inf.ed.ac.uk 0x34: bsr(IsCall); 5746974Stjones1@inf.ed.ac.uk } 5756974Stjones1@inf.ed.ac.uk 5766974Stjones1@inf.ed.ac.uk // indirect branches 5778591Sgblack@eecs.umich.edu 0x1a: decode JMPFUNC { 5788591Sgblack@eecs.umich.edu format Jump { 5798591Sgblack@eecs.umich.edu 0: jmp(); 5802292SN/A 1: jsr(IsCall); 5812292SN/A 2: ret(IsReturn); 5822292SN/A 3: jsr_coroutine(IsCall, IsReturn); 5832669Sktlim@umich.edu } 5842292SN/A } 5852292SN/A 5862292SN/A // Square root and integer-to-FP moves 5872292SN/A 0x14: decode FP_SHORTFUNC { 5886974Stjones1@inf.ed.ac.uk // Integer to FP register moves must have RB == 31 5896974Stjones1@inf.ed.ac.uk 0x4: decode RB { 5906974Stjones1@inf.ed.ac.uk 31: decode FP_FULLFUNC { 5912292SN/A format BasicOperateWithNopCheck { 5926102Sgblack@eecs.umich.edu 0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp); 5936974Stjones1@inf.ed.ac.uk 0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp); 5943326Sktlim@umich.edu 0x014: FailUnimpl::itoff(); // VAX-format conversion 5953326Sktlim@umich.edu } 5963326Sktlim@umich.edu } 5973326Sktlim@umich.edu } 5983326Sktlim@umich.edu 5993326Sktlim@umich.edu // Square root instructions must have FA == 31 6002292SN/A 0xb: decode FA { 6012292SN/A 31: decode FP_TYPEFUNC { 6028481Sgblack@eecs.umich.edu format FloatingPointOperate { 6038481Sgblack@eecs.umich.edu#if SS_COMPATIBLE_FP 6048481Sgblack@eecs.umich.edu 0x0b: sqrts({{ 6058481Sgblack@eecs.umich.edu if (Fb < 0.0) 6068481Sgblack@eecs.umich.edu fault = new ArithmeticFault; 6078481Sgblack@eecs.umich.edu Fc = sqrt(Fb); 6088949Sandreas.hansson@arm.com }}, FloatSqrtOp); 6098481Sgblack@eecs.umich.edu#else 6108481Sgblack@eecs.umich.edu 0x0b: sqrts({{ 6118481Sgblack@eecs.umich.edu if (Fb_sf < 0.0) 6128481Sgblack@eecs.umich.edu fault = new ArithmeticFault; 6138481Sgblack@eecs.umich.edu Fc_sf = sqrt(Fb_sf); 6148481Sgblack@eecs.umich.edu }}, FloatSqrtOp); 6158949Sandreas.hansson@arm.com#endif 6168949Sandreas.hansson@arm.com 0x2b: sqrtt({{ 6178481Sgblack@eecs.umich.edu if (Fb < 0.0) 6188481Sgblack@eecs.umich.edu fault = new ArithmeticFault; 6198481Sgblack@eecs.umich.edu Fc = sqrt(Fb); 6208481Sgblack@eecs.umich.edu }}, FloatSqrtOp); 6218481Sgblack@eecs.umich.edu } 6228481Sgblack@eecs.umich.edu } 6238481Sgblack@eecs.umich.edu } 6248481Sgblack@eecs.umich.edu 6258481Sgblack@eecs.umich.edu // VAX-format sqrtf and sqrtg are not implemented 6268481Sgblack@eecs.umich.edu 0xa: FailUnimpl::sqrtfg(); 6278481Sgblack@eecs.umich.edu } 6288481Sgblack@eecs.umich.edu 6298481Sgblack@eecs.umich.edu // IEEE floating point 6308481Sgblack@eecs.umich.edu 0x16: decode FP_SHORTFUNC_TOP2 { 6318481Sgblack@eecs.umich.edu // The top two bits of the short function code break this 6328481Sgblack@eecs.umich.edu // space into four groups: binary ops, compares, reserved, and 6338481Sgblack@eecs.umich.edu // conversions. See Table 4-12 of AHB. There are different 6348481Sgblack@eecs.umich.edu // special cases in these different groups, so we decode on 6358481Sgblack@eecs.umich.edu // these top two bits first just to select a decode strategy. 6362292SN/A // Most of these instructions may have various trapping and 6372292SN/A // rounding mode flags set; these are decoded in the 6382292SN/A // FloatingPointDecode template used by the 6392292SN/A // FloatingPointOperate format. 6402292SN/A 6412292SN/A // add/sub/mul/div: just decode on the short function code 6422292SN/A // and source type. All valid trapping and rounding modes apply. 6432292SN/A 0: decode FP_TRAPMODE { 6442292SN/A // check for valid trapping modes here 6452292SN/A 0,1,5,7: decode FP_TYPEFUNC { 6462292SN/A format FloatingPointOperate { 6472292SN/A#if SS_COMPATIBLE_FP 6482292SN/A 0x00: adds({{ Fc = Fa + Fb; }}); 6492292SN/A 0x01: subs({{ Fc = Fa - Fb; }}); 6502292SN/A 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 6512292SN/A 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 6524032Sktlim@umich.edu#else 6534032Sktlim@umich.edu 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }}); 6544032Sktlim@umich.edu 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }}); 6554032Sktlim@umich.edu 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp); 6562292SN/A 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp); 6572292SN/A#endif 6582292SN/A 6592292SN/A 0x20: addt({{ Fc = Fa + Fb; }}); 6602669Sktlim@umich.edu 0x21: subt({{ Fc = Fa - Fb; }}); 6612292SN/A 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 6622669Sktlim@umich.edu 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 6632669Sktlim@umich.edu } 6642292SN/A } 6652669Sktlim@umich.edu } 6662292SN/A 6672292SN/A // Floating-point compare instructions must have the default 6682669Sktlim@umich.edu // rounding mode, and may use the default trapping mode or 6692669Sktlim@umich.edu // /SU. Both trapping modes are treated the same by M5; the 6702292SN/A // only difference on the real hardware (as far a I can tell) 6712292SN/A // is that without /SU you'd get an imprecise trap if you 6724032Sktlim@umich.edu // tried to compare a NaN with something else (instead of an 6732329SN/A // "unordered" result). 6748316Sgeoffrey.blake@arm.com 1: decode FP_FULLFUNC { 6752292SN/A format BasicOperateWithNopCheck { 6767520Sgblack@eecs.umich.edu 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 6777520Sgblack@eecs.umich.edu FloatCmpOp); 6783803Sgblack@eecs.umich.edu 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 6792669Sktlim@umich.edu FloatCmpOp); 6802669Sktlim@umich.edu 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 6812292SN/A FloatCmpOp); 6824326Sgblack@eecs.umich.edu 0x0a4, 0x5a4: cmptun({{ // unordered 6834326Sgblack@eecs.umich.edu Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 6842292SN/A }}, FloatCmpOp); 6852292SN/A } 6862292SN/A } 6872693Sktlim@umich.edu 6882678Sktlim@umich.edu // The FP-to-integer and integer-to-FP conversion insts 6898949Sandreas.hansson@arm.com // require that FA be 31. 6902678Sktlim@umich.edu 3: decode FA { 6912678Sktlim@umich.edu 31: decode FP_TYPEFUNC { 6922678Sktlim@umich.edu format FloatingPointOperate { 6932292SN/A 0x2f: decode FP_ROUNDMODE { 6942292SN/A format FPFixedRounding { 6952292SN/A // "chopped" i.e. round toward zero 6962292SN/A 0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }}, 6977823Ssteve.reinhardt@amd.com Chopped); 6982678Sktlim@umich.edu // round to minus infinity 6996974Stjones1@inf.ed.ac.uk 1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }}, 7006974Stjones1@inf.ed.ac.uk MinusInfinity); 7016974Stjones1@inf.ed.ac.uk } 7026974Stjones1@inf.ed.ac.uk default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }}); 7036974Stjones1@inf.ed.ac.uk } 7046974Stjones1@inf.ed.ac.uk 7052727Sktlim@umich.edu // The cvtts opcode is overloaded to be cvtst if the trap 7062292SN/A // mode is 2 or 6 (which are not valid otherwise) 7072292SN/A 0x2c: decode FP_FULLFUNC { 7082292SN/A format BasicOperateWithNopCheck { 7092292SN/A // trap on denorm version "cvtst/s" is 7102292SN/A // simulated same as cvtst 7112292SN/A 0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }}); 7122292SN/A } 7132292SN/A default: cvtts({{ Fc_sf = Fb; }}); 7142292SN/A } 7152292SN/A 7164032Sktlim@umich.edu // The trapping mode for integer-to-FP conversions 7172292SN/A // must be /SUI or nothing; /U and /SU are not 7182292SN/A // allowed. The full set of rounding modes are 7192292SN/A // supported though. 7202292SN/A 0x3c: decode FP_TRAPMODE { 7212292SN/A 0,7: cvtqs({{ Fc_sf = Fb_sq; }}); 7222292SN/A } 7232292SN/A 0x3e: decode FP_TRAPMODE { 7242669Sktlim@umich.edu 0,7: cvtqt({{ Fc = Fb_sq; }}); 7252292SN/A } 7262292SN/A } 7272292SN/A } 7282292SN/A } 7292292SN/A } 7302292SN/A 7312292SN/A // misc FP operate 7322292SN/A 0x17: decode FP_FULLFUNC { 7332669Sktlim@umich.edu format BasicOperateWithNopCheck { 7342927Sktlim@umich.edu 0x010: cvtlq({{ 7354032Sktlim@umich.edu Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>; 7362727Sktlim@umich.edu }}); 7372292SN/A 0x030: cvtql({{ 7382292SN/A Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29); 7392292SN/A }}); 7402292SN/A 7412292SN/A // We treat the precise & imprecise trapping versions of 7422669Sktlim@umich.edu // cvtql identically. 7432292SN/A 0x130, 0x530: cvtqlv({{ 7444032Sktlim@umich.edu // To avoid overflow, all the upper 32 bits must match 7454032Sktlim@umich.edu // the sign bit of the lower 32. We code this as 7464032Sktlim@umich.edu // checking the upper 33 bits for all 0s or all 1s. 7474032Sktlim@umich.edu uint64_t sign_bits = Fb_uq<63:31>; 7486974Stjones1@inf.ed.ac.uk if (sign_bits != 0 && sign_bits != mask(33)) 7496974Stjones1@inf.ed.ac.uk fault = new IntegerOverflowFault; 7506974Stjones1@inf.ed.ac.uk Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29); 7516974Stjones1@inf.ed.ac.uk }}); 7524032Sktlim@umich.edu 7532292SN/A 0x020: cpys({{ // copy sign 7542292SN/A Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>; 7552292SN/A }}); 7562292SN/A 0x021: cpysn({{ // copy sign negated 7572292SN/A Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>; 7587720Sgblack@eecs.umich.edu }}); 7597720Sgblack@eecs.umich.edu 0x022: cpyse({{ // copy sign and exponent 7602292SN/A Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>; 7612669Sktlim@umich.edu }}); 7622669Sktlim@umich.edu 7632292SN/A 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 7642292SN/A 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 7652292SN/A 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 7662907Sktlim@umich.edu 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 7676974Stjones1@inf.ed.ac.uk 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 7682907Sktlim@umich.edu 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 7696974Stjones1@inf.ed.ac.uk 7706974Stjones1@inf.ed.ac.uk 0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess); 7718949Sandreas.hansson@arm.com 0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess); 7726974Stjones1@inf.ed.ac.uk } 7736974Stjones1@inf.ed.ac.uk } 7746974Stjones1@inf.ed.ac.uk 7753228Sktlim@umich.edu // miscellaneous mem-format ops 7763228Sktlim@umich.edu 0x18: decode MEMFUNC { 7773228Sktlim@umich.edu format WarnUnimpl { 7783228Sktlim@umich.edu 0x8000: fetch(); 7793228Sktlim@umich.edu 0xa000: fetch_m(); 7803228Sktlim@umich.edu 0xe800: ecb(); 7813228Sktlim@umich.edu } 7823228Sktlim@umich.edu 7836974Stjones1@inf.ed.ac.uk format MiscPrefetch { 7846974Stjones1@inf.ed.ac.uk 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 7856974Stjones1@inf.ed.ac.uk {{ ; }}, 7866974Stjones1@inf.ed.ac.uk mem_flags = PREFETCH); 7876974Stjones1@inf.ed.ac.uk } 7886974Stjones1@inf.ed.ac.uk 7896974Stjones1@inf.ed.ac.uk format BasicOperate { 7908949Sandreas.hansson@arm.com 0xc000: rpcc({{ 7918949Sandreas.hansson@arm.com /* Rb is a fake dependency so here is a fun way to get 7926974Stjones1@inf.ed.ac.uk * the parser to understand that. 7936974Stjones1@inf.ed.ac.uk */ 7946974Stjones1@inf.ed.ac.uk uint64_t unused_var M5_VAR_USED = Rb; 7956974Stjones1@inf.ed.ac.uk Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick(); 7966974Stjones1@inf.ed.ac.uk }}, IsUnverifiable); 7976974Stjones1@inf.ed.ac.uk 7986974Stjones1@inf.ed.ac.uk // All of the barrier instructions below do nothing in 7996974Stjones1@inf.ed.ac.uk // their execute() methods (hence the empty code blocks). 8006974Stjones1@inf.ed.ac.uk // All of their functionality is hard-coded in the 8016974Stjones1@inf.ed.ac.uk // pipeline based on the flags IsSerializing, 8026974Stjones1@inf.ed.ac.uk // IsMemBarrier, and IsWriteBarrier. In the current 8036974Stjones1@inf.ed.ac.uk // detailed CPU model, the execute() function only gets 8048975Sandreas.hansson@arm.com // called at fetch, so there's no way to generate pipeline 8053228Sktlim@umich.edu // behavior at any other stage. Once we go to an 8063228Sktlim@umich.edu // exec-in-exec CPU model we should be able to get rid of 8073228Sktlim@umich.edu // these flags and implement this behavior via the 8084032Sktlim@umich.edu // execute() methods. 8093228Sktlim@umich.edu 8106974Stjones1@inf.ed.ac.uk // trapb is just a barrier on integer traps, where excb is 8116974Stjones1@inf.ed.ac.uk // a barrier on integer and FP traps. "EXCB is thus a 8126974Stjones1@inf.ed.ac.uk // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 8136974Stjones1@inf.ed.ac.uk // them the same though. 8146974Stjones1@inf.ed.ac.uk 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 8157511Stjones1@inf.ed.ac.uk 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 8167511Stjones1@inf.ed.ac.uk 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 8176974Stjones1@inf.ed.ac.uk 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 8183228Sktlim@umich.edu } 8194032Sktlim@umich.edu 8204032Sktlim@umich.edu 0xe000: decode FullSystemInt { 8212907Sktlim@umich.edu 0: FailUnimpl::rc_se(); 8222907Sktlim@umich.edu default: BasicOperate::rc({{ 8232907Sktlim@umich.edu Ra = IntrFlag; 8246974Stjones1@inf.ed.ac.uk IntrFlag = 0; 8256974Stjones1@inf.ed.ac.uk }}, IsNonSpeculative, IsUnverifiable); 8266974Stjones1@inf.ed.ac.uk } 8276974Stjones1@inf.ed.ac.uk 0xf000: decode FullSystemInt { 8286974Stjones1@inf.ed.ac.uk 0: FailUnimpl::rs_se(); 8296974Stjones1@inf.ed.ac.uk default: BasicOperate::rs({{ 8306974Stjones1@inf.ed.ac.uk Ra = IntrFlag; 8316974Stjones1@inf.ed.ac.uk IntrFlag = 1; 8326974Stjones1@inf.ed.ac.uk }}, IsNonSpeculative, IsUnverifiable); 8338975Sandreas.hansson@arm.com } 8346974Stjones1@inf.ed.ac.uk } 8356974Stjones1@inf.ed.ac.uk 8366974Stjones1@inf.ed.ac.uk 0x00: decode FullSystemInt { 8376974Stjones1@inf.ed.ac.uk 0: decode PALFUNC { 8386974Stjones1@inf.ed.ac.uk format EmulatedCallPal { 8396974Stjones1@inf.ed.ac.uk 0x00: halt ({{ 8406974Stjones1@inf.ed.ac.uk exitSimLoop("halt instruction encountered"); 8416974Stjones1@inf.ed.ac.uk }}, IsNonSpeculative); 8427511Stjones1@inf.ed.ac.uk 0x83: callsys({{ 8436974Stjones1@inf.ed.ac.uk xc->syscall(R0); 8446974Stjones1@inf.ed.ac.uk }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 8456974Stjones1@inf.ed.ac.uk // Read uniq reg into ABI return value register (r0) 8462907Sktlim@umich.edu 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); 8472907Sktlim@umich.edu // Write uniq reg with value from ABI arg register (r16) 8482907Sktlim@umich.edu 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess); 8492907Sktlim@umich.edu } 8502907Sktlim@umich.edu } 8512907Sktlim@umich.edu default: CallPal::call_pal({{ 8524032Sktlim@umich.edu if (!palValid || 8534032Sktlim@umich.edu (palPriv 8546974Stjones1@inf.ed.ac.uk && xc->readMiscReg(IPR_ICM) != mode_kernel)) { 8556974Stjones1@inf.ed.ac.uk // invalid pal function code, or attempt to do privileged 8566974Stjones1@inf.ed.ac.uk // PAL call in non-kernel mode 8576974Stjones1@inf.ed.ac.uk fault = new UnimplementedOpcodeFault; 8584032Sktlim@umich.edu } else { 8592727Sktlim@umich.edu // check to see if simulator wants to do something special 8603014Srdreslin@umich.edu // on this PAL call (including maybe suppress it) 8618315Sgeoffrey.blake@arm.com bool dopal = xc->simPalCheck(palFunc); 8628315Sgeoffrey.blake@arm.com 8638315Sgeoffrey.blake@arm.com if (dopal) { 8648315Sgeoffrey.blake@arm.com xc->setMiscReg(IPR_EXC_ADDR, NPC); 8658315Sgeoffrey.blake@arm.com NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset; 8668315Sgeoffrey.blake@arm.com } 8672669Sktlim@umich.edu } 8682669Sktlim@umich.edu }}, IsNonSpeculative); 8692669Sktlim@umich.edu } 8702292SN/A 8712669Sktlim@umich.edu 0x1b: decode PALMODE { 8722669Sktlim@umich.edu 0: OpcdecFault::hw_st_quad(); 8732669Sktlim@umich.edu 1: decode HW_LDST_QUAD { 8742669Sktlim@umich.edu format HwLoad { 8752669Sktlim@umich.edu 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }}, 8762669Sktlim@umich.edu L, IsSerializing, IsSerializeBefore); 8772669Sktlim@umich.edu 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }}, 8782669Sktlim@umich.edu Q, IsSerializing, IsSerializeBefore); 8792292SN/A } 8802292SN/A } 8812669Sktlim@umich.edu } 8822292SN/A 8832292SN/A 0x1f: decode PALMODE { 8842292SN/A 0: OpcdecFault::hw_st_cond(); 8852292SN/A format HwStore { 8866974Stjones1@inf.ed.ac.uk 1: decode HW_LDST_COND { 8877520Sgblack@eecs.umich.edu 0: decode HW_LDST_QUAD { 8882292SN/A 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 8892292SN/A {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore); 8902292SN/A 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 8912292SN/A {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore); 8922292SN/A } 8932669Sktlim@umich.edu 8942292SN/A 1: FailUnimpl::hw_st_cond(); 8952329SN/A } 8962292SN/A } 8976974Stjones1@inf.ed.ac.uk } 8986974Stjones1@inf.ed.ac.uk 8997520Sgblack@eecs.umich.edu 0x19: decode PALMODE { 9007520Sgblack@eecs.umich.edu 0: OpcdecFault::hw_mfpr(); 9017520Sgblack@eecs.umich.edu format HwMoveIPR { 9027509Stjones1@inf.ed.ac.uk 1: hw_mfpr({{ 9037509Stjones1@inf.ed.ac.uk int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 9047509Stjones1@inf.ed.ac.uk IprToMiscRegIndex[ipr_index] : -1; 9057509Stjones1@inf.ed.ac.uk if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || 9067509Stjones1@inf.ed.ac.uk miscRegIndex >= NumInternalProcRegs) 9077509Stjones1@inf.ed.ac.uk fault = new UnimplementedOpcodeFault; 9084326Sgblack@eecs.umich.edu else 9097520Sgblack@eecs.umich.edu Ra = xc->readMiscReg(miscRegIndex); 9102329SN/A }}, IsIprAccess); 9112292SN/A } 9122292SN/A } 9132292SN/A 9142292SN/A 0x1d: decode PALMODE { 9152292SN/A 0: OpcdecFault::hw_mtpr(); 9162292SN/A format HwMoveIPR { 917 1: hw_mtpr({{ 918 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 919 IprToMiscRegIndex[ipr_index] : -1; 920 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) || 921 miscRegIndex >= NumInternalProcRegs) 922 fault = new UnimplementedOpcodeFault; 923 else 924 xc->setMiscReg(miscRegIndex, Ra); 925 if (traceData) { traceData->setData(Ra); } 926 }}, IsIprAccess); 927 } 928 } 929 930 0x1e: decode PALMODE { 931 0: OpcdecFault::hw_rei(); 932 format BasicOperate { 933 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); 934 } 935 } 936 937 format BasicOperate { 938 // M5 special opcodes use the reserved 0x01 opcode space 939 0x01: decode M5FUNC { 940 0x00: arm({{ 941 PseudoInst::arm(xc->tcBase()); 942 }}, IsNonSpeculative); 943 0x01: quiesce({{ 944 // Don't sleep if (unmasked) interrupts are pending 945 Interrupts* interrupts = 946 xc->tcBase()->getCpuPtr()->getInterruptController(); 947 if (interrupts->checkInterrupts(xc->tcBase())) { 948 PseudoInst::quiesceSkip(xc->tcBase()); 949 } else { 950 PseudoInst::quiesce(xc->tcBase()); 951 } 952 }}, IsNonSpeculative, IsQuiesce); 953 0x02: quiesceNs({{ 954 PseudoInst::quiesceNs(xc->tcBase(), R16); 955 }}, IsNonSpeculative, IsQuiesce); 956 0x03: quiesceCycles({{ 957 PseudoInst::quiesceCycles(xc->tcBase(), R16); 958 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 959 0x04: quiesceTime({{ 960 R0 = PseudoInst::quiesceTime(xc->tcBase()); 961 }}, IsNonSpeculative, IsUnverifiable); 962 0x07: rpns({{ 963 R0 = PseudoInst::rpns(xc->tcBase()); 964 }}, IsNonSpeculative, IsUnverifiable); 965 0x09: wakeCPU({{ 966 PseudoInst::wakeCPU(xc->tcBase(), R16); 967 }}, IsNonSpeculative, IsUnverifiable); 968 0x10: deprecated_ivlb({{ 969 warn_once("Obsolete M5 ivlb instruction encountered.\n"); 970 }}); 971 0x11: deprecated_ivle({{ 972 warn_once("Obsolete M5 ivlb instruction encountered.\n"); 973 }}); 974 0x20: deprecated_exit ({{ 975 warn_once("deprecated M5 exit instruction encountered.\n"); 976 PseudoInst::m5exit(xc->tcBase(), 0); 977 }}, No_OpClass, IsNonSpeculative); 978 0x21: m5exit({{ 979 PseudoInst::m5exit(xc->tcBase(), R16); 980 }}, No_OpClass, IsNonSpeculative); 981 0x31: loadsymbol({{ 982 PseudoInst::loadsymbol(xc->tcBase()); 983 }}, No_OpClass, IsNonSpeculative); 984 0x30: initparam({{ 985 Ra = PseudoInst::initParam(xc->tcBase()); 986 }}); 987 0x40: resetstats({{ 988 PseudoInst::resetstats(xc->tcBase(), R16, R17); 989 }}, IsNonSpeculative); 990 0x41: dumpstats({{ 991 PseudoInst::dumpstats(xc->tcBase(), R16, R17); 992 }}, IsNonSpeculative); 993 0x42: dumpresetstats({{ 994 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17); 995 }}, IsNonSpeculative); 996 0x43: m5checkpoint({{ 997 PseudoInst::m5checkpoint(xc->tcBase(), R16, R17); 998 }}, IsNonSpeculative); 999 0x50: m5readfile({{ 1000 R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18); 1001 }}, IsNonSpeculative); 1002 0x51: m5break({{ 1003 PseudoInst::debugbreak(xc->tcBase()); 1004 }}, IsNonSpeculative); 1005 0x52: m5switchcpu({{ 1006 PseudoInst::switchcpu(xc->tcBase()); 1007 }}, IsNonSpeculative); 1008 0x53: m5addsymbol({{ 1009 PseudoInst::addsymbol(xc->tcBase(), R16, R17); 1010 }}, IsNonSpeculative); 1011 0x54: m5panic({{ 1012 panic("M5 panic instruction called at pc = %#x.", PC); 1013 }}, IsNonSpeculative); 1014#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase()) 1015 0x55: decode RA { 1016 0x00: m5a_old({{ 1017 panic("Deprecated M5 annotate instruction executed " 1018 "at pc = %#x\n", PC); 1019 }}, IsNonSpeculative); 1020 0x01: m5a_bsm({{ 1021 CPANN(swSmBegin); 1022 }}, IsNonSpeculative); 1023 0x02: m5a_esm({{ 1024 CPANN(swSmEnd); 1025 }}, IsNonSpeculative); 1026 0x03: m5a_begin({{ 1027 CPANN(swExplictBegin); 1028 }}, IsNonSpeculative); 1029 0x04: m5a_end({{ 1030 CPANN(swEnd); 1031 }}, IsNonSpeculative); 1032 0x06: m5a_q({{ 1033 CPANN(swQ); 1034 }}, IsNonSpeculative); 1035 0x07: m5a_dq({{ 1036 CPANN(swDq); 1037 }}, IsNonSpeculative); 1038 0x08: m5a_wf({{ 1039 CPANN(swWf); 1040 }}, IsNonSpeculative); 1041 0x09: m5a_we({{ 1042 CPANN(swWe); 1043 }}, IsNonSpeculative); 1044 0x0C: m5a_sq({{ 1045 CPANN(swSq); 1046 }}, IsNonSpeculative); 1047 0x0D: m5a_aq({{ 1048 CPANN(swAq); 1049 }}, IsNonSpeculative); 1050 0x0E: m5a_pq({{ 1051 CPANN(swPq); 1052 }}, IsNonSpeculative); 1053 0x0F: m5a_l({{ 1054 CPANN(swLink); 1055 }}, IsNonSpeculative); 1056 0x10: m5a_identify({{ 1057 CPANN(swIdentify); 1058 }}, IsNonSpeculative); 1059 0x11: m5a_getid({{ 1060 R0 = CPANN(swGetId); 1061 }}, IsNonSpeculative); 1062 0x13: m5a_scl({{ 1063 CPANN(swSyscallLink); 1064 }}, IsNonSpeculative); 1065 0x14: m5a_rq({{ 1066 CPANN(swRq); 1067 }}, IsNonSpeculative); 1068 } // M5 Annotate Operations 1069#undef CPANN 1070 0x56: m5reserved2({{ 1071 warn("M5 reserved opcode ignored"); 1072 }}, IsNonSpeculative); 1073 0x57: m5reserved3({{ 1074 warn("M5 reserved opcode ignored"); 1075 }}, IsNonSpeculative); 1076 0x58: m5reserved4({{ 1077 warn("M5 reserved opcode ignored"); 1078 }}, IsNonSpeculative); 1079 0x59: m5reserved5({{ 1080 warn("M5 reserved opcode ignored"); 1081 }}, IsNonSpeculative); 1082 } 1083 } 1084} 1085