decoder.isa revision 7794:8a7ba5a1b35d
19243SN/A// -*- mode:c++ -*- 211846Swendy.elsasser@arm.com 39243SN/A// Copyright (c) 2003-2006 The Regents of The University of Michigan 49243SN/A// All rights reserved. 59243SN/A// 69243SN/A// Redistribution and use in source and binary forms, with or without 79243SN/A// modification, are permitted provided that the following conditions are 89243SN/A// met: redistributions of source code must retain the above copyright 99243SN/A// notice, this list of conditions and the following disclaimer; 109243SN/A// redistributions in binary form must reproduce the above copyright 119243SN/A// notice, this list of conditions and the following disclaimer in the 129243SN/A// documentation and/or other materials provided with the distribution; 139243SN/A// neither the name of the copyright holders nor the names of its 149831SN/A// contributors may be used to endorse or promote products derived from 159831SN/A// this software without specific prior written permission. 169831SN/A// 179243SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 189243SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 199243SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 209243SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 219243SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 229243SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 239243SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 249243SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 259243SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 269243SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 279243SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 289243SN/A// 299243SN/A// Authors: Steve Reinhardt 309243SN/A 319243SN/A//////////////////////////////////////////////////////////////////// 329243SN/A// 339243SN/A// The actual decoder specification 349243SN/A// 359243SN/A 369243SN/Adecode OPCODE default Unknown::unknown() { 379243SN/A 389243SN/A format LoadAddress { 399243SN/A 0x08: lda({{ Ra = Rb + disp; }}); 409243SN/A 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 419243SN/A } 429967SN/A 4310618SOmar.Naji@arm.com format LoadOrNop { 4411678Swendy.elsasser@arm.com 0x0a: ldbu({{ Ra.uq = Mem.ub; }}); 4512266Sradhika.jagtap@arm.com 0x0c: ldwu({{ Ra.uq = Mem.uw; }}); 469243SN/A 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 479243SN/A 0x23: ldt({{ Fa = Mem.df; }}); 4811793Sbrandon.potter@amd.com 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC); 4911793Sbrandon.potter@amd.com 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC); 5010146Sandreas.hansson@arm.com } 519356SN/A 5210146Sandreas.hansson@arm.com format LoadOrPrefetch { 5310247Sandreas.hansson@arm.com 0x28: ldl({{ Ra.sl = Mem.sl; }}); 5410208Sandreas.hansson@arm.com 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT); 559352SN/A // IsFloating flag on lds gets the prefetch to disassemble 569814SN/A // using f31 instead of r31... funcitonally it's unnecessary 579243SN/A 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }}, 589243SN/A pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 5910432SOmar.Naji@arm.com } 609243SN/A 6110146Sandreas.hansson@arm.com format Store { 629243SN/A 0x0e: stb({{ Mem.ub = Ra<7:0>; }}); 6310619Sandreas.hansson@arm.com 0x0d: stw({{ Mem.uw = Ra<15:0>; }}); 649243SN/A 0x2c: stl({{ Mem.ul = Ra<31:0>; }}); 6510211Sandreas.hansson@arm.com 0x2d: stq({{ Mem.uq = Ra.uq; }}); 6611678Swendy.elsasser@arm.com 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 6712084Sspwilson2@wisc.edu 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 6812084Sspwilson2@wisc.edu 0x27: stt({{ Mem.df = Fa; }}); 6910489SOmar.Naji@arm.com } 709831SN/A 719831SN/A format StoreCond { 729831SN/A 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }}, 739831SN/A {{ 749831SN/A uint64_t tmp = write_result; 7510140SN/A // see stq_c 7610646Sandreas.hansson@arm.com Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 779243SN/A if (tmp == 1) { 7810394Swendy.elsasser@arm.com xc->setStCondFailures(0); 7910394Swendy.elsasser@arm.com } 809566SN/A }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 819243SN/A 0x2f: stq_c({{ Mem.uq = Ra; }}, 829243SN/A {{ 8310140SN/A uint64_t tmp = write_result; 8410140SN/A // If the write operation returns 0 or 1, then 8510147Sandreas.hansson@arm.com // this was a conventional store conditional, 8610147Sandreas.hansson@arm.com // and the value indicates the success/failure 8710393Swendy.elsasser@arm.com // of the operation. If another value is 8810394Swendy.elsasser@arm.com // returned, then this was a Turbolaser 8910394Swendy.elsasser@arm.com // mailbox access, and we don't update the 9011673SOmar.Naji@arm.com // result register at all. 9111673SOmar.Naji@arm.com Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 929243SN/A if (tmp == 1) { 939243SN/A // clear failure counter... this is 9410141SN/A // non-architectural and for debugging 959726SN/A // only. 969726SN/A xc->setStCondFailures(0); 9710618SOmar.Naji@arm.com } 9812266Sradhika.jagtap@arm.com }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 9912266Sradhika.jagtap@arm.com } 1009243SN/A 10110620Sandreas.hansson@arm.com format IntegerOperate { 10210620Sandreas.hansson@arm.com 10310620Sandreas.hansson@arm.com 0x10: decode INTFUNC { // integer arithmetic operations 10410620Sandreas.hansson@arm.com 10510620Sandreas.hansson@arm.com 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 10610889Sandreas.hansson@arm.com 0x40: addlv({{ 10710889Sandreas.hansson@arm.com int32_t tmp = Ra.sl + Rb_or_imm.sl; 10810889Sandreas.hansson@arm.com // signed overflow occurs when operands have same sign 10910618SOmar.Naji@arm.com // and sign of result does not match. 11012081Sspwilson2@wisc.edu if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 11110618SOmar.Naji@arm.com fault = new IntegerOverflowFault; 11210246Sandreas.hansson@arm.com Rc.sl = tmp; 11310246Sandreas.hansson@arm.com }}); 11410140SN/A 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); 11510140SN/A 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }}); 11610140SN/A 11710140SN/A 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 11810140SN/A 0x60: addqv({{ 1199243SN/A uint64_t tmp = Ra + Rb_or_imm; 1209243SN/A // signed overflow occurs when operands have same sign 1219567SN/A // and sign of result does not match. 1229243SN/A if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 12310489SOmar.Naji@arm.com fault = new IntegerOverflowFault; 12410489SOmar.Naji@arm.com Rc = tmp; 12510489SOmar.Naji@arm.com }}); 12610489SOmar.Naji@arm.com 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 12710489SOmar.Naji@arm.com 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 12810489SOmar.Naji@arm.com 12910489SOmar.Naji@arm.com 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }}); 13010489SOmar.Naji@arm.com 0x49: sublv({{ 13110489SOmar.Naji@arm.com int32_t tmp = Ra.sl - Rb_or_imm.sl; 13210489SOmar.Naji@arm.com // signed overflow detection is same as for add, 1339243SN/A // except we need to look at the *complemented* 1349243SN/A // sign bit of the subtrahend (Rb), i.e., if the initial 1359831SN/A // signs are the *same* then no overflow can occur 1369831SN/A if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1379831SN/A fault = new IntegerOverflowFault; 1389831SN/A Rc.sl = tmp; 1399831SN/A }}); 1409243SN/A 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); 14110207Sandreas.hansson@arm.com 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }}); 14210207Sandreas.hansson@arm.com 14310207Sandreas.hansson@arm.com 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 14410207Sandreas.hansson@arm.com 0x69: subqv({{ 14510207Sandreas.hansson@arm.com uint64_t tmp = Ra - Rb_or_imm; 14610394Swendy.elsasser@arm.com // signed overflow detection is same as for add, 14710394Swendy.elsasser@arm.com // except we need to look at the *complemented* 14810394Swendy.elsasser@arm.com // sign bit of the subtrahend (Rb), i.e., if the initial 14910394Swendy.elsasser@arm.com // signs are the *same* then no overflow can occur 15010394Swendy.elsasser@arm.com if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 15110394Swendy.elsasser@arm.com fault = new IntegerOverflowFault; 15210394Swendy.elsasser@arm.com Rc = tmp; 15310394Swendy.elsasser@arm.com }}); 15410394Swendy.elsasser@arm.com 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 15510394Swendy.elsasser@arm.com 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 15610394Swendy.elsasser@arm.com 15710394Swendy.elsasser@arm.com 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 15810394Swendy.elsasser@arm.com 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }}); 15910394Swendy.elsasser@arm.com 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }}); 16010394Swendy.elsasser@arm.com 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }}); 16110394Swendy.elsasser@arm.com 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }}); 16210394Swendy.elsasser@arm.com 16310394Swendy.elsasser@arm.com 0x0f: cmpbge({{ 16410394Swendy.elsasser@arm.com int hi = 7; 16510394Swendy.elsasser@arm.com int lo = 0; 16610394Swendy.elsasser@arm.com uint64_t tmp = 0; 16710394Swendy.elsasser@arm.com for (int i = 0; i < 8; ++i) { 16810561SOmar.Naji@arm.com tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i; 16910561SOmar.Naji@arm.com hi += 8; 17010394Swendy.elsasser@arm.com lo += 8; 17110394Swendy.elsasser@arm.com } 17210394Swendy.elsasser@arm.com Rc = tmp; 17310394Swendy.elsasser@arm.com }}); 17410394Swendy.elsasser@arm.com } 17510394Swendy.elsasser@arm.com 1769243SN/A 0x11: decode INTFUNC { // integer logical operations 1779243SN/A 1789243SN/A 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 17910146Sandreas.hansson@arm.com 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 18010140SN/A 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 18110466Sandreas.hansson@arm.com 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 18210466Sandreas.hansson@arm.com 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 18310466Sandreas.hansson@arm.com 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 18410146Sandreas.hansson@arm.com 18510140SN/A // conditional moves 18610140SN/A 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 18710140SN/A 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 18810646Sandreas.hansson@arm.com 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 18910646Sandreas.hansson@arm.com 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 19010646Sandreas.hansson@arm.com 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }}); 19110646Sandreas.hansson@arm.com 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }}); 19210646Sandreas.hansson@arm.com 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }}); 19310646Sandreas.hansson@arm.com 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }}); 19410646Sandreas.hansson@arm.com 19510646Sandreas.hansson@arm.com // For AMASK, RA must be R31. 19610646Sandreas.hansson@arm.com 0x61: decode RA { 19710646Sandreas.hansson@arm.com 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 19810646Sandreas.hansson@arm.com } 19910646Sandreas.hansson@arm.com 20010646Sandreas.hansson@arm.com // For IMPLVER, RA must be R31 and the B operand 20110646Sandreas.hansson@arm.com // must be the immediate value 1. 20210646Sandreas.hansson@arm.com 0x6c: decode RA { 20310646Sandreas.hansson@arm.com 31: decode IMM { 20410646Sandreas.hansson@arm.com 1: decode INTIMM { 20510646Sandreas.hansson@arm.com // return EV5 for FULL_SYSTEM and EV6 otherwise 20610646Sandreas.hansson@arm.com 1: implver({{ 20710646Sandreas.hansson@arm.com#if FULL_SYSTEM 20810646Sandreas.hansson@arm.com Rc = 1; 20910646Sandreas.hansson@arm.com#else 21010646Sandreas.hansson@arm.com Rc = 2; 21110646Sandreas.hansson@arm.com#endif 21210646Sandreas.hansson@arm.com }}); 21310646Sandreas.hansson@arm.com } 21410646Sandreas.hansson@arm.com } 21510646Sandreas.hansson@arm.com } 21610646Sandreas.hansson@arm.com 21710646Sandreas.hansson@arm.com#if FULL_SYSTEM 21810646Sandreas.hansson@arm.com // The mysterious 11.25... 21910646Sandreas.hansson@arm.com 0x25: WarnUnimpl::eleven25(); 22010646Sandreas.hansson@arm.com#endif 22110646Sandreas.hansson@arm.com } 22210646Sandreas.hansson@arm.com 22310646Sandreas.hansson@arm.com 0x12: decode INTFUNC { 22410646Sandreas.hansson@arm.com 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 22510646Sandreas.hansson@arm.com 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }}); 22610646Sandreas.hansson@arm.com 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }}); 22710646Sandreas.hansson@arm.com 22810140SN/A 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 22910140SN/A 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 23010140SN/A 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 23110146Sandreas.hansson@arm.com 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 2329243SN/A 23310619Sandreas.hansson@arm.com 0x52: mskwh({{ 23410619Sandreas.hansson@arm.com int bv = Rb_or_imm<2:0>; 23510618SOmar.Naji@arm.com Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 23610619Sandreas.hansson@arm.com }}); 23710619Sandreas.hansson@arm.com 0x62: msklh({{ 23810619Sandreas.hansson@arm.com int bv = Rb_or_imm<2:0>; 23910619Sandreas.hansson@arm.com Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 24010619Sandreas.hansson@arm.com }}); 24110619Sandreas.hansson@arm.com 0x72: mskqh({{ 24210619Sandreas.hansson@arm.com int bv = Rb_or_imm<2:0>; 24310619Sandreas.hansson@arm.com Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 24410619Sandreas.hansson@arm.com }}); 24510619Sandreas.hansson@arm.com 24610619Sandreas.hansson@arm.com 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 24710619Sandreas.hansson@arm.com 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 24810619Sandreas.hansson@arm.com 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 24910619Sandreas.hansson@arm.com 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }}); 25010619Sandreas.hansson@arm.com 25110618SOmar.Naji@arm.com 0x5a: extwh({{ 2529243SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 2539243SN/A 0x6a: extlh({{ 2549243SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 25510146Sandreas.hansson@arm.com 0x7a: extqh({{ 2569243SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 2579243SN/A 2589243SN/A 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 25911334Sandreas.hansson@arm.com 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 26011334Sandreas.hansson@arm.com 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 26111334Sandreas.hansson@arm.com 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 2629243SN/A 2639243SN/A 0x57: inswh({{ 2649243SN/A int bv = Rb_or_imm<2:0>; 2659243SN/A Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0; 26611334Sandreas.hansson@arm.com }}); 2679243SN/A 0x67: inslh({{ 2689243SN/A int bv = Rb_or_imm<2:0>; 2699243SN/A Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0; 2709243SN/A }}); 2719243SN/A 0x77: insqh({{ 2729243SN/A int bv = Rb_or_imm<2:0>; 2739243SN/A Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0; 2749243SN/A }}); 27510146Sandreas.hansson@arm.com 2769243SN/A 0x30: zap({{ 2779831SN/A uint64_t zapmask = 0; 2789831SN/A for (int i = 0; i < 8; ++i) { 2799831SN/A if (Rb_or_imm<i:>) 2809243SN/A zapmask |= (mask(8) << (i * 8)); 2819831SN/A } 2829831SN/A Rc = Ra & ~zapmask; 2839243SN/A }}); 2849243SN/A 0x31: zapnot({{ 2859243SN/A uint64_t zapmask = 0; 28610146Sandreas.hansson@arm.com for (int i = 0; i < 8; ++i) { 2879243SN/A if (!Rb_or_imm<i:>) 2889831SN/A zapmask |= (mask(8) << (i * 8)); 2899831SN/A } 2909831SN/A Rc = Ra & ~zapmask; 2919243SN/A }}); 2929243SN/A } 29310146Sandreas.hansson@arm.com 29410146Sandreas.hansson@arm.com 0x13: decode INTFUNC { // integer multiplies 29510143SN/A 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 2969243SN/A 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 2979669SN/A 0x30: umulh({{ 29810136SN/A uint64_t hi, lo; 29910136SN/A mul128(Ra, Rb_or_imm, hi, lo); 3009243SN/A Rc = hi; 3019967SN/A }}, IntMultOp); 30210245Sandreas.hansson@arm.com 0x40: mullv({{ 30310245Sandreas.hansson@arm.com // 32-bit multiply with trap on overflow 30410245Sandreas.hansson@arm.com int64_t Rax = Ra.sl; // sign extended version of Ra.sl 3059243SN/A int64_t Rbx = Rb_or_imm.sl; 30610286Sandreas.hansson@arm.com int64_t tmp = Rax * Rbx; 30710286Sandreas.hansson@arm.com // To avoid overflow, all the upper 32 bits must match 3089831SN/A // the sign bit of the lower 32. We code this as 3099243SN/A // checking the upper 33 bits for all 0s or all 1s. 3109491SN/A uint64_t sign_bits = tmp<63:31>; 3119831SN/A if (sign_bits != 0 && sign_bits != mask(33)) 31210136SN/A fault = new IntegerOverflowFault; 3139491SN/A Rc.sl = tmp<31:0>; 3149491SN/A }}, IntMultOp); 3159831SN/A 0x60: mulqv({{ 3169243SN/A // 64-bit multiply with trap on overflow 3179669SN/A uint64_t hi, lo; 3189566SN/A mul128(Ra, Rb_or_imm, hi, lo); 3199566SN/A // all the upper 64 bits must match the sign bit of 3209669SN/A // the lower 64 3219669SN/A if (!((hi == 0 && lo<63:> == 0) || 3229669SN/A (hi == mask(64) && lo<63:> == 1))) 3239669SN/A fault = new IntegerOverflowFault; 3249669SN/A Rc = lo; 3259669SN/A }}, IntMultOp); 3269669SN/A } 3279669SN/A 3289669SN/A 0x1c: decode INTFUNC { 3299669SN/A 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 33011189Sandreas.hansson@arm.com 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } 3319669SN/A 33210136SN/A 0x30: ctpop({{ 33310286Sandreas.hansson@arm.com uint64_t count = 0; 33410286Sandreas.hansson@arm.com for (int i = 0; Rb<63:i>; ++i) { 33510286Sandreas.hansson@arm.com if (Rb<i:i> == 0x1) 3369669SN/A ++count; 3379669SN/A } 3389669SN/A Rc = count; 33910286Sandreas.hansson@arm.com }}, IntAluOp); 34010286Sandreas.hansson@arm.com 3419669SN/A 0x31: perr({{ 3429669SN/A uint64_t temp = 0; 3439491SN/A int hi = 7; 3449243SN/A int lo = 0; 3459243SN/A for (int i = 0; i < 8; ++i) { 3469243SN/A uint8_t ra_ub = Ra.uq<hi:lo>; 3479491SN/A uint8_t rb_ub = Rb.uq<hi:lo>; 3489491SN/A temp += (ra_ub >= rb_ub) ? 3499243SN/A (ra_ub - rb_ub) : (rb_ub - ra_ub); 3509243SN/A hi += 8; 3519243SN/A lo += 8; 35211189Sandreas.hansson@arm.com } 3539243SN/A Rc = temp; 35410136SN/A }}); 3559491SN/A 3569491SN/A 0x32: ctlz({{ 3579491SN/A uint64_t count = 0; 35810286Sandreas.hansson@arm.com uint64_t temp = Rb; 35910286Sandreas.hansson@arm.com if (temp<63:32>) temp >>= 32; else count += 32; 36010286Sandreas.hansson@arm.com if (temp<31:16>) temp >>= 16; else count += 16; 3619566SN/A if (temp<15:8>) temp >>= 8; else count += 8; 3629566SN/A if (temp<7:4>) temp >>= 4; else count += 4; 3639566SN/A if (temp<3:2>) temp >>= 2; else count += 2; 3649566SN/A if (temp<1:1>) temp >>= 1; else count += 1; 3659566SN/A if ((temp<0:0>) != 0x1) count += 1; 3669491SN/A Rc = count; 3679491SN/A }}, IntAluOp); 3689243SN/A 3699243SN/A 0x33: cttz({{ 3709243SN/A uint64_t count = 0; 3719491SN/A uint64_t temp = Rb; 3729243SN/A if (!(temp<31:0>)) { temp >>= 32; count += 32; } 3739243SN/A if (!(temp<15:0>)) { temp >>= 16; count += 16; } 3749243SN/A if (!(temp<7:0>)) { temp >>= 8; count += 8; } 37510286Sandreas.hansson@arm.com if (!(temp<3:0>)) { temp >>= 4; count += 4; } 37610286Sandreas.hansson@arm.com if (!(temp<1:0>)) { temp >>= 2; count += 2; } 3779243SN/A if (!(temp<0:0> & ULL(0x1))) { 37811189Sandreas.hansson@arm.com temp >>= 1; count += 1; 3799243SN/A } 3809243SN/A if (!(temp<0:0> & ULL(0x1))) count += 1; 3819243SN/A Rc = count; 3829243SN/A }}, IntAluOp); 3839243SN/A 3849243SN/A 3859243SN/A 0x34: unpkbw({{ 38610245Sandreas.hansson@arm.com Rc = (Rb.uq<7:0> 3879243SN/A | (Rb.uq<15:8> << 16) 3889243SN/A | (Rb.uq<23:16> << 32) 3899831SN/A | (Rb.uq<31:24> << 48)); 3909243SN/A }}, IntAluOp); 3919243SN/A 3929567SN/A 0x35: unpkbl({{ 3939567SN/A Rc = (Rb.uq<7:0> | (Rb.uq<15:8> << 32)); 3949967SN/A }}, IntAluOp); 3959967SN/A 39610618SOmar.Naji@arm.com 0x36: pkwb({{ 3979243SN/A Rc = (Rb.uq<7:0> 3989243SN/A | (Rb.uq<23:16> << 8) 3999243SN/A | (Rb.uq<39:32> << 16) 40010146Sandreas.hansson@arm.com | (Rb.uq<55:48> << 24)); 4019243SN/A }}, IntAluOp); 4029243SN/A 4039243SN/A 0x37: pklb({{ 4049243SN/A Rc = (Rb.uq<7:0> | (Rb.uq<39:32> << 8)); 4059243SN/A }}, IntAluOp); 4069831SN/A 4079831SN/A 0x38: minsb8({{ 4089831SN/A uint64_t temp = 0; 4099831SN/A int hi = 63; 4109831SN/A int lo = 56; 4119831SN/A for (int i = 7; i >= 0; --i) { 4129831SN/A int8_t ra_sb = Ra.uq<hi:lo>; 4139831SN/A int8_t rb_sb = Rb.uq<hi:lo>; 4149243SN/A temp = ((temp << 8) 4159831SN/A | ((ra_sb < rb_sb) ? Ra.uq<hi:lo> 4169831SN/A : Rb.uq<hi:lo>)); 4179831SN/A hi -= 8; 4189831SN/A lo -= 8; 4199831SN/A } 4209831SN/A Rc = temp; 4219831SN/A }}); 4229243SN/A 4239831SN/A 0x39: minsw4({{ 4249831SN/A uint64_t temp = 0; 4259831SN/A int hi = 63; 42610889Sandreas.hansson@arm.com int lo = 48; 42710889Sandreas.hansson@arm.com for (int i = 3; i >= 0; --i) { 42810889Sandreas.hansson@arm.com int16_t ra_sw = Ra.uq<hi:lo>; 42910889Sandreas.hansson@arm.com int16_t rb_sw = Rb.uq<hi:lo>; 43010889Sandreas.hansson@arm.com temp = ((temp << 16) 43110889Sandreas.hansson@arm.com | ((ra_sw < rb_sw) ? Ra.uq<hi:lo> 43210889Sandreas.hansson@arm.com : Rb.uq<hi:lo>)); 43310889Sandreas.hansson@arm.com hi -= 16; 43410889Sandreas.hansson@arm.com lo -= 16; 43510889Sandreas.hansson@arm.com } 43610889Sandreas.hansson@arm.com Rc = temp; 43710889Sandreas.hansson@arm.com }}); 43810889Sandreas.hansson@arm.com 43910889Sandreas.hansson@arm.com 0x3a: minub8({{ 44010889Sandreas.hansson@arm.com uint64_t temp = 0; 44110889Sandreas.hansson@arm.com int hi = 63; 4429831SN/A int lo = 56; 4439243SN/A for (int i = 7; i >= 0; --i) { 4449831SN/A uint8_t ra_ub = Ra.uq<hi:lo>; 4459831SN/A uint8_t rb_ub = Rb.uq<hi:lo>; 4469831SN/A temp = ((temp << 8) 4479831SN/A | ((ra_ub < rb_ub) ? Ra.uq<hi:lo> 4489831SN/A : Rb.uq<hi:lo>)); 4499831SN/A hi -= 8; 4509831SN/A lo -= 8; 4519831SN/A } 4529831SN/A Rc = temp; 4539831SN/A }}); 4549831SN/A 4559831SN/A 0x3b: minuw4({{ 4569966SN/A uint64_t temp = 0; 4579831SN/A int hi = 63; 4589831SN/A int lo = 48; 4599831SN/A for (int i = 3; i >= 0; --i) { 4609831SN/A uint16_t ra_sw = Ra.uq<hi:lo>; 4619831SN/A uint16_t rb_sw = Rb.uq<hi:lo>; 4629831SN/A temp = ((temp << 16) 4639831SN/A | ((ra_sw < rb_sw) ? Ra.uq<hi:lo> 4649831SN/A : Rb.uq<hi:lo>)); 4659831SN/A hi -= 16; 46611678Swendy.elsasser@arm.com lo -= 16; 46711678Swendy.elsasser@arm.com } 46811678Swendy.elsasser@arm.com Rc = temp; 4699831SN/A }}); 4709831SN/A 4719831SN/A 0x3c: maxub8({{ 4729831SN/A uint64_t temp = 0; 4739831SN/A int hi = 63; 4749831SN/A int lo = 56; 4759243SN/A for (int i = 7; i >= 0; --i) { 4769243SN/A uint8_t ra_ub = Ra.uq<hi:lo>; 4779831SN/A uint8_t rb_ub = Rb.uq<hi:lo>; 4789831SN/A temp = ((temp << 8) 4799831SN/A | ((ra_ub > rb_ub) ? Ra.uq<hi:lo> 4809831SN/A : Rb.uq<hi:lo>)); 4819831SN/A hi -= 8; 4829243SN/A lo -= 8; 4839831SN/A } 4849831SN/A Rc = temp; 4859831SN/A }}); 4869243SN/A 48710206Sandreas.hansson@arm.com 0x3d: maxuw4({{ 48810206Sandreas.hansson@arm.com uint64_t temp = 0; 48910206Sandreas.hansson@arm.com int hi = 63; 4909567SN/A int lo = 48; 4919567SN/A for (int i = 3; i >= 0; --i) { 4929243SN/A uint16_t ra_uw = Ra.uq<hi:lo>; 4939243SN/A uint16_t rb_uw = Rb.uq<hi:lo>; 4949243SN/A temp = ((temp << 16) 4959243SN/A | ((ra_uw > rb_uw) ? Ra.uq<hi:lo> 49610146Sandreas.hansson@arm.com : Rb.uq<hi:lo>)); 4979243SN/A hi -= 16; 4989243SN/A lo -= 16; 4999243SN/A } 5009243SN/A Rc = temp; 5019243SN/A }}); 5029831SN/A 5039831SN/A 0x3e: maxsb8({{ 5049831SN/A uint64_t temp = 0; 5059831SN/A int hi = 63; 5069831SN/A int lo = 56; 5079831SN/A for (int i = 7; i >= 0; --i) { 5089831SN/A int8_t ra_sb = Ra.uq<hi:lo>; 5099831SN/A int8_t rb_sb = Rb.uq<hi:lo>; 5109243SN/A temp = ((temp << 8) 5119832SN/A | ((ra_sb > rb_sb) ? Ra.uq<hi:lo> 51210889Sandreas.hansson@arm.com : Rb.uq<hi:lo>)); 51310889Sandreas.hansson@arm.com hi -= 8; 51410889Sandreas.hansson@arm.com lo -= 8; 5159243SN/A } 5169832SN/A Rc = temp; 5179832SN/A }}); 5189832SN/A 5199966SN/A 0x3f: maxsw4({{ 5209243SN/A uint64_t temp = 0; 5219832SN/A int hi = 63; 5229832SN/A int lo = 48; 5239243SN/A for (int i = 3; i >= 0; --i) { 5249832SN/A int16_t ra_sw = Ra.uq<hi:lo>; 5259831SN/A int16_t rb_sw = Rb.uq<hi:lo>; 5269832SN/A temp = ((temp << 16) 52710889Sandreas.hansson@arm.com | ((ra_sw > rb_sw) ? Ra.uq<hi:lo> 52810889Sandreas.hansson@arm.com : Rb.uq<hi:lo>)); 5299831SN/A hi -= 16; 5309832SN/A lo -= 16; 5319832SN/A } 53211678Swendy.elsasser@arm.com Rc = temp; 53311678Swendy.elsasser@arm.com }}); 53411678Swendy.elsasser@arm.com 5359977SN/A format BasicOperateWithNopCheck { 53610889Sandreas.hansson@arm.com 0x70: decode RB { 53710889Sandreas.hansson@arm.com 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp); 5389977SN/A } 5399977SN/A 0x78: decode RB { 5409977SN/A 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }}, 5419832SN/A FloatCvtOp); 5429832SN/A } 5439831SN/A } 5449831SN/A } 5459831SN/A } 5469243SN/A 5479243SN/A // Conditional branches. 5489243SN/A format CondBranch { 5499243SN/A 0x39: beq({{ cond = (Ra == 0); }}); 5509831SN/A 0x3d: bne({{ cond = (Ra != 0); }}); 5519831SN/A 0x3e: bge({{ cond = (Ra.sq >= 0); }}); 5529726SN/A 0x3f: bgt({{ cond = (Ra.sq > 0); }}); 5539243SN/A 0x3b: ble({{ cond = (Ra.sq <= 0); }}); 55410206Sandreas.hansson@arm.com 0x3a: blt({{ cond = (Ra.sq < 0); }}); 55510206Sandreas.hansson@arm.com 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 55610206Sandreas.hansson@arm.com 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 55710206Sandreas.hansson@arm.com 55810206Sandreas.hansson@arm.com 0x31: fbeq({{ cond = (Fa == 0); }}); 5599243SN/A 0x35: fbne({{ cond = (Fa != 0); }}); 5609243SN/A 0x36: fbge({{ cond = (Fa >= 0); }}); 5619243SN/A 0x37: fbgt({{ cond = (Fa > 0); }}); 5629243SN/A 0x33: fble({{ cond = (Fa <= 0); }}); 56310146Sandreas.hansson@arm.com 0x32: fblt({{ cond = (Fa < 0); }}); 5649243SN/A } 5659833SN/A 5669243SN/A // unconditional branches 5679243SN/A format UncondBranch { 5689243SN/A 0x30: br(); 5699833SN/A 0x34: bsr(IsCall); 5709243SN/A } 5719243SN/A 5729243SN/A // indirect branches 5739833SN/A 0x1a: decode JMPFUNC { 5749243SN/A format Jump { 5759243SN/A 0: jmp(); 5769243SN/A 1: jsr(IsCall); 5779243SN/A 2: ret(IsReturn); 5789243SN/A 3: jsr_coroutine(IsCall, IsReturn); 57910146Sandreas.hansson@arm.com } 5809243SN/A } 5819243SN/A 5829567SN/A // Square root and integer-to-FP moves 5839831SN/A 0x14: decode FP_SHORTFUNC { 5849243SN/A // Integer to FP register moves must have RB == 31 58511334Sandreas.hansson@arm.com 0x4: decode RB { 58611334Sandreas.hansson@arm.com 31: decode FP_FULLFUNC { 58711334Sandreas.hansson@arm.com format BasicOperateWithNopCheck { 58811334Sandreas.hansson@arm.com 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 58911334Sandreas.hansson@arm.com 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 5909243SN/A 0x014: FailUnimpl::itoff(); // VAX-format conversion 5919243SN/A } 5929243SN/A } 5939243SN/A } 5949243SN/A 5959243SN/A // Square root instructions must have FA == 31 5969243SN/A 0xb: decode FA { 5979831SN/A 31: decode FP_TYPEFUNC { 5989831SN/A format FloatingPointOperate { 5999831SN/A#if SS_COMPATIBLE_FP 6009831SN/A 0x0b: sqrts({{ 6019831SN/A if (Fb < 0.0) 6029243SN/A fault = new ArithmeticFault; 6039831SN/A Fc = sqrt(Fb); 6049831SN/A }}, FloatSqrtOp); 6059243SN/A#else 6069243SN/A 0x0b: sqrts({{ 6079243SN/A if (Fb.sf < 0.0) 6089567SN/A fault = new ArithmeticFault; 6099831SN/A Fc.sf = sqrt(Fb.sf); 6109567SN/A }}, FloatSqrtOp); 6119243SN/A#endif 6129243SN/A 0x2b: sqrtt({{ 6139243SN/A if (Fb < 0.0) 6149243SN/A fault = new ArithmeticFault; 6159243SN/A Fc = sqrt(Fb); 6169831SN/A }}, FloatSqrtOp); 6179243SN/A } 6189977SN/A } 6199243SN/A } 62011334Sandreas.hansson@arm.com 62111334Sandreas.hansson@arm.com // VAX-format sqrtf and sqrtg are not implemented 6229567SN/A 0xa: FailUnimpl::sqrtfg(); 6239831SN/A } 6249567SN/A 6259243SN/A // IEEE floating point 6269243SN/A 0x16: decode FP_SHORTFUNC_TOP2 { 6279243SN/A // The top two bits of the short function code break this 6289243SN/A // space into four groups: binary ops, compares, reserved, and 6299243SN/A // conversions. See Table 4-12 of AHB. There are different 6309831SN/A // special cases in these different groups, so we decode on 6319243SN/A // these top two bits first just to select a decode strategy. 6329977SN/A // Most of these instructions may have various trapping and 6339243SN/A // rounding mode flags set; these are decoded in the 6349243SN/A // FloatingPointDecode template used by the 6359243SN/A // FloatingPointOperate format. 6369243SN/A 6379243SN/A // add/sub/mul/div: just decode on the short function code 6389243SN/A // and source type. All valid trapping and rounding modes apply. 6399243SN/A 0: decode FP_TRAPMODE { 64010146Sandreas.hansson@arm.com // check for valid trapping modes here 6419243SN/A 0,1,5,7: decode FP_TYPEFUNC { 6429243SN/A format FloatingPointOperate { 6439243SN/A#if SS_COMPATIBLE_FP 6449243SN/A 0x00: adds({{ Fc = Fa + Fb; }}); 6459831SN/A 0x01: subs({{ Fc = Fa - Fb; }}); 6469243SN/A 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 64711678Swendy.elsasser@arm.com 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 64811678Swendy.elsasser@arm.com#else 64911678Swendy.elsasser@arm.com 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }}); 65011678Swendy.elsasser@arm.com 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }}); 65111678Swendy.elsasser@arm.com 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); 65211678Swendy.elsasser@arm.com 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp); 65311678Swendy.elsasser@arm.com#endif 65411678Swendy.elsasser@arm.com 65511678Swendy.elsasser@arm.com 0x20: addt({{ Fc = Fa + Fb; }}); 65611678Swendy.elsasser@arm.com 0x21: subt({{ Fc = Fa - Fb; }}); 65711678Swendy.elsasser@arm.com 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 65811678Swendy.elsasser@arm.com 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 65911678Swendy.elsasser@arm.com } 66011846Swendy.elsasser@arm.com } 66111846Swendy.elsasser@arm.com } 66211846Swendy.elsasser@arm.com 66311846Swendy.elsasser@arm.com // Floating-point compare instructions must have the default 66411678Swendy.elsasser@arm.com // rounding mode, and may use the default trapping mode or 66511678Swendy.elsasser@arm.com // /SU. Both trapping modes are treated the same by M5; the 66611678Swendy.elsasser@arm.com // only difference on the real hardware (as far a I can tell) 66712705Swendy.elsasser@arm.com // is that without /SU you'd get an imprecise trap if you 66812705Swendy.elsasser@arm.com // tried to compare a NaN with something else (instead of an 66911678Swendy.elsasser@arm.com // "unordered" result). 67011678Swendy.elsasser@arm.com 1: decode FP_FULLFUNC { 67111678Swendy.elsasser@arm.com format BasicOperateWithNopCheck { 67211678Swendy.elsasser@arm.com 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 67311678Swendy.elsasser@arm.com FloatCmpOp); 67411678Swendy.elsasser@arm.com 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 67511678Swendy.elsasser@arm.com FloatCmpOp); 67611678Swendy.elsasser@arm.com 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 67711678Swendy.elsasser@arm.com FloatCmpOp); 67811678Swendy.elsasser@arm.com 0x0a4, 0x5a4: cmptun({{ // unordered 67911678Swendy.elsasser@arm.com Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 68011678Swendy.elsasser@arm.com }}, FloatCmpOp); 68111678Swendy.elsasser@arm.com } 68211678Swendy.elsasser@arm.com } 68311678Swendy.elsasser@arm.com 68411678Swendy.elsasser@arm.com // The FP-to-integer and integer-to-FP conversion insts 68511678Swendy.elsasser@arm.com // require that FA be 31. 68611678Swendy.elsasser@arm.com 3: decode FA { 68711678Swendy.elsasser@arm.com 31: decode FP_TYPEFUNC { 6889831SN/A format FloatingPointOperate { 6899831SN/A 0x2f: decode FP_ROUNDMODE { 6909831SN/A format FPFixedRounding { 6919831SN/A // "chopped" i.e. round toward zero 69210143SN/A 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }}, 6939831SN/A Chopped); 6949831SN/A // round to minus infinity 6959831SN/A 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }}, 6969831SN/A MinusInfinity); 6979831SN/A } 6989831SN/A default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }}); 6999831SN/A } 7009831SN/A 7019831SN/A // The cvtts opcode is overloaded to be cvtst if the trap 7029831SN/A // mode is 2 or 6 (which are not valid otherwise) 7039831SN/A 0x2c: decode FP_FULLFUNC { 7049831SN/A format BasicOperateWithNopCheck { 7059243SN/A // trap on denorm version "cvtst/s" is 7069831SN/A // simulated same as cvtst 7079831SN/A 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }}); 7089243SN/A } 7099831SN/A default: cvtts({{ Fc.sf = Fb; }}); 7109831SN/A } 7119831SN/A 7129831SN/A // The trapping mode for integer-to-FP conversions 7139831SN/A // must be /SUI or nothing; /U and /SU are not 7149831SN/A // allowed. The full set of rounding modes are 71510913Sandreas.sandberg@arm.com // supported though. 71611676Swendy.elsasser@arm.com 0x3c: decode FP_TRAPMODE { 71710913Sandreas.sandberg@arm.com 0,7: cvtqs({{ Fc.sf = Fb.sq; }}); 71810509SAli.Saidi@ARM.com } 71910913Sandreas.sandberg@arm.com 0x3e: decode FP_TRAPMODE { 7209831SN/A 0,7: cvtqt({{ Fc = Fb.sq; }}); 7219831SN/A } 7229567SN/A } 7239831SN/A } 7249831SN/A } 7259831SN/A } 7269831SN/A 72710713Sandreas.hansson@arm.com // misc FP operate 7289831SN/A 0x17: decode FP_FULLFUNC { 7299243SN/A format BasicOperateWithNopCheck { 7309243SN/A 0x010: cvtlq({{ 73110618SOmar.Naji@arm.com Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>; 73210890Swendy.elsasser@arm.com }}); 7339243SN/A 0x030: cvtql({{ 73410206Sandreas.hansson@arm.com Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 73510206Sandreas.hansson@arm.com }}); 73610206Sandreas.hansson@arm.com 73710206Sandreas.hansson@arm.com // We treat the precise & imprecise trapping versions of 73810206Sandreas.hansson@arm.com // cvtql identically. 7399243SN/A 0x130, 0x530: cvtqlv({{ 74010618SOmar.Naji@arm.com // To avoid overflow, all the upper 32 bits must match 74110618SOmar.Naji@arm.com // the sign bit of the lower 32. We code this as 74210206Sandreas.hansson@arm.com // checking the upper 33 bits for all 0s or all 1s. 74310618SOmar.Naji@arm.com uint64_t sign_bits = Fb.uq<63:31>; 74410618SOmar.Naji@arm.com if (sign_bits != 0 && sign_bits != mask(33)) 74512266Sradhika.jagtap@arm.com fault = new IntegerOverflowFault; 74610618SOmar.Naji@arm.com Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 74710618SOmar.Naji@arm.com }}); 74810618SOmar.Naji@arm.com 74910618SOmar.Naji@arm.com 0x020: cpys({{ // copy sign 75010618SOmar.Naji@arm.com Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>; 75110618SOmar.Naji@arm.com }}); 7529243SN/A 0x021: cpysn({{ // copy sign negated 7539243SN/A Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>; 7549243SN/A }}); 75510618SOmar.Naji@arm.com 0x022: cpyse({{ // copy sign and exponent 75611321Ssteve.reinhardt@amd.com Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>; 75710618SOmar.Naji@arm.com }}); 75812266Sradhika.jagtap@arm.com 75910618SOmar.Naji@arm.com 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 76010618SOmar.Naji@arm.com 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 76110618SOmar.Naji@arm.com 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 76210618SOmar.Naji@arm.com 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 76310618SOmar.Naji@arm.com 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 76410618SOmar.Naji@arm.com 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 7659243SN/A 76610890Swendy.elsasser@arm.com 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess); 7679243SN/A 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess); 7689243SN/A } 76910618SOmar.Naji@arm.com } 7709243SN/A 7719243SN/A // miscellaneous mem-format ops 77210618SOmar.Naji@arm.com 0x18: decode MEMFUNC { 77310890Swendy.elsasser@arm.com format WarnUnimpl { 7749974SN/A 0x8000: fetch(); 77510890Swendy.elsasser@arm.com 0xa000: fetch_m(); 7769974SN/A 0xe800: ecb(); 77710890Swendy.elsasser@arm.com } 7789974SN/A 77910890Swendy.elsasser@arm.com format MiscPrefetch { 78010890Swendy.elsasser@arm.com 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 78110890Swendy.elsasser@arm.com {{ ; }}, 78210890Swendy.elsasser@arm.com mem_flags = PREFETCH); 78310890Swendy.elsasser@arm.com } 78410890Swendy.elsasser@arm.com 78510890Swendy.elsasser@arm.com format BasicOperate { 78610890Swendy.elsasser@arm.com 0xc000: rpcc({{ 78710890Swendy.elsasser@arm.com#if FULL_SYSTEM 78810890Swendy.elsasser@arm.com /* Rb is a fake dependency so here is a fun way to get 78910890Swendy.elsasser@arm.com * the parser to understand that. 79010890Swendy.elsasser@arm.com */ 79110890Swendy.elsasser@arm.com Ra = xc->readMiscReg(IPR_CC) + (Rb & 0); 7929974SN/A 79310890Swendy.elsasser@arm.com#else 79410618SOmar.Naji@arm.com Ra = curTick; 7959974SN/A#endif 79610890Swendy.elsasser@arm.com }}, IsUnverifiable); 79710890Swendy.elsasser@arm.com 79810890Swendy.elsasser@arm.com // All of the barrier instructions below do nothing in 79910890Swendy.elsasser@arm.com // their execute() methods (hence the empty code blocks). 8009974SN/A // All of their functionality is hard-coded in the 8019974SN/A // pipeline based on the flags IsSerializing, 8029974SN/A // IsMemBarrier, and IsWriteBarrier. In the current 80310890Swendy.elsasser@arm.com // detailed CPU model, the execute() function only gets 80412266Sradhika.jagtap@arm.com // called at fetch, so there's no way to generate pipeline 80512266Sradhika.jagtap@arm.com // behavior at any other stage. Once we go to an 80612266Sradhika.jagtap@arm.com // exec-in-exec CPU model we should be able to get rid of 80710890Swendy.elsasser@arm.com // these flags and implement this behavior via the 80810618SOmar.Naji@arm.com // execute() methods. 80910890Swendy.elsasser@arm.com 81010890Swendy.elsasser@arm.com // trapb is just a barrier on integer traps, where excb is 81110890Swendy.elsasser@arm.com // a barrier on integer and FP traps. "EXCB is thus a 81210890Swendy.elsasser@arm.com // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 81310890Swendy.elsasser@arm.com // them the same though. 81410890Swendy.elsasser@arm.com 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 81510890Swendy.elsasser@arm.com 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 81610890Swendy.elsasser@arm.com 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 81710890Swendy.elsasser@arm.com 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 81810618SOmar.Naji@arm.com } 81910890Swendy.elsasser@arm.com 82010618SOmar.Naji@arm.com#if FULL_SYSTEM 82110890Swendy.elsasser@arm.com format BasicOperate { 82210890Swendy.elsasser@arm.com 0xe000: rc({{ 82310890Swendy.elsasser@arm.com Ra = IntrFlag; 82410890Swendy.elsasser@arm.com IntrFlag = 0; 82510890Swendy.elsasser@arm.com }}, IsNonSpeculative, IsUnverifiable); 82610618SOmar.Naji@arm.com 0xf000: rs({{ 82710890Swendy.elsasser@arm.com Ra = IntrFlag; 82810890Swendy.elsasser@arm.com IntrFlag = 1; 82910618SOmar.Naji@arm.com }}, IsNonSpeculative, IsUnverifiable); 83010890Swendy.elsasser@arm.com } 83110890Swendy.elsasser@arm.com#else 83210890Swendy.elsasser@arm.com format FailUnimpl { 83310890Swendy.elsasser@arm.com 0xe000: rc(); 83410890Swendy.elsasser@arm.com 0xf000: rs(); 83510890Swendy.elsasser@arm.com } 83610890Swendy.elsasser@arm.com#endif 83710890Swendy.elsasser@arm.com } 83810890Swendy.elsasser@arm.com 83910890Swendy.elsasser@arm.com#if FULL_SYSTEM 84010211Sandreas.hansson@arm.com 0x00: CallPal::call_pal({{ 84110890Swendy.elsasser@arm.com if (!palValid || 84210890Swendy.elsasser@arm.com (palPriv 84310890Swendy.elsasser@arm.com && xc->readMiscReg(IPR_ICM) != mode_kernel)) { 84410890Swendy.elsasser@arm.com // invalid pal function code, or attempt to do privileged 84510618SOmar.Naji@arm.com // PAL call in non-kernel mode 84610890Swendy.elsasser@arm.com fault = new UnimplementedOpcodeFault; 84710890Swendy.elsasser@arm.com } else { 84810890Swendy.elsasser@arm.com // check to see if simulator wants to do something special 84910890Swendy.elsasser@arm.com // on this PAL call (including maybe suppress it) 85010890Swendy.elsasser@arm.com bool dopal = xc->simPalCheck(palFunc); 85110890Swendy.elsasser@arm.com 85210890Swendy.elsasser@arm.com if (dopal) { 85310890Swendy.elsasser@arm.com xc->setMiscReg(IPR_EXC_ADDR, NPC); 85410618SOmar.Naji@arm.com NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset; 8559974SN/A } 8569974SN/A } 8579974SN/A }}, IsNonSpeculative); 8589974SN/A#else 85910618SOmar.Naji@arm.com 0x00: decode PALFUNC { 86010618SOmar.Naji@arm.com format EmulatedCallPal { 86110618SOmar.Naji@arm.com 0x00: halt ({{ 86210618SOmar.Naji@arm.com exitSimLoop("halt instruction encountered"); 86310890Swendy.elsasser@arm.com }}, IsNonSpeculative); 86410618SOmar.Naji@arm.com 0x83: callsys({{ 86510890Swendy.elsasser@arm.com xc->syscall(R0); 86610890Swendy.elsasser@arm.com }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 8679974SN/A // Read uniq reg into ABI return value register (r0) 8689974SN/A 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); 8699974SN/A // Write uniq reg with value from ABI arg register (r16) 87010146Sandreas.hansson@arm.com 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess); 8719243SN/A } 8729243SN/A } 8739243SN/A#endif 8749243SN/A 8759243SN/A#if FULL_SYSTEM 8769243SN/A 0x1b: decode PALMODE { 8779243SN/A 0: OpcdecFault::hw_st_quad(); 8789243SN/A 1: decode HW_LDST_QUAD { 8799243SN/A format HwLoad { 8809243SN/A 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, 8819243SN/A L, IsSerializing, IsSerializeBefore); 8829243SN/A 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, 88310721SMarco.Balboni@ARM.com Q, IsSerializing, IsSerializeBefore); 88410721SMarco.Balboni@ARM.com } 88510721SMarco.Balboni@ARM.com } 88610721SMarco.Balboni@ARM.com } 88710721SMarco.Balboni@ARM.com 88810721SMarco.Balboni@ARM.com 0x1f: decode PALMODE { 88910721SMarco.Balboni@ARM.com 0: OpcdecFault::hw_st_cond(); 89010694SMarco.Balboni@ARM.com format HwStore { 8919549SN/A 1: decode HW_LDST_COND { 8929726SN/A 0: decode HW_LDST_QUAD { 8939726SN/A 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 89411194Sali.jafri@arm.com {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore); 8959243SN/A 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 8969587SN/A {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore); 8979587SN/A } 89811190Sandreas.hansson@arm.com 8999243SN/A 1: FailUnimpl::hw_st_cond(); 9009243SN/A } 9019243SN/A } 9029243SN/A } 9039243SN/A 9049243SN/A 0x19: decode PALMODE { 9059243SN/A 0: OpcdecFault::hw_mfpr(); 9069243SN/A format HwMoveIPR { 90710618SOmar.Naji@arm.com 1: hw_mfpr({{ 90810618SOmar.Naji@arm.com int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 9099488SN/A IprToMiscRegIndex[ipr_index] : -1; 91010618SOmar.Naji@arm.com if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || 9119488SN/A miscRegIndex >= NumInternalProcRegs) 9129488SN/A fault = new UnimplementedOpcodeFault; 9139488SN/A else 91410207Sandreas.hansson@arm.com Ra = xc->readMiscReg(miscRegIndex); 91510618SOmar.Naji@arm.com }}, IsIprAccess); 91610618SOmar.Naji@arm.com } 91710207Sandreas.hansson@arm.com } 91810207Sandreas.hansson@arm.com 91910207Sandreas.hansson@arm.com 0x1d: decode PALMODE { 92010207Sandreas.hansson@arm.com 0: OpcdecFault::hw_mtpr(); 92110618SOmar.Naji@arm.com format HwMoveIPR { 92210618SOmar.Naji@arm.com 1: hw_mtpr({{ 92310207Sandreas.hansson@arm.com int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 92410618SOmar.Naji@arm.com IprToMiscRegIndex[ipr_index] : -1; 92510618SOmar.Naji@arm.com if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) || 92610207Sandreas.hansson@arm.com miscRegIndex >= NumInternalProcRegs) 92710247Sandreas.hansson@arm.com fault = new UnimplementedOpcodeFault; 92810618SOmar.Naji@arm.com else 92910618SOmar.Naji@arm.com xc->setMiscReg(miscRegIndex, Ra); 93010247Sandreas.hansson@arm.com if (traceData) { traceData->setData(Ra); } 93111675Swendy.elsasser@arm.com }}, IsIprAccess); 93211675Swendy.elsasser@arm.com } 93310432SOmar.Naji@arm.com } 93410432SOmar.Naji@arm.com 93510618SOmar.Naji@arm.com 0x1e: decode PALMODE { 9369975SN/A 0: OpcdecFault::hw_rei(); 93710211Sandreas.hansson@arm.com format BasicOperate { 93810618SOmar.Naji@arm.com 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); 93910211Sandreas.hansson@arm.com } 94010211Sandreas.hansson@arm.com } 94110618SOmar.Naji@arm.com 94210211Sandreas.hansson@arm.com#endif 9439971SN/A 94411321Ssteve.reinhardt@amd.com format BasicOperate { 94510210Sandreas.hansson@arm.com // M5 special opcodes use the reserved 0x01 opcode space 94610210Sandreas.hansson@arm.com 0x01: decode M5FUNC { 94710618SOmar.Naji@arm.com#if FULL_SYSTEM 94810394Swendy.elsasser@arm.com 0x00: arm({{ 94910394Swendy.elsasser@arm.com PseudoInst::arm(xc->tcBase()); 95010394Swendy.elsasser@arm.com }}, IsNonSpeculative); 95110618SOmar.Naji@arm.com 0x01: quiesce({{ 95210618SOmar.Naji@arm.com PseudoInst::quiesce(xc->tcBase()); 95310394Swendy.elsasser@arm.com }}, IsNonSpeculative, IsQuiesce); 95410394Swendy.elsasser@arm.com 0x02: quiesceNs({{ 95510394Swendy.elsasser@arm.com PseudoInst::quiesceNs(xc->tcBase(), R16); 95610394Swendy.elsasser@arm.com }}, IsNonSpeculative, IsQuiesce); 95710618SOmar.Naji@arm.com 0x03: quiesceCycles({{ 95810618SOmar.Naji@arm.com PseudoInst::quiesceCycles(xc->tcBase(), R16); 95910394Swendy.elsasser@arm.com }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 9609971SN/A 0x04: quiesceTime({{ 96110208Sandreas.hansson@arm.com R0 = PseudoInst::quiesceTime(xc->tcBase()); 9629971SN/A }}, IsNonSpeculative, IsUnverifiable); 96310492SOmar.Naji@arm.com#endif 96410618SOmar.Naji@arm.com 0x07: rpns({{ 96510492SOmar.Naji@arm.com R0 = PseudoInst::rpns(xc->tcBase()); 96610618SOmar.Naji@arm.com }}, IsNonSpeculative, IsUnverifiable); 96710618SOmar.Naji@arm.com 0x09: wakeCPU({{ 96810492SOmar.Naji@arm.com PseudoInst::wakeCPU(xc->tcBase(), R16); 96910492SOmar.Naji@arm.com }}, IsNonSpeculative, IsUnverifiable); 97010618SOmar.Naji@arm.com 0x10: deprecated_ivlb({{ 97110618SOmar.Naji@arm.com warn_once("Obsolete M5 ivlb instruction encountered.\n"); 97210492SOmar.Naji@arm.com }}); 9739824SN/A 0x11: deprecated_ivle({{ 97410492SOmar.Naji@arm.com warn_once("Obsolete M5 ivlb instruction encountered.\n"); 97510492SOmar.Naji@arm.com }}); 97610618SOmar.Naji@arm.com 0x20: deprecated_exit ({{ 9779488SN/A warn_once("deprecated M5 exit instruction encountered.\n"); 97810492SOmar.Naji@arm.com PseudoInst::m5exit(xc->tcBase(), 0); 97910618SOmar.Naji@arm.com }}, No_OpClass, IsNonSpeculative); 9809488SN/A 0x21: m5exit({{ 98110492SOmar.Naji@arm.com PseudoInst::m5exit(xc->tcBase(), R16); 98210492SOmar.Naji@arm.com }}, No_OpClass, IsNonSpeculative); 98310492SOmar.Naji@arm.com#if FULL_SYSTEM 98410618SOmar.Naji@arm.com 0x31: loadsymbol({{ 98510618SOmar.Naji@arm.com PseudoInst::loadsymbol(xc->tcBase()); 98610492SOmar.Naji@arm.com }}, No_OpClass, IsNonSpeculative); 98710492SOmar.Naji@arm.com 0x30: initparam({{ 98810618SOmar.Naji@arm.com Ra = xc->tcBase()->getCpuPtr()->system->init_param; 98911321Ssteve.reinhardt@amd.com }}); 9909488SN/A#endif 99110618SOmar.Naji@arm.com 0x40: resetstats({{ 99210618SOmar.Naji@arm.com PseudoInst::resetstats(xc->tcBase(), R16, R17); 99310618SOmar.Naji@arm.com }}, IsNonSpeculative); 99410492SOmar.Naji@arm.com 0x41: dumpstats({{ 9959488SN/A PseudoInst::dumpstats(xc->tcBase(), R16, R17); 99610208Sandreas.hansson@arm.com }}, IsNonSpeculative); 99710208Sandreas.hansson@arm.com 0x42: dumpresetstats({{ 99810208Sandreas.hansson@arm.com PseudoInst::dumpresetstats(xc->tcBase(), R16, R17); 99910618SOmar.Naji@arm.com }}, IsNonSpeculative); 100010618SOmar.Naji@arm.com 0x43: m5checkpoint({{ 100110618SOmar.Naji@arm.com PseudoInst::m5checkpoint(xc->tcBase(), R16, R17); 100210208Sandreas.hansson@arm.com }}, IsNonSpeculative); 100310618SOmar.Naji@arm.com#if FULL_SYSTEM 100410208Sandreas.hansson@arm.com 0x50: m5readfile({{ 100510208Sandreas.hansson@arm.com R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18); 100610208Sandreas.hansson@arm.com }}, IsNonSpeculative); 100710618SOmar.Naji@arm.com#endif 100810207Sandreas.hansson@arm.com 0x51: m5break({{ 100910207Sandreas.hansson@arm.com PseudoInst::debugbreak(xc->tcBase()); 101010207Sandreas.hansson@arm.com }}, IsNonSpeculative); 101110207Sandreas.hansson@arm.com 0x52: m5switchcpu({{ 101210207Sandreas.hansson@arm.com PseudoInst::switchcpu(xc->tcBase()); 101310207Sandreas.hansson@arm.com }}, IsNonSpeculative); 101410207Sandreas.hansson@arm.com#if FULL_SYSTEM 101510207Sandreas.hansson@arm.com 0x53: m5addsymbol({{ 101610207Sandreas.hansson@arm.com PseudoInst::addsymbol(xc->tcBase(), R16, R17); 101710207Sandreas.hansson@arm.com }}, IsNonSpeculative); 101810214Sandreas.hansson@arm.com#endif 101910214Sandreas.hansson@arm.com 0x54: m5panic({{ 102010214Sandreas.hansson@arm.com panic("M5 panic instruction called at pc = %#x.", PC); 102110211Sandreas.hansson@arm.com }}, IsNonSpeculative); 102210211Sandreas.hansson@arm.com#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase()) 102310211Sandreas.hansson@arm.com 0x55: decode RA { 102410207Sandreas.hansson@arm.com 0x00: m5a_old({{ 102510618SOmar.Naji@arm.com panic("Deprecated M5 annotate instruction executed " 102610618SOmar.Naji@arm.com "at pc = %#x\n", PC); 102710207Sandreas.hansson@arm.com }}, IsNonSpeculative); 102810247Sandreas.hansson@arm.com 0x01: m5a_bsm({{ 102910618SOmar.Naji@arm.com CPANN(swSmBegin); 103010618SOmar.Naji@arm.com }}, IsNonSpeculative); 103110247Sandreas.hansson@arm.com 0x02: m5a_esm({{ 103210432SOmar.Naji@arm.com CPANN(swSmEnd); 103310207Sandreas.hansson@arm.com }}, IsNonSpeculative); 103411675Swendy.elsasser@arm.com 0x03: m5a_begin({{ 103511675Swendy.elsasser@arm.com CPANN(swExplictBegin); 103610432SOmar.Naji@arm.com }}, IsNonSpeculative); 103710618SOmar.Naji@arm.com 0x04: m5a_end({{ 103810432SOmar.Naji@arm.com CPANN(swEnd); 103910208Sandreas.hansson@arm.com }}, IsNonSpeculative); 104010208Sandreas.hansson@arm.com 0x06: m5a_q({{ 104110208Sandreas.hansson@arm.com CPANN(swQ); 104210208Sandreas.hansson@arm.com }}, IsNonSpeculative); 104310208Sandreas.hansson@arm.com 0x07: m5a_dq({{ 104410208Sandreas.hansson@arm.com CPANN(swDq); 104511678Swendy.elsasser@arm.com }}, IsNonSpeculative); 104610618SOmar.Naji@arm.com 0x08: m5a_wf({{ 104711678Swendy.elsasser@arm.com CPANN(swWf); 104811678Swendy.elsasser@arm.com }}, IsNonSpeculative); 104911678Swendy.elsasser@arm.com 0x09: m5a_we({{ 105010618SOmar.Naji@arm.com CPANN(swWe); 105111678Swendy.elsasser@arm.com }}, IsNonSpeculative); 105210207Sandreas.hansson@arm.com 0x0C: m5a_sq({{ 105310207Sandreas.hansson@arm.com CPANN(swSq); 105410207Sandreas.hansson@arm.com }}, IsNonSpeculative); 105510146Sandreas.hansson@arm.com 0x0D: m5a_aq({{ 10569243SN/A CPANN(swAq); 10579243SN/A }}, IsNonSpeculative); 10589243SN/A 0x0E: m5a_pq({{ 10599243SN/A CPANN(swPq); 106010618SOmar.Naji@arm.com }}, IsNonSpeculative); 106110618SOmar.Naji@arm.com 0x0F: m5a_l({{ 106210618SOmar.Naji@arm.com CPANN(swLink); 106311678Swendy.elsasser@arm.com }}, IsNonSpeculative); 106411678Swendy.elsasser@arm.com 0x10: m5a_identify({{ 106511678Swendy.elsasser@arm.com CPANN(swIdentify); 106611678Swendy.elsasser@arm.com }}, IsNonSpeculative); 106711678Swendy.elsasser@arm.com 0x11: m5a_getid({{ 106811678Swendy.elsasser@arm.com R0 = CPANN(swGetId); 106911678Swendy.elsasser@arm.com }}, IsNonSpeculative); 107011678Swendy.elsasser@arm.com 0x13: m5a_scl({{ 107110211Sandreas.hansson@arm.com CPANN(swSyscallLink); 10729967SN/A }}, IsNonSpeculative); 10739243SN/A 0x14: m5a_rq({{ 107410211Sandreas.hansson@arm.com CPANN(swRq); 107510211Sandreas.hansson@arm.com }}, IsNonSpeculative); 107610211Sandreas.hansson@arm.com } // M5 Annotate Operations 107710211Sandreas.hansson@arm.com#undef CPANN 107810211Sandreas.hansson@arm.com 0x56: m5reserved2({{ 107910211Sandreas.hansson@arm.com warn("M5 reserved opcode ignored"); 108010211Sandreas.hansson@arm.com }}, IsNonSpeculative); 108110211Sandreas.hansson@arm.com 0x57: m5reserved3({{ 108210211Sandreas.hansson@arm.com warn("M5 reserved opcode ignored"); 108310209Sandreas.hansson@arm.com }}, IsNonSpeculative); 108410211Sandreas.hansson@arm.com 0x58: m5reserved4({{ 108510211Sandreas.hansson@arm.com warn("M5 reserved opcode ignored"); 108610209Sandreas.hansson@arm.com }}, IsNonSpeculative); 108710209Sandreas.hansson@arm.com 0x59: m5reserved5({{ 108810618SOmar.Naji@arm.com warn("M5 reserved opcode ignored"); 10899488SN/A }}, IsNonSpeculative); 10909973SN/A } 109110211Sandreas.hansson@arm.com } 109210211Sandreas.hansson@arm.com} 109310211Sandreas.hansson@arm.com