decoder.isa revision 2312
12889Sbinkertn@umich.edu// -*- mode:c++ -*-
22889Sbinkertn@umich.edu
32889Sbinkertn@umich.edu// Copyright (c) 2003-2006 The Regents of The University of Michigan
42889Sbinkertn@umich.edu// All rights reserved.
52889Sbinkertn@umich.edu//
62889Sbinkertn@umich.edu// Redistribution and use in source and binary forms, with or without
72889Sbinkertn@umich.edu// modification, are permitted provided that the following conditions are
82889Sbinkertn@umich.edu// met: redistributions of source code must retain the above copyright
92889Sbinkertn@umich.edu// notice, this list of conditions and the following disclaimer;
102889Sbinkertn@umich.edu// redistributions in binary form must reproduce the above copyright
112889Sbinkertn@umich.edu// notice, this list of conditions and the following disclaimer in the
122889Sbinkertn@umich.edu// documentation and/or other materials provided with the distribution;
132889Sbinkertn@umich.edu// neither the name of the copyright holders nor the names of its
142889Sbinkertn@umich.edu// contributors may be used to endorse or promote products derived from
152889Sbinkertn@umich.edu// this software without specific prior written permission.
162889Sbinkertn@umich.edu//
172889Sbinkertn@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182889Sbinkertn@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192889Sbinkertn@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202889Sbinkertn@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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232889Sbinkertn@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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252889Sbinkertn@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262889Sbinkertn@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272889Sbinkertn@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282889Sbinkertn@umich.edu
294850Snate@binkert.orgdecode OPCODE default Unknown::unknown() {
304850Snate@binkert.org
314850Snate@binkert.org    format LoadAddress {
324850Snate@binkert.org        0x08: lda({{ Ra = Rb + disp; }});
334850Snate@binkert.org        0x09: ldah({{ Ra = Rb + (disp << 16); }});
344850Snate@binkert.org    }
352889Sbinkertn@umich.edu
362889Sbinkertn@umich.edu    format LoadOrNop {
378327Sgblack@eecs.umich.edu        0x0a: ldbu({{ Ra.uq = Mem.ub; }});
385470Snate@binkert.org        0x0c: ldwu({{ Ra.uq = Mem.uw; }});
398333Snate@binkert.org        0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
408333Snate@binkert.org        0x23: ldt({{ Fa = Mem.df; }});
412889Sbinkertn@umich.edu        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
428234Snate@binkert.org        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
438234Snate@binkert.org        0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
448234Snate@binkert.org                                      {{ fault = xc->copySrcTranslate(EA); }},
452889Sbinkertn@umich.edu                                      inst_flags = [IsMemRef, IsLoad, IsCopy]);
468234Snate@binkert.org    }
478234Snate@binkert.org
488234Snate@binkert.org    format LoadOrPrefetch {
498234Snate@binkert.org        0x28: ldl({{ Ra.sl = Mem.sl; }});
502889Sbinkertn@umich.edu        0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
518234Snate@binkert.org        // IsFloating flag on lds gets the prefetch to disassemble
528234Snate@binkert.org        // using f31 instead of r31... funcitonally it's unnecessary
538234Snate@binkert.org        0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
548234Snate@binkert.org                  pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
558234Snate@binkert.org    }
568234Snate@binkert.org
578234Snate@binkert.org    format Store {
582889Sbinkertn@umich.edu        0x0e: stb({{ Mem.ub = Ra<7:0>; }});
598234Snate@binkert.org        0x0d: stw({{ Mem.uw = Ra<15:0>; }});
608234Snate@binkert.org        0x2c: stl({{ Mem.ul = Ra<31:0>; }});
618234Snate@binkert.org        0x2d: stq({{ Mem.uq = Ra.uq; }});
628234Snate@binkert.org        0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
638234Snate@binkert.org        0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
648234Snate@binkert.org        0x27: stt({{ Mem.df = Fa; }});
658234Snate@binkert.org        0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
668234Snate@binkert.org                                       {{ fault = xc->copy(EA); }},
678234Snate@binkert.org                                       inst_flags = [IsMemRef, IsStore, IsCopy]);
688234Snate@binkert.org    }
698234Snate@binkert.org
708234Snate@binkert.org    format StoreCond {
718234Snate@binkert.org        0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
728234Snate@binkert.org                    {{
738234Snate@binkert.org                        uint64_t tmp = write_result;
748234Snate@binkert.org                        // see stq_c
758234Snate@binkert.org                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
768234Snate@binkert.org                    }}, mem_flags = LOCKED, inst_flags = [IsNonSpeculative,
778234Snate@binkert.org                                                          IsSerializing,
788234Snate@binkert.org                                                          IsSerializeAfter]);
798234Snate@binkert.org        0x2f: stq_c({{ Mem.uq = Ra; }},
802889Sbinkertn@umich.edu                    {{
818234Snate@binkert.org                        uint64_t tmp = write_result;
828234Snate@binkert.org                        // If the write operation returns 0 or 1, then
838234Snate@binkert.org                        // this was a conventional store conditional,
848234Snate@binkert.org                        // and the value indicates the success/failure
855773Snate@binkert.org                        // of the operation.  If another value is
868234Snate@binkert.org                        // returned, then this was a Turbolaser
878234Snate@binkert.org                        // mailbox access, and we don't update the
888234Snate@binkert.org                        // result register at all.
898234Snate@binkert.org                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
908664SAli.Saidi@ARM.com                    }}, mem_flags = LOCKED, inst_flags = [IsNonSpeculative,
918664SAli.Saidi@ARM.com                                                          IsSerializing,
928998Suri.wiener@arm.com                                                          IsSerializeAfter]);
938998Suri.wiener@arm.com    }
942889Sbinkertn@umich.edu
958234Snate@binkert.org    format IntegerOperate {
968234Snate@binkert.org
978234Snate@binkert.org        0x10: decode INTFUNC {	// integer arithmetic operations
988234Snate@binkert.org
998234Snate@binkert.org            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1008234Snate@binkert.org            0x40: addlv({{
1018234Snate@binkert.org                uint32_t tmp  = Ra.sl + Rb_or_imm.sl;
1028234Snate@binkert.org                // signed overflow occurs when operands have same sign
1038234Snate@binkert.org                // and sign of result does not match.
1048234Snate@binkert.org                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1052889Sbinkertn@umich.edu                    fault = new IntegerOverflowFault;
1068234Snate@binkert.org                Rc.sl = tmp;
1078234Snate@binkert.org            }});
1088234Snate@binkert.org            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1098234Snate@binkert.org            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1108234Snate@binkert.org
1118234Snate@binkert.org            0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1128234Snate@binkert.org            0x60: addqv({{
1138234Snate@binkert.org                uint64_t tmp = Ra + Rb_or_imm;
1145473Snate@binkert.org                // signed overflow occurs when operands have same sign
1158234Snate@binkert.org                // and sign of result does not match.
1168234Snate@binkert.org                if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1178234Snate@binkert.org                    fault = new IntegerOverflowFault;
1188234Snate@binkert.org                Rc = tmp;
1196171Snate@binkert.org            }});
1208234Snate@binkert.org            0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
1218234Snate@binkert.org            0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
1228234Snate@binkert.org
1238234Snate@binkert.org            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
1248234Snate@binkert.org            0x49: sublv({{
1258234Snate@binkert.org                uint32_t tmp  = Ra.sl - Rb_or_imm.sl;
1268234Snate@binkert.org                // signed overflow detection is same as for add,
1278234Snate@binkert.org                // except we need to look at the *complemented*
1288234Snate@binkert.org                // sign bit of the subtrahend (Rb), i.e., if the initial
1296171Snate@binkert.org                // signs are the *same* then no overflow can occur
1308219Snate@binkert.org                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1318327Sgblack@eecs.umich.edu                    fault = new IntegerOverflowFault;
1329512Sandreas@sandberg.pp.se                Rc.sl = tmp;
1339512Sandreas@sandberg.pp.se            }});
1349512Sandreas@sandberg.pp.se            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1359512Sandreas@sandberg.pp.se            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1369512Sandreas@sandberg.pp.se
1379512Sandreas@sandberg.pp.se            0x29: subq({{ Rc = Ra - Rb_or_imm; }});
1388219Snate@binkert.org            0x69: subqv({{
1398219Snate@binkert.org                uint64_t tmp  = Ra - Rb_or_imm;
1409512Sandreas@sandberg.pp.se                // signed overflow detection is same as for add,
1419512Sandreas@sandberg.pp.se                // except we need to look at the *complemented*
1429512Sandreas@sandberg.pp.se                // sign bit of the subtrahend (Rb), i.e., if the initial
1439512Sandreas@sandberg.pp.se                // signs are the *same* then no overflow can occur
1449512Sandreas@sandberg.pp.se                if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1459512Sandreas@sandberg.pp.se                    fault = new IntegerOverflowFault;
1469512Sandreas@sandberg.pp.se                Rc = tmp;
1479512Sandreas@sandberg.pp.se            }});
1489512Sandreas@sandberg.pp.se            0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1499512Sandreas@sandberg.pp.se            0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1509512Sandreas@sandberg.pp.se
1519512Sandreas@sandberg.pp.se            0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1529512Sandreas@sandberg.pp.se            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1539512Sandreas@sandberg.pp.se            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
1549512Sandreas@sandberg.pp.se            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1559512Sandreas@sandberg.pp.se            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
1569512Sandreas@sandberg.pp.se
1579512Sandreas@sandberg.pp.se            0x0f: cmpbge({{
1589512Sandreas@sandberg.pp.se                int hi = 7;
1599512Sandreas@sandberg.pp.se                int lo = 0;
1609512Sandreas@sandberg.pp.se                uint64_t tmp = 0;
1619512Sandreas@sandberg.pp.se                for (int i = 0; i < 8; ++i) {
1628219Snate@binkert.org                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1639512Sandreas@sandberg.pp.se                    hi += 8;
1649512Sandreas@sandberg.pp.se                    lo += 8;
1659512Sandreas@sandberg.pp.se                }
1668219Snate@binkert.org                Rc = tmp;
1678219Snate@binkert.org            }});
1688234Snate@binkert.org        }
1698245Snate@binkert.org
1708245Snate@binkert.org        0x11: decode INTFUNC {	// integer logical operations
1715801Snate@binkert.org
1725801Snate@binkert.org            0x00: and({{ Rc = Ra & Rb_or_imm; }});
1735801Snate@binkert.org            0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1744167Sbinkertn@umich.edu            0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1754042Sbinkertn@umich.edu            0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1765801Snate@binkert.org            0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1775799Snate@binkert.org            0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1785799Snate@binkert.org
1798234Snate@binkert.org            // conditional moves
1808234Snate@binkert.org            0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
1818234Snate@binkert.org            0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
1828234Snate@binkert.org            0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
1838234Snate@binkert.org            0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
1848234Snate@binkert.org            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
1858234Snate@binkert.org            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
1868234Snate@binkert.org            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
1878234Snate@binkert.org            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
1888245Snate@binkert.org
1898245Snate@binkert.org            // For AMASK, RA must be R31.
1905799Snate@binkert.org            0x61: decode RA {
1915799Snate@binkert.org                31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
1925799Snate@binkert.org            }
1935799Snate@binkert.org
1945802Snate@binkert.org            // For IMPLVER, RA must be R31 and the B operand
1952889Sbinkertn@umich.edu            // must be the immediate value 1.
1965524Sstever@gmail.com            0x6c: decode RA {
1975524Sstever@gmail.com                31: decode IMM {
1985524Sstever@gmail.com                    1: decode INTIMM {
1995524Sstever@gmail.com                        // return EV5 for FULL_SYSTEM and EV6 otherwise
2005524Sstever@gmail.com                        1: implver({{
2015524Sstever@gmail.com#if FULL_SYSTEM
2025524Sstever@gmail.com                             Rc = 1;
2035524Sstever@gmail.com#else
2045524Sstever@gmail.com                             Rc = 2;
2055524Sstever@gmail.com#endif
2065524Sstever@gmail.com                        }});
2075524Sstever@gmail.com                    }
2085524Sstever@gmail.com                }
2095524Sstever@gmail.com            }
2105524Sstever@gmail.com
2115524Sstever@gmail.com#if FULL_SYSTEM
2125524Sstever@gmail.com            // The mysterious 11.25...
2135524Sstever@gmail.com            0x25: WarnUnimpl::eleven25();
2145524Sstever@gmail.com#endif
2155524Sstever@gmail.com        }
2165524Sstever@gmail.com
2175524Sstever@gmail.com        0x12: decode INTFUNC {
2185524Sstever@gmail.com            0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
2195524Sstever@gmail.com            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
2205524Sstever@gmail.com            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
2215524Sstever@gmail.com
2225524Sstever@gmail.com            0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
2232889Sbinkertn@umich.edu            0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
2244850Snate@binkert.org            0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
2254850Snate@binkert.org            0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
2264850Snate@binkert.org
2274850Snate@binkert.org            0x52: mskwh({{
2284850Snate@binkert.org                int bv = Rb_or_imm<2:0>;
2295801Snate@binkert.org                Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
2304850Snate@binkert.org            }});
2315801Snate@binkert.org            0x62: msklh({{
2324850Snate@binkert.org                int bv = Rb_or_imm<2:0>;
2334850Snate@binkert.org                Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
2345801Snate@binkert.org            }});
2354850Snate@binkert.org            0x72: mskqh({{
2364850Snate@binkert.org                int bv = Rb_or_imm<2:0>;
2374850Snate@binkert.org                Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
2382889Sbinkertn@umich.edu            }});
2392889Sbinkertn@umich.edu
2408333Snate@binkert.org            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
2412889Sbinkertn@umich.edu            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
2422889Sbinkertn@umich.edu            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
2432889Sbinkertn@umich.edu            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
2442889Sbinkertn@umich.edu
2452889Sbinkertn@umich.edu            0x5a: extwh({{
2462889Sbinkertn@umich.edu                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
2472889Sbinkertn@umich.edu            0x6a: extlh({{
2482889Sbinkertn@umich.edu                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
2492889Sbinkertn@umich.edu            0x7a: extqh({{
2508232Snate@binkert.org                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
2514053Sbinkertn@umich.edu
2525799Snate@binkert.org            0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
2538232Snate@binkert.org            0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
2544053Sbinkertn@umich.edu            0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
2555473Snate@binkert.org            0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
2565473Snate@binkert.org
2575473Snate@binkert.org            0x57: inswh({{
2585473Snate@binkert.org                int bv = Rb_or_imm<2:0>;
2595473Snate@binkert.org                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
2605473Snate@binkert.org            }});
2615473Snate@binkert.org            0x67: inslh({{
2625473Snate@binkert.org                int bv = Rb_or_imm<2:0>;
2635473Snate@binkert.org                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2645473Snate@binkert.org            }});
2655473Snate@binkert.org            0x77: insqh({{
2665473Snate@binkert.org                int bv = Rb_or_imm<2:0>;
2675473Snate@binkert.org                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
2685473Snate@binkert.org            }});
2695473Snate@binkert.org
2705473Snate@binkert.org            0x30: zap({{
2715473Snate@binkert.org                uint64_t zapmask = 0;
2725473Snate@binkert.org                for (int i = 0; i < 8; ++i) {
2735473Snate@binkert.org                    if (Rb_or_imm<i:>)
2745473Snate@binkert.org                        zapmask |= (mask(8) << (i * 8));
2755473Snate@binkert.org                }
2762889Sbinkertn@umich.edu                Rc = Ra & ~zapmask;
2772889Sbinkertn@umich.edu            }});
2782889Sbinkertn@umich.edu            0x31: zapnot({{
2795470Snate@binkert.org                uint64_t zapmask = 0;
2805470Snate@binkert.org                for (int i = 0; i < 8; ++i) {
2815470Snate@binkert.org                    if (!Rb_or_imm<i:>)
2825470Snate@binkert.org                        zapmask |= (mask(8) << (i * 8));
2835470Snate@binkert.org                }
2842889Sbinkertn@umich.edu                Rc = Ra & ~zapmask;
2858333Snate@binkert.org            }});
2862889Sbinkertn@umich.edu        }
2872889Sbinkertn@umich.edu
2885801Snate@binkert.org        0x13: decode INTFUNC {	// integer multiplies
2898327Sgblack@eecs.umich.edu            0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
2905456Ssaidi@eecs.umich.edu            0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
2918327Sgblack@eecs.umich.edu            0x30: umulh({{
2928327Sgblack@eecs.umich.edu                uint64_t hi, lo;
2938327Sgblack@eecs.umich.edu                mul128(Ra, Rb_or_imm, hi, lo);
2945528Sstever@gmail.com                Rc = hi;
2952967Sktlim@umich.edu            }}, IntMultOp);
2962967Sktlim@umich.edu            0x40: mullv({{
2972967Sktlim@umich.edu                // 32-bit multiply with trap on overflow
2982967Sktlim@umich.edu                int64_t Rax = Ra.sl;	// sign extended version of Ra.sl
2992889Sbinkertn@umich.edu                int64_t Rbx = Rb_or_imm.sl;
3002889Sbinkertn@umich.edu                int64_t tmp = Rax * Rbx;
3012889Sbinkertn@umich.edu                // To avoid overflow, all the upper 32 bits must match
3022922Sktlim@umich.edu                // the sign bit of the lower 32.  We code this as
3032922Sktlim@umich.edu                // checking the upper 33 bits for all 0s or all 1s.
3044053Sbinkertn@umich.edu                uint64_t sign_bits = tmp<63:31>;
3055470Snate@binkert.org                if (sign_bits != 0 && sign_bits != mask(33))
3062889Sbinkertn@umich.edu                    fault = new IntegerOverflowFault;
3072889Sbinkertn@umich.edu                Rc.sl = tmp<31:0>;
3085801Snate@binkert.org            }}, IntMultOp);
3092889Sbinkertn@umich.edu            0x60: mulqv({{
3102889Sbinkertn@umich.edu                // 64-bit multiply with trap on overflow
3112889Sbinkertn@umich.edu                uint64_t hi, lo;
3122889Sbinkertn@umich.edu                mul128(Ra, Rb_or_imm, hi, lo);
3132889Sbinkertn@umich.edu                // all the upper 64 bits must match the sign bit of
3145801Snate@binkert.org                // the lower 64
3152889Sbinkertn@umich.edu                if (!((hi == 0 && lo<63:> == 0) ||
3162889Sbinkertn@umich.edu                      (hi == mask(64) && lo<63:> == 1)))
3175801Snate@binkert.org                    fault = new IntegerOverflowFault;
3183645Sbinkertn@umich.edu                Rc = lo;
3195801Snate@binkert.org            }}, IntMultOp);
3202889Sbinkertn@umich.edu        }
3218232Snate@binkert.org
3225799Snate@binkert.org        0x1c: decode INTFUNC {
3234053Sbinkertn@umich.edu            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
3245586Snate@binkert.org            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
3255586Snate@binkert.org            0x32: ctlz({{
3268232Snate@binkert.org                             uint64_t count = 0;
3275586Snate@binkert.org                             uint64_t temp = Rb;
3285586Snate@binkert.org                             if (temp<63:32>) temp >>= 32; else count += 32;
3295586Snate@binkert.org                             if (temp<31:16>) temp >>= 16; else count += 16;
3305586Snate@binkert.org                             if (temp<15:8>) temp >>= 8; else count += 8;
3318232Snate@binkert.org                             if (temp<7:4>) temp >>= 4; else count += 4;
3328232Snate@binkert.org                             if (temp<3:2>) temp >>= 2; else count += 2;
3338232Snate@binkert.org                             if (temp<1:1>) temp >>= 1; else count += 1;
3345586Snate@binkert.org                             if ((temp<0:0>) != 0x1) count += 1;
3354053Sbinkertn@umich.edu                             Rc = count;
3365586Snate@binkert.org                           }}, IntAluOp);
3378232Snate@binkert.org
3385586Snate@binkert.org            0x33: cttz({{
3398232Snate@binkert.org                             uint64_t count = 0;
3404053Sbinkertn@umich.edu                             uint64_t temp = Rb;
3414074Sbinkertn@umich.edu                             if (!(temp<31:0>)) { temp >>= 32; count += 32; }
3425799Snate@binkert.org                             if (!(temp<15:0>)) { temp >>= 16; count += 16; }
3435950Ssaidi@eecs.umich.edu                             if (!(temp<7:0>)) { temp >>= 8; count += 8; }
3445606Snate@binkert.org                             if (!(temp<3:0>)) { temp >>= 4; count += 4; }
3454074Sbinkertn@umich.edu                             if (!(temp<1:0>)) { temp >>= 2; count += 2; }
3465799Snate@binkert.org                             if (!(temp<0:0> & ULL(0x1))) count += 1;
3474042Sbinkertn@umich.edu                             Rc = count;
3485799Snate@binkert.org                           }}, IntAluOp);
3494042Sbinkertn@umich.edu
3504042Sbinkertn@umich.edu            format FailUnimpl {
3515799Snate@binkert.org                0x30: ctpop();
3525799Snate@binkert.org                0x31: perr();
3532889Sbinkertn@umich.edu                0x34: unpkbw();
3542889Sbinkertn@umich.edu                0x35: unpkbl();
3552889Sbinkertn@umich.edu                0x36: pkwb();
3562891Sbinkertn@umich.edu                0x37: pklb();
3575604Snate@binkert.org                0x38: minsb8();
3585604Snate@binkert.org                0x39: minsw4();
3595604Snate@binkert.org                0x3a: minub8();
3605604Snate@binkert.org                0x3b: minuw4();
3613887Sbinkertn@umich.edu                0x3c: maxub8();
3622899Sbinkertn@umich.edu                0x3d: maxuw4();
3632899Sbinkertn@umich.edu                0x3e: maxsb8();
3642899Sbinkertn@umich.edu                0x3f: maxsw4();
3654042Sbinkertn@umich.edu            }
3662899Sbinkertn@umich.edu
3672899Sbinkertn@umich.edu            format BasicOperateWithNopCheck {
3682899Sbinkertn@umich.edu                0x70: decode RB {
3692899Sbinkertn@umich.edu                    31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
3705604Snate@binkert.org                }
3715604Snate@binkert.org                0x78: decode RB {
3725604Snate@binkert.org                    31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
3735604Snate@binkert.org                              FloatCvtOp);
3745604Snate@binkert.org                }
3755604Snate@binkert.org            }
3765604Snate@binkert.org        }
3775604Snate@binkert.org    }
3785604Snate@binkert.org
3795604Snate@binkert.org    // Conditional branches.
3805604Snate@binkert.org    format CondBranch {
3815604Snate@binkert.org        0x39: beq({{ cond = (Ra == 0); }});
3825604Snate@binkert.org        0x3d: bne({{ cond = (Ra != 0); }});
3835604Snate@binkert.org        0x3e: bge({{ cond = (Ra.sq >= 0); }});
3845604Snate@binkert.org        0x3f: bgt({{ cond = (Ra.sq >  0); }});
3855604Snate@binkert.org        0x3b: ble({{ cond = (Ra.sq <= 0); }});
3862899Sbinkertn@umich.edu        0x3a: blt({{ cond = (Ra.sq < 0); }});
3875604Snate@binkert.org        0x38: blbc({{ cond = ((Ra & 1) == 0); }});
3882889Sbinkertn@umich.edu        0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
3892889Sbinkertn@umich.edu
3902889Sbinkertn@umich.edu        0x31: fbeq({{ cond = (Fa == 0); }});
3918219Snate@binkert.org        0x35: fbne({{ cond = (Fa != 0); }});
3922889Sbinkertn@umich.edu        0x36: fbge({{ cond = (Fa >= 0); }});
3932889Sbinkertn@umich.edu        0x37: fbgt({{ cond = (Fa >  0); }});
3942889Sbinkertn@umich.edu        0x33: fble({{ cond = (Fa <= 0); }});
3952889Sbinkertn@umich.edu        0x32: fblt({{ cond = (Fa < 0); }});
3968234Snate@binkert.org    }
3978234Snate@binkert.org
3982889Sbinkertn@umich.edu    // unconditional branches
3992889Sbinkertn@umich.edu    format UncondBranch {
4002889Sbinkertn@umich.edu        0x30: br();
4012889Sbinkertn@umich.edu        0x34: bsr(IsCall);
4022889Sbinkertn@umich.edu    }
4032889Sbinkertn@umich.edu
404    // indirect branches
405    0x1a: decode JMPFUNC {
406        format Jump {
407            0: jmp();
408            1: jsr(IsCall);
409            2: ret(IsReturn);
410            3: jsr_coroutine(IsCall, IsReturn);
411        }
412    }
413
414    // Square root and integer-to-FP moves
415    0x14: decode FP_SHORTFUNC {
416        // Integer to FP register moves must have RB == 31
417        0x4: decode RB {
418            31: decode FP_FULLFUNC {
419                format BasicOperateWithNopCheck {
420                    0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
421                    0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
422                    0x014: FailUnimpl::itoff();	// VAX-format conversion
423                }
424            }
425        }
426
427        // Square root instructions must have FA == 31
428        0xb: decode FA {
429            31: decode FP_TYPEFUNC {
430                format FloatingPointOperate {
431#if SS_COMPATIBLE_FP
432                    0x0b: sqrts({{
433                        if (Fb < 0.0)
434                            fault = new ArithmeticFault;
435                        Fc = sqrt(Fb);
436                    }}, FloatSqrtOp);
437#else
438                    0x0b: sqrts({{
439                        if (Fb.sf < 0.0)
440                            fault = new ArithmeticFault;
441                        Fc.sf = sqrt(Fb.sf);
442                    }}, FloatSqrtOp);
443#endif
444                    0x2b: sqrtt({{
445                        if (Fb < 0.0)
446                            fault = new ArithmeticFault;
447                        Fc = sqrt(Fb);
448                    }}, FloatSqrtOp);
449                }
450            }
451        }
452
453        // VAX-format sqrtf and sqrtg are not implemented
454        0xa: FailUnimpl::sqrtfg();
455    }
456
457    // IEEE floating point
458    0x16: decode FP_SHORTFUNC_TOP2 {
459        // The top two bits of the short function code break this
460        // space into four groups: binary ops, compares, reserved, and
461        // conversions.  See Table 4-12 of AHB.  There are different
462        // special cases in these different groups, so we decode on
463        // these top two bits first just to select a decode strategy.
464        // Most of these instructions may have various trapping and
465        // rounding mode flags set; these are decoded in the
466        // FloatingPointDecode template used by the
467        // FloatingPointOperate format.
468
469        // add/sub/mul/div: just decode on the short function code
470        // and source type.  All valid trapping and rounding modes apply.
471        0: decode FP_TRAPMODE {
472            // check for valid trapping modes here
473            0,1,5,7: decode FP_TYPEFUNC {
474                   format FloatingPointOperate {
475#if SS_COMPATIBLE_FP
476                       0x00: adds({{ Fc = Fa + Fb; }});
477                       0x01: subs({{ Fc = Fa - Fb; }});
478                       0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
479                       0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
480#else
481                       0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
482                       0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
483                       0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
484                       0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
485#endif
486
487                       0x20: addt({{ Fc = Fa + Fb; }});
488                       0x21: subt({{ Fc = Fa - Fb; }});
489                       0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
490                       0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
491                   }
492             }
493        }
494
495        // Floating-point compare instructions must have the default
496        // rounding mode, and may use the default trapping mode or
497        // /SU.  Both trapping modes are treated the same by M5; the
498        // only difference on the real hardware (as far a I can tell)
499        // is that without /SU you'd get an imprecise trap if you
500        // tried to compare a NaN with something else (instead of an
501        // "unordered" result).
502        1: decode FP_FULLFUNC {
503            format BasicOperateWithNopCheck {
504                0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
505                                     FloatCmpOp);
506                0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
507                                     FloatCmpOp);
508                0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
509                                     FloatCmpOp);
510                0x0a4, 0x5a4: cmptun({{ // unordered
511                    Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
512                }}, FloatCmpOp);
513            }
514        }
515
516        // The FP-to-integer and integer-to-FP conversion insts
517        // require that FA be 31.
518        3: decode FA {
519            31: decode FP_TYPEFUNC {
520                format FloatingPointOperate {
521                    0x2f: decode FP_ROUNDMODE {
522                        format FPFixedRounding {
523                            // "chopped" i.e. round toward zero
524                            0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
525                                     Chopped);
526                            // round to minus infinity
527                            1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
528                                     MinusInfinity);
529                        }
530                      default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
531                    }
532
533                    // The cvtts opcode is overloaded to be cvtst if the trap
534                    // mode is 2 or 6 (which are not valid otherwise)
535                    0x2c: decode FP_FULLFUNC {
536                        format BasicOperateWithNopCheck {
537                            // trap on denorm version "cvtst/s" is
538                            // simulated same as cvtst
539                            0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
540                        }
541                      default: cvtts({{ Fc.sf = Fb; }});
542                    }
543
544                    // The trapping mode for integer-to-FP conversions
545                    // must be /SUI or nothing; /U and /SU are not
546                    // allowed.  The full set of rounding modes are
547                    // supported though.
548                    0x3c: decode FP_TRAPMODE {
549                        0,7: cvtqs({{ Fc.sf = Fb.sq; }});
550                    }
551                    0x3e: decode FP_TRAPMODE {
552                        0,7: cvtqt({{ Fc    = Fb.sq; }});
553                    }
554                }
555            }
556        }
557    }
558
559    // misc FP operate
560    0x17: decode FP_FULLFUNC {
561        format BasicOperateWithNopCheck {
562            0x010: cvtlq({{
563                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
564            }});
565            0x030: cvtql({{
566                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
567            }});
568
569            // We treat the precise & imprecise trapping versions of
570            // cvtql identically.
571            0x130, 0x530: cvtqlv({{
572                // To avoid overflow, all the upper 32 bits must match
573                // the sign bit of the lower 32.  We code this as
574                // checking the upper 33 bits for all 0s or all 1s.
575                uint64_t sign_bits = Fb.uq<63:31>;
576                if (sign_bits != 0 && sign_bits != mask(33))
577                    fault = new IntegerOverflowFault;
578                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
579            }});
580
581            0x020: cpys({{  // copy sign
582                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
583            }});
584            0x021: cpysn({{ // copy sign negated
585                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
586            }});
587            0x022: cpyse({{ // copy sign and exponent
588                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
589            }});
590
591            0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
592            0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
593            0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
594            0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
595            0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
596            0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
597
598            0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsSerializing, IsSerializeBefore);
599            0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsSerializing, IsSerializeBefore);
600        }
601    }
602
603    // miscellaneous mem-format ops
604    0x18: decode MEMFUNC {
605        format WarnUnimpl {
606            0x8000: fetch();
607            0xa000: fetch_m();
608            0xe800: ecb();
609        }
610
611        format MiscPrefetch {
612            0xf800: wh64({{ EA = Rb & ~ULL(63); }},
613                         {{ xc->writeHint(EA, 64, memAccessFlags); }},
614                         mem_flags = NO_FAULT,
615                         inst_flags = [IsMemRef, IsDataPrefetch,
616                                       IsStore, MemWriteOp]);
617        }
618
619        format BasicOperate {
620            0xc000: rpcc({{
621#if FULL_SYSTEM
622        /* Rb is a fake dependency so here is a fun way to get
623         * the parser to understand that.
624         */
625                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
626
627#else
628                Ra = curTick;
629#endif
630            }}, IsUnverifiable);
631
632            // All of the barrier instructions below do nothing in
633            // their execute() methods (hence the empty code blocks).
634            // All of their functionality is hard-coded in the
635            // pipeline based on the flags IsSerializing,
636            // IsMemBarrier, and IsWriteBarrier.  In the current
637            // detailed CPU model, the execute() function only gets
638            // called at fetch, so there's no way to generate pipeline
639            // behavior at any other stage.  Once we go to an
640            // exec-in-exec CPU model we should be able to get rid of
641            // these flags and implement this behavior via the
642            // execute() methods.
643
644            // trapb is just a barrier on integer traps, where excb is
645            // a barrier on integer and FP traps.  "EXCB is thus a
646            // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
647            // them the same though.
648            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
649            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
650            0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
651            0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
652        }
653
654#if FULL_SYSTEM
655        format BasicOperate {
656            0xe000: rc({{
657                Ra = xc->readIntrFlag();
658                xc->setIntrFlag(0);
659            }}, IsNonSpeculative);
660            0xf000: rs({{
661                Ra = xc->readIntrFlag();
662                xc->setIntrFlag(1);
663            }}, IsNonSpeculative);
664        }
665#else
666        format FailUnimpl {
667            0xe000: rc();
668            0xf000: rs();
669        }
670#endif
671    }
672
673#if FULL_SYSTEM
674    0x00: CallPal::call_pal({{
675        if (!palValid ||
676            (palPriv
677             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
678            // invalid pal function code, or attempt to do privileged
679            // PAL call in non-kernel mode
680            fault = new UnimplementedOpcodeFault;
681        }
682        else {
683            // check to see if simulator wants to do something special
684            // on this PAL call (including maybe suppress it)
685            bool dopal = xc->simPalCheck(palFunc);
686
687            if (dopal) {
688                xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
689                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
690            }
691        }
692    }}, IsNonSpeculative);
693#else
694    0x00: decode PALFUNC {
695        format EmulatedCallPal {
696            0x00: halt ({{
697                SimExit(curTick, "halt instruction encountered");
698            }}, IsNonSpeculative);
699            0x83: callsys({{
700                xc->syscall();
701            }}, IsNonSpeculative, IsSerializeAfter);
702            // Read uniq reg into ABI return value register (r0)
703            0x9e: rduniq({{ R0 = Runiq; }}, IsSerializing, IsSerializeBefore);
704            // Write uniq reg with value from ABI arg register (r16)
705            0x9f: wruniq({{ Runiq = R16; }}, IsSerializing, IsSerializeBefore);
706        }
707    }
708#endif
709
710#if FULL_SYSTEM
711    0x1b: decode PALMODE {
712        0: OpcdecFault::hw_st_quad();
713        1: decode HW_LDST_QUAD {
714            format HwLoad {
715                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
716                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
717            }
718        }
719    }
720
721    0x1f: decode PALMODE {
722        0: OpcdecFault::hw_st_cond();
723        format HwStore {
724            1: decode HW_LDST_COND {
725                0: decode HW_LDST_QUAD {
726                    0: hw_st({{ EA = (Rb + disp) & ~3; }},
727                {{ Mem.ul = Ra<31:0>; }}, L);
728                    1: hw_st({{ EA = (Rb + disp) & ~7; }},
729                {{ Mem.uq = Ra.uq; }}, Q);
730                }
731
732                1: FailUnimpl::hw_st_cond();
733            }
734        }
735    }
736
737    0x19: decode PALMODE {
738        0: OpcdecFault::hw_mfpr();
739        format HwMoveIPR {
740            1: hw_mfpr({{
741                Ra = xc->readMiscRegWithEffect(ipr_index, fault);
742            }}, IsSerializing, IsSerializeBefore);
743        }
744    }
745
746    0x1d: decode PALMODE {
747        0: OpcdecFault::hw_mtpr();
748        format HwMoveIPR {
749            1: hw_mtpr({{
750                xc->setMiscRegWithEffect(ipr_index, Ra);
751                if (traceData) { traceData->setData(Ra); }
752            }}, IsSerializing, IsSerializeBefore);
753        }
754    }
755
756    format BasicOperate {
757        0x1e: decode PALMODE {
758            0: OpcdecFault::hw_rei();
759            1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
760        }
761
762        // M5 special opcodes use the reserved 0x01 opcode space
763        0x01: decode M5FUNC {
764            0x00: arm({{
765                AlphaPseudo::arm(xc->xcBase());
766            }}, IsNonSpeculative);
767            0x01: quiesce({{
768                AlphaPseudo::quiesce(xc->xcBase());
769            }}, IsNonSpeculative, IsQuiesce);
770            0x02: quiesceNs({{
771                AlphaPseudo::quiesceNs(xc->xcBase(), R16);
772            }}, IsNonSpeculative, IsQuiesce);
773            0x03: quiesceCycles({{
774                AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
775            }}, IsNonSpeculative, IsQuiesce);
776            0x04: quiesceTime({{
777                R0 = AlphaPseudo::quiesceTime(xc->xcBase());
778            }}, IsNonSpeculative);
779            0x10: ivlb({{
780                AlphaPseudo::ivlb(xc->xcBase());
781            }}, No_OpClass, IsNonSpeculative);
782            0x11: ivle({{
783                AlphaPseudo::ivle(xc->xcBase());
784            }}, No_OpClass, IsNonSpeculative);
785            0x20: m5exit_old({{
786                AlphaPseudo::m5exit_old(xc->xcBase());
787            }}, No_OpClass, IsNonSpeculative);
788            0x21: m5exit({{
789                AlphaPseudo::m5exit(xc->xcBase(), R16);
790            }}, No_OpClass, IsNonSpeculative);
791            0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }});
792            0x40: resetstats({{
793                AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
794            }}, IsNonSpeculative);
795            0x41: dumpstats({{
796                AlphaPseudo::dumpstats(xc->xcBase(), R16, R17);
797            }}, IsNonSpeculative);
798            0x42: dumpresetstats({{
799                AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17);
800            }}, IsNonSpeculative);
801            0x43: m5checkpoint({{
802                AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17);
803            }}, IsNonSpeculative);
804            0x50: m5readfile({{
805                R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18);
806            }}, IsNonSpeculative);
807            0x51: m5break({{
808                AlphaPseudo::debugbreak(xc->xcBase());
809            }}, IsNonSpeculative);
810            0x52: m5switchcpu({{
811                AlphaPseudo::switchcpu(xc->xcBase());
812            }}, IsNonSpeculative);
813            0x53: m5addsymbol({{
814                AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
815            }}, IsNonSpeculative);
816            0x54: m5panic({{
817                panic("M5 panic instruction called.");
818            }}, IsNonSpeculative);
819
820        }
821    }
822#endif
823}
824