decoder.isa revision 8560
12292SN/A// -*- mode:c++ -*- 22329SN/A 32292SN/A// Copyright (c) 2003-2006 The Regents of The University of Michigan 42292SN/A// All rights reserved. 52292SN/A// 62292SN/A// Redistribution and use in source and binary forms, with or without 72292SN/A// modification, are permitted provided that the following conditions are 82292SN/A// met: redistributions of source code must retain the above copyright 92292SN/A// notice, this list of conditions and the following disclaimer; 102292SN/A// redistributions in binary form must reproduce the above copyright 112292SN/A// notice, this list of conditions and the following disclaimer in the 122292SN/A// documentation and/or other materials provided with the distribution; 132292SN/A// neither the name of the copyright holders nor the names of its 142292SN/A// contributors may be used to endorse or promote products derived from 152292SN/A// this software without specific prior written permission. 162292SN/A// 172292SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182292SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192292SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202292SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212292SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222292SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232292SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242292SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252292SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262292SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272689Sktlim@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282689Sktlim@umich.edu// 292689Sktlim@umich.edu// Authors: Steve Reinhardt 302292SN/A 312292SN/A//////////////////////////////////////////////////////////////////// 322292SN/A// 332292SN/A// The actual decoder specification 342292SN/A// 352329SN/A 362292SN/Adecode OPCODE default Unknown::unknown() { 372292SN/A 382292SN/A format LoadAddress { 392329SN/A 0x08: lda({{ Ra = Rb + disp; }}); 403326Sktlim@umich.edu 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 412292SN/A } 422292SN/A 432292SN/A format LoadOrNop { 443348Sbinkertn@umich.edu 0x0a: ldbu({{ Ra.uq = Mem.ub; }}); 452669Sktlim@umich.edu 0x0c: ldwu({{ Ra.uq = Mem.uw; }}); 462292SN/A 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 472292SN/A 0x23: ldt({{ Fa = Mem.df; }}); 482329SN/A 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC); 492329SN/A 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC); 502329SN/A } 512329SN/A 522329SN/A format LoadOrPrefetch { 532329SN/A 0x28: ldl({{ Ra.sl = Mem.sl; }}); 542329SN/A 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT); 552329SN/A // IsFloating flag on lds gets the prefetch to disassemble 562329SN/A // using f31 instead of r31... funcitonally it's unnecessary 572329SN/A 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }}, 582292SN/A pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 592292SN/A } 602292SN/A 612292SN/A format Store { 622292SN/A 0x0e: stb({{ Mem.ub = Ra<7:0>; }}); 632292SN/A 0x0d: stw({{ Mem.uw = Ra<15:0>; }}); 642292SN/A 0x2c: stl({{ Mem.ul = Ra<31:0>; }}); 652733Sktlim@umich.edu 0x2d: stq({{ Mem.uq = Ra.uq; }}); 662292SN/A 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 672292SN/A 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 682907Sktlim@umich.edu 0x27: stt({{ Mem.df = Fa; }}); 692292SN/A } 702292SN/A 712292SN/A format StoreCond { 722292SN/A 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }}, 732292SN/A {{ 742292SN/A uint64_t tmp = write_result; 752292SN/A // see stq_c 762907Sktlim@umich.edu Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 772292SN/A if (tmp == 1) { 782292SN/A xc->setStCondFailures(0); 792292SN/A } 802292SN/A }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 812292SN/A 0x2f: stq_c({{ Mem.uq = Ra; }}, 822727Sktlim@umich.edu {{ 832727Sktlim@umich.edu uint64_t tmp = write_result; 842727Sktlim@umich.edu // If the write operation returns 0 or 1, then 852292SN/A // this was a conventional store conditional, 862733Sktlim@umich.edu // and the value indicates the success/failure 872292SN/A // of the operation. If another value is 882292SN/A // returned, then this was a Turbolaser 892292SN/A // mailbox access, and we don't update the 902292SN/A // result register at all. 912292SN/A Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 922907Sktlim@umich.edu if (tmp == 1) { 932907Sktlim@umich.edu // clear failure counter... this is 942907Sktlim@umich.edu // non-architectural and for debugging 952907Sktlim@umich.edu // only. 962348SN/A xc->setStCondFailures(0); 972307SN/A } 982307SN/A }}, mem_flags = LLSC, inst_flags = IsStoreConditional); 992348SN/A } 1002307SN/A 1012307SN/A format IntegerOperate { 1022348SN/A 1032307SN/A 0x10: decode INTFUNC { // integer arithmetic operations 1042307SN/A 1052292SN/A 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 1062292SN/A 0x40: addlv({{ 1072292SN/A int32_t tmp = Ra.sl + Rb_or_imm.sl; 1082292SN/A // signed overflow occurs when operands have same sign 1092292SN/A // and sign of result does not match. 1102292SN/A if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1112292SN/A fault = new IntegerOverflowFault; 1122292SN/A Rc.sl = tmp; 1132292SN/A }}); 1142292SN/A 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); 1152292SN/A 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }}); 1162292SN/A 1172292SN/A 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 1182292SN/A 0x60: addqv({{ 1192292SN/A uint64_t tmp = Ra + Rb_or_imm; 1202292SN/A // signed overflow occurs when operands have same sign 1212292SN/A // and sign of result does not match. 1222329SN/A if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1232292SN/A fault = new IntegerOverflowFault; 1242292SN/A Rc = tmp; 1252292SN/A }}); 1262292SN/A 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 1272292SN/A 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 1282292SN/A 1292292SN/A 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }}); 1302292SN/A 0x49: sublv({{ 1312292SN/A int32_t tmp = Ra.sl - Rb_or_imm.sl; 1322292SN/A // signed overflow detection is same as for add, 1332292SN/A // except we need to look at the *complemented* 1342292SN/A // sign bit of the subtrahend (Rb), i.e., if the initial 1352292SN/A // signs are the *same* then no overflow can occur 1362292SN/A if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1372790Sktlim@umich.edu fault = new IntegerOverflowFault; 1382790Sktlim@umich.edu Rc.sl = tmp; 1392669Sktlim@umich.edu }}); 1402669Sktlim@umich.edu 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); 1412292SN/A 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }}); 1422292SN/A 1432292SN/A 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 1442292SN/A 0x69: subqv({{ 1452292SN/A uint64_t tmp = Ra - Rb_or_imm; 1462292SN/A // signed overflow detection is same as for add, 1472292SN/A // except we need to look at the *complemented* 1482292SN/A // sign bit of the subtrahend (Rb), i.e., if the initial 1492292SN/A // signs are the *same* then no overflow can occur 1502292SN/A if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1512292SN/A fault = new IntegerOverflowFault; 1522292SN/A Rc = tmp; 1532292SN/A }}); 1542292SN/A 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 1552292SN/A 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 1562292SN/A 1572292SN/A 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 1582292SN/A 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }}); 1592292SN/A 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }}); 1602292SN/A 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }}); 1612292SN/A 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }}); 1622292SN/A 1632292SN/A 0x0f: cmpbge({{ 1642329SN/A int hi = 7; 1652292SN/A int lo = 0; 1662292SN/A uint64_t tmp = 0; 1672292SN/A for (int i = 0; i < 8; ++i) { 1682348SN/A tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i; 1692292SN/A hi += 8; 1702292SN/A lo += 8; 1712292SN/A } 1722348SN/A Rc = tmp; 1732292SN/A }}); 1742292SN/A } 1752292SN/A 1762348SN/A 0x11: decode INTFUNC { // integer logical operations 1772292SN/A 1782292SN/A 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 1792292SN/A 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 1802292SN/A 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 1812292SN/A 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 1822292SN/A 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 1832292SN/A 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 1842292SN/A 1852292SN/A // conditional moves 1862292SN/A 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 1872292SN/A 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 1882292SN/A 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 1892292SN/A 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 1902292SN/A 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }}); 1912292SN/A 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }}); 1922292SN/A 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }}); 1932292SN/A 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }}); 1942292SN/A 1952292SN/A // For AMASK, RA must be R31. 1962292SN/A 0x61: decode RA { 1972292SN/A 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 1982292SN/A } 1992292SN/A 2002292SN/A // For IMPLVER, RA must be R31 and the B operand 2012292SN/A // must be the immediate value 1. 2022292SN/A 0x6c: decode RA { 2032292SN/A 31: decode IMM { 2042292SN/A 1: decode INTIMM { 2052292SN/A // return EV5 for FULL_SYSTEM and EV6 otherwise 2062292SN/A 1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }}); 2072292SN/A } 2082292SN/A } 2092292SN/A } 2102292SN/A 2112292SN/A // The mysterious 11.25... 2122678Sktlim@umich.edu 0x25: WarnUnimpl::eleven25(); 2132678Sktlim@umich.edu } 2142292SN/A 2152907Sktlim@umich.edu 0x12: decode INTFUNC { 2162907Sktlim@umich.edu 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 2172907Sktlim@umich.edu 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }}); 2182292SN/A 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }}); 2192698Sktlim@umich.edu 2202678Sktlim@umich.edu 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 2212678Sktlim@umich.edu 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 2222698Sktlim@umich.edu 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 2233349Sbinkertn@umich.edu 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 2242693Sktlim@umich.edu 2252292SN/A 0x52: mskwh({{ 2262292SN/A int bv = Rb_or_imm<2:0>; 2272292SN/A Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 2282292SN/A }}); 2292292SN/A 0x62: msklh({{ 2302292SN/A int bv = Rb_or_imm<2:0>; 2312292SN/A Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 2322292SN/A }}); 2332292SN/A 0x72: mskqh({{ 2342292SN/A int bv = Rb_or_imm<2:0>; 2352292SN/A Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 2362292SN/A }}); 2372329SN/A 2382329SN/A 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 2392329SN/A 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 2402329SN/A 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 2412292SN/A 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }}); 2422292SN/A 2432733Sktlim@umich.edu 0x5a: extwh({{ 2442292SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 2452292SN/A 0x6a: extlh({{ 2462292SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 2472292SN/A 0x7a: extqh({{ 2482907Sktlim@umich.edu Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 2492907Sktlim@umich.edu 2502669Sktlim@umich.edu 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 2512907Sktlim@umich.edu 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 2522907Sktlim@umich.edu 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 2532292SN/A 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 2542698Sktlim@umich.edu 2552678Sktlim@umich.edu 0x57: inswh({{ 2562678Sktlim@umich.edu int bv = Rb_or_imm<2:0>; 2572678Sktlim@umich.edu Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0; 2582698Sktlim@umich.edu }}); 2592678Sktlim@umich.edu 0x67: inslh({{ 2602678Sktlim@umich.edu int bv = Rb_or_imm<2:0>; 2612678Sktlim@umich.edu Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0; 2622678Sktlim@umich.edu }}); 2632698Sktlim@umich.edu 0x77: insqh({{ 2642678Sktlim@umich.edu int bv = Rb_or_imm<2:0>; 2652698Sktlim@umich.edu Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0; 2662678Sktlim@umich.edu }}); 2672698Sktlim@umich.edu 2682678Sktlim@umich.edu 0x30: zap({{ 2692698Sktlim@umich.edu uint64_t zapmask = 0; 2702678Sktlim@umich.edu for (int i = 0; i < 8; ++i) { 2712678Sktlim@umich.edu if (Rb_or_imm<i:>) 2722678Sktlim@umich.edu zapmask |= (mask(8) << (i * 8)); 2732698Sktlim@umich.edu } 2742678Sktlim@umich.edu Rc = Ra & ~zapmask; 2752678Sktlim@umich.edu }}); 2762678Sktlim@umich.edu 0x31: zapnot({{ 2772678Sktlim@umich.edu uint64_t zapmask = 0; 2782678Sktlim@umich.edu for (int i = 0; i < 8; ++i) { 2792678Sktlim@umich.edu if (!Rb_or_imm<i:>) 2802678Sktlim@umich.edu zapmask |= (mask(8) << (i * 8)); 2812678Sktlim@umich.edu } 2822678Sktlim@umich.edu Rc = Ra & ~zapmask; 2832678Sktlim@umich.edu }}); 2842678Sktlim@umich.edu } 2852678Sktlim@umich.edu 2862698Sktlim@umich.edu 0x13: decode INTFUNC { // integer multiplies 2872678Sktlim@umich.edu 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 2882678Sktlim@umich.edu 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 2892698Sktlim@umich.edu 0x30: umulh({{ 2902678Sktlim@umich.edu uint64_t hi, lo; 2912678Sktlim@umich.edu mul128(Ra, Rb_or_imm, hi, lo); 2922678Sktlim@umich.edu Rc = hi; 2932678Sktlim@umich.edu }}, IntMultOp); 2942678Sktlim@umich.edu 0x40: mullv({{ 2952678Sktlim@umich.edu // 32-bit multiply with trap on overflow 2962292SN/A int64_t Rax = Ra.sl; // sign extended version of Ra.sl 2972292SN/A int64_t Rbx = Rb_or_imm.sl; 2982292SN/A int64_t tmp = Rax * Rbx; 2992292SN/A // To avoid overflow, all the upper 32 bits must match 3002292SN/A // the sign bit of the lower 32. We code this as 3012292SN/A // checking the upper 33 bits for all 0s or all 1s. 3022292SN/A uint64_t sign_bits = tmp<63:31>; 3032292SN/A if (sign_bits != 0 && sign_bits != mask(33)) 3042292SN/A fault = new IntegerOverflowFault; 3052292SN/A Rc.sl = tmp<31:0>; 3062292SN/A }}, IntMultOp); 3072292SN/A 0x60: mulqv({{ 3082292SN/A // 64-bit multiply with trap on overflow 3092292SN/A uint64_t hi, lo; 3102292SN/A mul128(Ra, Rb_or_imm, hi, lo); 3112292SN/A // all the upper 64 bits must match the sign bit of 3122669Sktlim@umich.edu // the lower 64 3132669Sktlim@umich.edu if (!((hi == 0 && lo<63:> == 0) || 3142292SN/A (hi == mask(64) && lo<63:> == 1))) 3152292SN/A fault = new IntegerOverflowFault; 3162292SN/A Rc = lo; 3172292SN/A }}, IntMultOp); 3182292SN/A } 3192292SN/A 3202292SN/A 0x1c: decode INTFUNC { 3212292SN/A 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 3222292SN/A 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } 3232292SN/A 3242292SN/A 0x30: ctpop({{ 3252329SN/A uint64_t count = 0; 3262292SN/A for (int i = 0; Rb<63:i>; ++i) { 3272292SN/A if (Rb<i:i> == 0x1) 3282292SN/A ++count; 3292292SN/A } 3302292SN/A Rc = count; 3312292SN/A }}, IntAluOp); 3322292SN/A 3332292SN/A 0x31: perr({{ 3342292SN/A uint64_t temp = 0; 3352292SN/A int hi = 7; 3362329SN/A int lo = 0; 3372329SN/A for (int i = 0; i < 8; ++i) { 3382329SN/A uint8_t ra_ub = Ra.uq<hi:lo>; 3392292SN/A uint8_t rb_ub = Rb.uq<hi:lo>; 3402329SN/A temp += (ra_ub >= rb_ub) ? 3412329SN/A (ra_ub - rb_ub) : (rb_ub - ra_ub); 3422329SN/A hi += 8; 3432292SN/A lo += 8; 3442292SN/A } 3452292SN/A Rc = temp; 3462292SN/A }}); 3472329SN/A 3482292SN/A 0x32: ctlz({{ 3492292SN/A uint64_t count = 0; 3502292SN/A uint64_t temp = Rb; 3512292SN/A if (temp<63:32>) temp >>= 32; else count += 32; 3522292SN/A if (temp<31:16>) temp >>= 16; else count += 16; 3532292SN/A if (temp<15:8>) temp >>= 8; else count += 8; 3542292SN/A if (temp<7:4>) temp >>= 4; else count += 4; 3552292SN/A if (temp<3:2>) temp >>= 2; else count += 2; 3562292SN/A if (temp<1:1>) temp >>= 1; else count += 1; 3572292SN/A if ((temp<0:0>) != 0x1) count += 1; 3582292SN/A Rc = count; 3592329SN/A }}, IntAluOp); 3602329SN/A 3612292SN/A 0x33: cttz({{ 3622292SN/A uint64_t count = 0; 3632292SN/A uint64_t temp = Rb; 3642292SN/A if (!(temp<31:0>)) { temp >>= 32; count += 32; } 3652292SN/A if (!(temp<15:0>)) { temp >>= 16; count += 16; } 3662292SN/A if (!(temp<7:0>)) { temp >>= 8; count += 8; } 3672292SN/A if (!(temp<3:0>)) { temp >>= 4; count += 4; } 3682292SN/A if (!(temp<1:0>)) { temp >>= 2; count += 2; } 3692292SN/A if (!(temp<0:0> & ULL(0x1))) { 3702292SN/A temp >>= 1; count += 1; 3712292SN/A } 3722292SN/A if (!(temp<0:0> & ULL(0x1))) count += 1; 3732348SN/A Rc = count; 3742307SN/A }}, IntAluOp); 3752307SN/A 3762292SN/A 3772292SN/A 0x34: unpkbw({{ 3782292SN/A Rc = (Rb.uq<7:0> 3792292SN/A | (Rb.uq<15:8> << 16) 3802292SN/A | (Rb.uq<23:16> << 32) 3812292SN/A | (Rb.uq<31:24> << 48)); 3822292SN/A }}, IntAluOp); 3832292SN/A 3842292SN/A 0x35: unpkbl({{ 3852292SN/A Rc = (Rb.uq<7:0> | (Rb.uq<15:8> << 32)); 3862292SN/A }}, IntAluOp); 3872292SN/A 3882292SN/A 0x36: pkwb({{ 3892292SN/A Rc = (Rb.uq<7:0> 3902698Sktlim@umich.edu | (Rb.uq<23:16> << 8) 3912698Sktlim@umich.edu | (Rb.uq<39:32> << 16) 3922693Sktlim@umich.edu | (Rb.uq<55:48> << 24)); 3932698Sktlim@umich.edu }}, IntAluOp); 3942678Sktlim@umich.edu 3952678Sktlim@umich.edu 0x37: pklb({{ 3962329SN/A Rc = (Rb.uq<7:0> | (Rb.uq<39:32> << 8)); 3972292SN/A }}, IntAluOp); 3982292SN/A 3992348SN/A 0x38: minsb8({{ 4002292SN/A uint64_t temp = 0; 4012292SN/A int hi = 63; 4022348SN/A int lo = 56; 4032292SN/A for (int i = 7; i >= 0; --i) { 4042292SN/A int8_t ra_sb = Ra.uq<hi:lo>; 4052292SN/A int8_t rb_sb = Rb.uq<hi:lo>; 4062292SN/A temp = ((temp << 8) 4072292SN/A | ((ra_sb < rb_sb) ? Ra.uq<hi:lo> 4082292SN/A : Rb.uq<hi:lo>)); 4092292SN/A hi -= 8; 4102292SN/A lo -= 8; 4112727Sktlim@umich.edu } 4122727Sktlim@umich.edu Rc = temp; 4132307SN/A }}); 4143126Sktlim@umich.edu 4153126Sktlim@umich.edu 0x39: minsw4({{ 4163126Sktlim@umich.edu uint64_t temp = 0; 4173126Sktlim@umich.edu int hi = 63; 4183126Sktlim@umich.edu int lo = 48; 4193126Sktlim@umich.edu for (int i = 3; i >= 0; --i) { 4203126Sktlim@umich.edu int16_t ra_sw = Ra.uq<hi:lo>; 4213126Sktlim@umich.edu int16_t rb_sw = Rb.uq<hi:lo>; 4223126Sktlim@umich.edu temp = ((temp << 16) 4233126Sktlim@umich.edu | ((ra_sw < rb_sw) ? Ra.uq<hi:lo> 4243126Sktlim@umich.edu : Rb.uq<hi:lo>)); 4253126Sktlim@umich.edu hi -= 16; 4263126Sktlim@umich.edu lo -= 16; 4272727Sktlim@umich.edu } 4282727Sktlim@umich.edu Rc = temp; 4292727Sktlim@umich.edu }}); 4302727Sktlim@umich.edu 4312727Sktlim@umich.edu 0x3a: minub8({{ 4322727Sktlim@umich.edu uint64_t temp = 0; 4332727Sktlim@umich.edu int hi = 63; 4342727Sktlim@umich.edu int lo = 56; 4352727Sktlim@umich.edu for (int i = 7; i >= 0; --i) { 4362727Sktlim@umich.edu uint8_t ra_ub = Ra.uq<hi:lo>; 4372727Sktlim@umich.edu uint8_t rb_ub = Rb.uq<hi:lo>; 4382727Sktlim@umich.edu temp = ((temp << 8) 4392727Sktlim@umich.edu | ((ra_ub < rb_ub) ? Ra.uq<hi:lo> 4402727Sktlim@umich.edu : Rb.uq<hi:lo>)); 4412727Sktlim@umich.edu hi -= 8; 4422292SN/A lo -= 8; 4432292SN/A } 4442292SN/A Rc = temp; 4452669Sktlim@umich.edu }}); 4462292SN/A 4472292SN/A 0x3b: minuw4({{ 4482292SN/A uint64_t temp = 0; 4492669Sktlim@umich.edu int hi = 63; 4502292SN/A int lo = 48; 4512292SN/A for (int i = 3; i >= 0; --i) { 4522292SN/A uint16_t ra_sw = Ra.uq<hi:lo>; 4532292SN/A uint16_t rb_sw = Rb.uq<hi:lo>; 4542292SN/A temp = ((temp << 16) 4552292SN/A | ((ra_sw < rb_sw) ? Ra.uq<hi:lo> 4562292SN/A : Rb.uq<hi:lo>)); 4572292SN/A hi -= 16; 4582292SN/A lo -= 16; 4592292SN/A } 4602292SN/A Rc = temp; 4612292SN/A }}); 4622292SN/A 4632292SN/A 0x3c: maxub8({{ 4642292SN/A uint64_t temp = 0; 4652292SN/A int hi = 63; 4662292SN/A int lo = 56; 4672292SN/A for (int i = 7; i >= 0; --i) { 4682292SN/A uint8_t ra_ub = Ra.uq<hi:lo>; 4692292SN/A uint8_t rb_ub = Rb.uq<hi:lo>; 4702292SN/A temp = ((temp << 8) 4712292SN/A | ((ra_ub > rb_ub) ? Ra.uq<hi:lo> 4722292SN/A : Rb.uq<hi:lo>)); 4732292SN/A hi -= 8; 4742292SN/A lo -= 8; 4752292SN/A } 4762292SN/A Rc = temp; 4772292SN/A }}); 4782292SN/A 4792292SN/A 0x3d: maxuw4({{ 4802292SN/A uint64_t temp = 0; 4812292SN/A int hi = 63; 4822292SN/A int lo = 48; 4832292SN/A for (int i = 3; i >= 0; --i) { 4842669Sktlim@umich.edu uint16_t ra_uw = Ra.uq<hi:lo>; 4852292SN/A uint16_t rb_uw = Rb.uq<hi:lo>; 4862669Sktlim@umich.edu temp = ((temp << 16) 4872292SN/A | ((ra_uw > rb_uw) ? Ra.uq<hi:lo> 4882669Sktlim@umich.edu : Rb.uq<hi:lo>)); 4892669Sktlim@umich.edu hi -= 16; 4902669Sktlim@umich.edu lo -= 16; 4912292SN/A } 4922292SN/A Rc = temp; 4932292SN/A }}); 4942292SN/A 4952292SN/A 0x3e: maxsb8({{ 4963172Sstever@eecs.umich.edu uint64_t temp = 0; 4972731Sktlim@umich.edu int hi = 63; 4982669Sktlim@umich.edu int lo = 56; 4992727Sktlim@umich.edu for (int i = 7; i >= 0; --i) { 5002292SN/A int8_t ra_sb = Ra.uq<hi:lo>; 5012292SN/A int8_t rb_sb = Rb.uq<hi:lo>; 5022292SN/A temp = ((temp << 8) 5032292SN/A | ((ra_sb > rb_sb) ? Ra.uq<hi:lo> 5042669Sktlim@umich.edu : Rb.uq<hi:lo>)); 5052292SN/A hi -= 8; 5062292SN/A lo -= 8; 5072292SN/A } 5082292SN/A Rc = temp; 5092292SN/A }}); 5102669Sktlim@umich.edu 5112292SN/A 0x3f: maxsw4({{ 5123172Sstever@eecs.umich.edu uint64_t temp = 0; 5133326Sktlim@umich.edu int hi = 63; 5143326Sktlim@umich.edu int lo = 48; 5153326Sktlim@umich.edu for (int i = 3; i >= 0; --i) { 5163326Sktlim@umich.edu int16_t ra_sw = Ra.uq<hi:lo>; 5173326Sktlim@umich.edu int16_t rb_sw = Rb.uq<hi:lo>; 5183326Sktlim@umich.edu temp = ((temp << 16) 5192292SN/A | ((ra_sw > rb_sw) ? Ra.uq<hi:lo> 5202292SN/A : Rb.uq<hi:lo>)); 5212292SN/A hi -= 16; 5222292SN/A lo -= 16; 5232292SN/A } 5242292SN/A Rc = temp; 5252292SN/A }}); 5262292SN/A 5272292SN/A format BasicOperateWithNopCheck { 5282292SN/A 0x70: decode RB { 5292292SN/A 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp); 5302292SN/A } 5312292SN/A 0x78: decode RB { 5322292SN/A 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }}, 5332292SN/A FloatCvtOp); 5342292SN/A } 5352292SN/A } 5362292SN/A } 5372292SN/A } 5382292SN/A 5392292SN/A // Conditional branches. 5402292SN/A format CondBranch { 5412669Sktlim@umich.edu 0x39: beq({{ cond = (Ra == 0); }}); 5422292SN/A 0x3d: bne({{ cond = (Ra != 0); }}); 5432669Sktlim@umich.edu 0x3e: bge({{ cond = (Ra.sq >= 0); }}); 5442669Sktlim@umich.edu 0x3f: bgt({{ cond = (Ra.sq > 0); }}); 5452292SN/A 0x3b: ble({{ cond = (Ra.sq <= 0); }}); 5462669Sktlim@umich.edu 0x3a: blt({{ cond = (Ra.sq < 0); }}); 5472292SN/A 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 5482292SN/A 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 5492669Sktlim@umich.edu 5502669Sktlim@umich.edu 0x31: fbeq({{ cond = (Fa == 0); }}); 5512292SN/A 0x35: fbne({{ cond = (Fa != 0); }}); 5522292SN/A 0x36: fbge({{ cond = (Fa >= 0); }}); 5532292SN/A 0x37: fbgt({{ cond = (Fa > 0); }}); 5542329SN/A 0x33: fble({{ cond = (Fa <= 0); }}); 5552669Sktlim@umich.edu 0x32: fblt({{ cond = (Fa < 0); }}); 5562329SN/A } 5572292SN/A 5582292SN/A // unconditional branches 5592292SN/A format UncondBranch { 5602292SN/A 0x30: br(); 5612292SN/A 0x34: bsr(IsCall); 5623803Sgblack@eecs.umich.edu } 5633803Sgblack@eecs.umich.edu 5643803Sgblack@eecs.umich.edu // indirect branches 5653803Sgblack@eecs.umich.edu 0x1a: decode JMPFUNC { 5663803Sgblack@eecs.umich.edu format Jump { 5673803Sgblack@eecs.umich.edu 0: jmp(); 5682669Sktlim@umich.edu 1: jsr(IsCall); 5692669Sktlim@umich.edu 2: ret(IsReturn); 5702292SN/A 3: jsr_coroutine(IsCall, IsReturn); 5712669Sktlim@umich.edu } 5722292SN/A } 5732292SN/A 5742292SN/A // Square root and integer-to-FP moves 5752693Sktlim@umich.edu 0x14: decode FP_SHORTFUNC { 5762678Sktlim@umich.edu // Integer to FP register moves must have RB == 31 5774022Sstever@eecs.umich.edu 0x4: decode RB { 5784022Sstever@eecs.umich.edu 31: decode FP_FULLFUNC { 5792678Sktlim@umich.edu format BasicOperateWithNopCheck { 5802678Sktlim@umich.edu 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 5812678Sktlim@umich.edu 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 5822292SN/A 0x014: FailUnimpl::itoff(); // VAX-format conversion 5832292SN/A } 5842292SN/A } 5852292SN/A } 5862292SN/A 5872678Sktlim@umich.edu // Square root instructions must have FA == 31 5882727Sktlim@umich.edu 0xb: decode FA { 5892292SN/A 31: decode FP_TYPEFUNC { 5902292SN/A format FloatingPointOperate { 5912292SN/A#if SS_COMPATIBLE_FP 5922292SN/A 0x0b: sqrts({{ 5932292SN/A if (Fb < 0.0) 5942292SN/A fault = new ArithmeticFault; 5952292SN/A Fc = sqrt(Fb); 5962292SN/A }}, FloatSqrtOp); 5972292SN/A#else 5982292SN/A 0x0b: sqrts({{ 5992292SN/A if (Fb.sf < 0.0) 6002292SN/A fault = new ArithmeticFault; 6012292SN/A Fc.sf = sqrt(Fb.sf); 6022292SN/A }}, FloatSqrtOp); 6032292SN/A#endif 6042292SN/A 0x2b: sqrtt({{ 6052292SN/A if (Fb < 0.0) 6062669Sktlim@umich.edu fault = new ArithmeticFault; 6072292SN/A Fc = sqrt(Fb); 6082292SN/A }}, FloatSqrtOp); 6092292SN/A } 6102292SN/A } 6112292SN/A } 6122292SN/A 6132292SN/A // VAX-format sqrtf and sqrtg are not implemented 6142292SN/A 0xa: FailUnimpl::sqrtfg(); 6152669Sktlim@umich.edu } 6162927Sktlim@umich.edu 6172727Sktlim@umich.edu // IEEE floating point 6182292SN/A 0x16: decode FP_SHORTFUNC_TOP2 { 6192292SN/A // The top two bits of the short function code break this 6202292SN/A // space into four groups: binary ops, compares, reserved, and 6212292SN/A // conversions. See Table 4-12 of AHB. There are different 6222292SN/A // special cases in these different groups, so we decode on 6232669Sktlim@umich.edu // these top two bits first just to select a decode strategy. 6242292SN/A // Most of these instructions may have various trapping and 6252727Sktlim@umich.edu // rounding mode flags set; these are decoded in the 6262292SN/A // FloatingPointDecode template used by the 6272292SN/A // FloatingPointOperate format. 6282292SN/A 6292292SN/A // add/sub/mul/div: just decode on the short function code 6302292SN/A // and source type. All valid trapping and rounding modes apply. 6312907Sktlim@umich.edu 0: decode FP_TRAPMODE { 6322669Sktlim@umich.edu // check for valid trapping modes here 6332292SN/A 0,1,5,7: decode FP_TYPEFUNC { 6342669Sktlim@umich.edu format FloatingPointOperate { 6352669Sktlim@umich.edu#if SS_COMPATIBLE_FP 6362292SN/A 0x00: adds({{ Fc = Fa + Fb; }}); 6372292SN/A 0x01: subs({{ Fc = Fa - Fb; }}); 6382292SN/A 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 6392907Sktlim@umich.edu 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 6402907Sktlim@umich.edu#else 6413228Sktlim@umich.edu 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }}); 6424022Sstever@eecs.umich.edu 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }}); 6433228Sktlim@umich.edu 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); 6443228Sktlim@umich.edu 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp); 6453228Sktlim@umich.edu#endif 6463228Sktlim@umich.edu 6473228Sktlim@umich.edu 0x20: addt({{ Fc = Fa + Fb; }}); 6483228Sktlim@umich.edu 0x21: subt({{ Fc = Fa - Fb; }}); 6493228Sktlim@umich.edu 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 6503228Sktlim@umich.edu 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 6512907Sktlim@umich.edu } 6523228Sktlim@umich.edu } 6533228Sktlim@umich.edu } 6543228Sktlim@umich.edu 6553228Sktlim@umich.edu // Floating-point compare instructions must have the default 6563228Sktlim@umich.edu // rounding mode, and may use the default trapping mode or 6573228Sktlim@umich.edu // /SU. Both trapping modes are treated the same by M5; the 6583228Sktlim@umich.edu // only difference on the real hardware (as far a I can tell) 6593228Sktlim@umich.edu // is that without /SU you'd get an imprecise trap if you 6603221Sktlim@umich.edu // tried to compare a NaN with something else (instead of an 6613221Sktlim@umich.edu // "unordered" result). 6623221Sktlim@umich.edu 1: decode FP_FULLFUNC { 6632907Sktlim@umich.edu format BasicOperateWithNopCheck { 6642907Sktlim@umich.edu 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 6652907Sktlim@umich.edu FloatCmpOp); 6662907Sktlim@umich.edu 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 6672907Sktlim@umich.edu FloatCmpOp); 6682907Sktlim@umich.edu 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 6692907Sktlim@umich.edu FloatCmpOp); 6702907Sktlim@umich.edu 0x0a4, 0x5a4: cmptun({{ // unordered 6712907Sktlim@umich.edu Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 6722727Sktlim@umich.edu }}, FloatCmpOp); 6733014Srdreslin@umich.edu } 6743014Srdreslin@umich.edu } 6752669Sktlim@umich.edu 6762669Sktlim@umich.edu // The FP-to-integer and integer-to-FP conversion insts 6772669Sktlim@umich.edu // require that FA be 31. 6782292SN/A 3: decode FA { 6792669Sktlim@umich.edu 31: decode FP_TYPEFUNC { 6802669Sktlim@umich.edu format FloatingPointOperate { 6812669Sktlim@umich.edu 0x2f: decode FP_ROUNDMODE { 6822669Sktlim@umich.edu format FPFixedRounding { 6832669Sktlim@umich.edu // "chopped" i.e. round toward zero 6842669Sktlim@umich.edu 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }}, 6852669Sktlim@umich.edu Chopped); 6862669Sktlim@umich.edu // round to minus infinity 6872292SN/A 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }}, 6882292SN/A MinusInfinity); 6892669Sktlim@umich.edu } 6902292SN/A default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }}); 6912292SN/A } 6922292SN/A 6932292SN/A // The cvtts opcode is overloaded to be cvtst if the trap 6942292SN/A // mode is 2 or 6 (which are not valid otherwise) 6952669Sktlim@umich.edu 0x2c: decode FP_FULLFUNC { 6962292SN/A format BasicOperateWithNopCheck { 6972292SN/A // trap on denorm version "cvtst/s" is 6982292SN/A // simulated same as cvtst 6992292SN/A 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }}); 7002292SN/A } 7012669Sktlim@umich.edu default: cvtts({{ Fc.sf = Fb; }}); 7022292SN/A } 7032329SN/A 7042292SN/A // The trapping mode for integer-to-FP conversions 7052292SN/A // must be /SUI or nothing; /U and /SU are not 7062292SN/A // allowed. The full set of rounding modes are 7072329SN/A // supported though. 7082292SN/A 0x3c: decode FP_TRAPMODE { 7092292SN/A 0,7: cvtqs({{ Fc.sf = Fb.sq; }}); 7102292SN/A } 7112292SN/A 0x3e: decode FP_TRAPMODE { 7122292SN/A 0,7: cvtqt({{ Fc = Fb.sq; }}); 7132292SN/A } 714 } 715 } 716 } 717 } 718 719 // misc FP operate 720 0x17: decode FP_FULLFUNC { 721 format BasicOperateWithNopCheck { 722 0x010: cvtlq({{ 723 Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>; 724 }}); 725 0x030: cvtql({{ 726 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 727 }}); 728 729 // We treat the precise & imprecise trapping versions of 730 // cvtql identically. 731 0x130, 0x530: cvtqlv({{ 732 // To avoid overflow, all the upper 32 bits must match 733 // the sign bit of the lower 32. We code this as 734 // checking the upper 33 bits for all 0s or all 1s. 735 uint64_t sign_bits = Fb.uq<63:31>; 736 if (sign_bits != 0 && sign_bits != mask(33)) 737 fault = new IntegerOverflowFault; 738 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 739 }}); 740 741 0x020: cpys({{ // copy sign 742 Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>; 743 }}); 744 0x021: cpysn({{ // copy sign negated 745 Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>; 746 }}); 747 0x022: cpyse({{ // copy sign and exponent 748 Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>; 749 }}); 750 751 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 752 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 753 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 754 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 755 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 756 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 757 758 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess); 759 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess); 760 } 761 } 762 763 // miscellaneous mem-format ops 764 0x18: decode MEMFUNC { 765 format WarnUnimpl { 766 0x8000: fetch(); 767 0xa000: fetch_m(); 768 0xe800: ecb(); 769 } 770 771 format MiscPrefetch { 772 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 773 {{ ; }}, 774 mem_flags = PREFETCH); 775 } 776 777 format BasicOperate { 778 0xc000: rpcc({{ 779 /* Rb is a fake dependency so here is a fun way to get 780 * the parser to understand that. 781 */ 782 uint64_t unused_var M5_VAR_USED = Rb; 783 Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick(); 784 }}, IsUnverifiable); 785 786 // All of the barrier instructions below do nothing in 787 // their execute() methods (hence the empty code blocks). 788 // All of their functionality is hard-coded in the 789 // pipeline based on the flags IsSerializing, 790 // IsMemBarrier, and IsWriteBarrier. In the current 791 // detailed CPU model, the execute() function only gets 792 // called at fetch, so there's no way to generate pipeline 793 // behavior at any other stage. Once we go to an 794 // exec-in-exec CPU model we should be able to get rid of 795 // these flags and implement this behavior via the 796 // execute() methods. 797 798 // trapb is just a barrier on integer traps, where excb is 799 // a barrier on integer and FP traps. "EXCB is thus a 800 // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 801 // them the same though. 802 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 803 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 804 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 805 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 806 } 807 808 0xe000: decode FULL_SYSTEM { 809 0: FailUnimpl::rc_se(); 810 default: BasicOperate::rc({{ 811 Ra = IntrFlag; 812 IntrFlag = 0; 813 }}, IsNonSpeculative, IsUnverifiable); 814 } 815 0xf000: decode FULL_SYSTEM { 816 0: FailUnimpl::rs_se(); 817 default: BasicOperate::rs({{ 818 Ra = IntrFlag; 819 IntrFlag = 1; 820 }}, IsNonSpeculative, IsUnverifiable); 821 } 822 } 823 824#if FULL_SYSTEM 825 0x00: CallPal::call_pal({{ 826 if (!palValid || 827 (palPriv 828 && xc->readMiscReg(IPR_ICM) != mode_kernel)) { 829 // invalid pal function code, or attempt to do privileged 830 // PAL call in non-kernel mode 831 fault = new UnimplementedOpcodeFault; 832 } else { 833 // check to see if simulator wants to do something special 834 // on this PAL call (including maybe suppress it) 835 bool dopal = xc->simPalCheck(palFunc); 836 837 if (dopal) { 838 xc->setMiscReg(IPR_EXC_ADDR, NPC); 839 NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset; 840 } 841 } 842 }}, IsNonSpeculative); 843#else 844 0x00: decode PALFUNC { 845 format EmulatedCallPal { 846 0x00: halt ({{ 847 exitSimLoop("halt instruction encountered"); 848 }}, IsNonSpeculative); 849 0x83: callsys({{ 850 xc->syscall(R0); 851 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 852 // Read uniq reg into ABI return value register (r0) 853 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); 854 // Write uniq reg with value from ABI arg register (r16) 855 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess); 856 } 857 } 858#endif 859 860#if FULL_SYSTEM 861 0x1b: decode PALMODE { 862 0: OpcdecFault::hw_st_quad(); 863 1: decode HW_LDST_QUAD { 864 format HwLoad { 865 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, 866 L, IsSerializing, IsSerializeBefore); 867 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, 868 Q, IsSerializing, IsSerializeBefore); 869 } 870 } 871 } 872 873 0x1f: decode PALMODE { 874 0: OpcdecFault::hw_st_cond(); 875 format HwStore { 876 1: decode HW_LDST_COND { 877 0: decode HW_LDST_QUAD { 878 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 879 {{ Mem.ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore); 880 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 881 {{ Mem.uq = Ra.uq; }}, Q, IsSerializing, IsSerializeBefore); 882 } 883 884 1: FailUnimpl::hw_st_cond(); 885 } 886 } 887 } 888 889 0x19: decode PALMODE { 890 0: OpcdecFault::hw_mfpr(); 891 format HwMoveIPR { 892 1: hw_mfpr({{ 893 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 894 IprToMiscRegIndex[ipr_index] : -1; 895 if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || 896 miscRegIndex >= NumInternalProcRegs) 897 fault = new UnimplementedOpcodeFault; 898 else 899 Ra = xc->readMiscReg(miscRegIndex); 900 }}, IsIprAccess); 901 } 902 } 903 904 0x1d: decode PALMODE { 905 0: OpcdecFault::hw_mtpr(); 906 format HwMoveIPR { 907 1: hw_mtpr({{ 908 int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? 909 IprToMiscRegIndex[ipr_index] : -1; 910 if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) || 911 miscRegIndex >= NumInternalProcRegs) 912 fault = new UnimplementedOpcodeFault; 913 else 914 xc->setMiscReg(miscRegIndex, Ra); 915 if (traceData) { traceData->setData(Ra); } 916 }}, IsIprAccess); 917 } 918 } 919 920 0x1e: decode PALMODE { 921 0: OpcdecFault::hw_rei(); 922 format BasicOperate { 923 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); 924 } 925 } 926 927#endif 928 929 format BasicOperate { 930 // M5 special opcodes use the reserved 0x01 opcode space 931 0x01: decode M5FUNC { 932 0x00: arm({{ 933 PseudoInst::arm(xc->tcBase()); 934 }}, IsNonSpeculative); 935 0x01: quiesce({{ 936 PseudoInst::quiesce(xc->tcBase()); 937 }}, IsNonSpeculative, IsQuiesce); 938 0x02: quiesceNs({{ 939 PseudoInst::quiesceNs(xc->tcBase(), R16); 940 }}, IsNonSpeculative, IsQuiesce); 941 0x03: quiesceCycles({{ 942 PseudoInst::quiesceCycles(xc->tcBase(), R16); 943 }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 944 0x04: quiesceTime({{ 945 R0 = PseudoInst::quiesceTime(xc->tcBase()); 946 }}, IsNonSpeculative, IsUnverifiable); 947 0x07: rpns({{ 948 R0 = PseudoInst::rpns(xc->tcBase()); 949 }}, IsNonSpeculative, IsUnverifiable); 950 0x09: wakeCPU({{ 951 PseudoInst::wakeCPU(xc->tcBase(), R16); 952 }}, IsNonSpeculative, IsUnverifiable); 953 0x10: deprecated_ivlb({{ 954 warn_once("Obsolete M5 ivlb instruction encountered.\n"); 955 }}); 956 0x11: deprecated_ivle({{ 957 warn_once("Obsolete M5 ivlb instruction encountered.\n"); 958 }}); 959 0x20: deprecated_exit ({{ 960 warn_once("deprecated M5 exit instruction encountered.\n"); 961 PseudoInst::m5exit(xc->tcBase(), 0); 962 }}, No_OpClass, IsNonSpeculative); 963 0x21: m5exit({{ 964 PseudoInst::m5exit(xc->tcBase(), R16); 965 }}, No_OpClass, IsNonSpeculative); 966 0x31: loadsymbol({{ 967 PseudoInst::loadsymbol(xc->tcBase()); 968 }}, No_OpClass, IsNonSpeculative); 969 0x30: initparam({{ 970 Ra = PseudoInst::initParam(xc->tcBase()); 971 }}); 972 0x40: resetstats({{ 973 PseudoInst::resetstats(xc->tcBase(), R16, R17); 974 }}, IsNonSpeculative); 975 0x41: dumpstats({{ 976 PseudoInst::dumpstats(xc->tcBase(), R16, R17); 977 }}, IsNonSpeculative); 978 0x42: dumpresetstats({{ 979 PseudoInst::dumpresetstats(xc->tcBase(), R16, R17); 980 }}, IsNonSpeculative); 981 0x43: m5checkpoint({{ 982 PseudoInst::m5checkpoint(xc->tcBase(), R16, R17); 983 }}, IsNonSpeculative); 984 0x50: m5readfile({{ 985 R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18); 986 }}, IsNonSpeculative); 987 0x51: m5break({{ 988 PseudoInst::debugbreak(xc->tcBase()); 989 }}, IsNonSpeculative); 990 0x52: m5switchcpu({{ 991 PseudoInst::switchcpu(xc->tcBase()); 992 }}, IsNonSpeculative); 993 0x53: m5addsymbol({{ 994 PseudoInst::addsymbol(xc->tcBase(), R16, R17); 995 }}, IsNonSpeculative); 996 0x54: m5panic({{ 997 panic("M5 panic instruction called at pc = %#x.", PC); 998 }}, IsNonSpeculative); 999#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase()) 1000 0x55: decode RA { 1001 0x00: m5a_old({{ 1002 panic("Deprecated M5 annotate instruction executed " 1003 "at pc = %#x\n", PC); 1004 }}, IsNonSpeculative); 1005 0x01: m5a_bsm({{ 1006 CPANN(swSmBegin); 1007 }}, IsNonSpeculative); 1008 0x02: m5a_esm({{ 1009 CPANN(swSmEnd); 1010 }}, IsNonSpeculative); 1011 0x03: m5a_begin({{ 1012 CPANN(swExplictBegin); 1013 }}, IsNonSpeculative); 1014 0x04: m5a_end({{ 1015 CPANN(swEnd); 1016 }}, IsNonSpeculative); 1017 0x06: m5a_q({{ 1018 CPANN(swQ); 1019 }}, IsNonSpeculative); 1020 0x07: m5a_dq({{ 1021 CPANN(swDq); 1022 }}, IsNonSpeculative); 1023 0x08: m5a_wf({{ 1024 CPANN(swWf); 1025 }}, IsNonSpeculative); 1026 0x09: m5a_we({{ 1027 CPANN(swWe); 1028 }}, IsNonSpeculative); 1029 0x0C: m5a_sq({{ 1030 CPANN(swSq); 1031 }}, IsNonSpeculative); 1032 0x0D: m5a_aq({{ 1033 CPANN(swAq); 1034 }}, IsNonSpeculative); 1035 0x0E: m5a_pq({{ 1036 CPANN(swPq); 1037 }}, IsNonSpeculative); 1038 0x0F: m5a_l({{ 1039 CPANN(swLink); 1040 }}, IsNonSpeculative); 1041 0x10: m5a_identify({{ 1042 CPANN(swIdentify); 1043 }}, IsNonSpeculative); 1044 0x11: m5a_getid({{ 1045 R0 = CPANN(swGetId); 1046 }}, IsNonSpeculative); 1047 0x13: m5a_scl({{ 1048 CPANN(swSyscallLink); 1049 }}, IsNonSpeculative); 1050 0x14: m5a_rq({{ 1051 CPANN(swRq); 1052 }}, IsNonSpeculative); 1053 } // M5 Annotate Operations 1054#undef CPANN 1055 0x56: m5reserved2({{ 1056 warn("M5 reserved opcode ignored"); 1057 }}, IsNonSpeculative); 1058 0x57: m5reserved3({{ 1059 warn("M5 reserved opcode ignored"); 1060 }}, IsNonSpeculative); 1061 0x58: m5reserved4({{ 1062 warn("M5 reserved opcode ignored"); 1063 }}, IsNonSpeculative); 1064 0x59: m5reserved5({{ 1065 warn("M5 reserved opcode ignored"); 1066 }}, IsNonSpeculative); 1067 } 1068 } 1069} 1070