decoder.isa revision 3144
11689SN/A// -*- mode:c++ -*-
210333Smitch.hayenga@arm.com
37782Sminkyu.jeong@arm.com// Copyright (c) 2003-2006 The Regents of The University of Michigan
47782Sminkyu.jeong@arm.com// All rights reserved.
57782Sminkyu.jeong@arm.com//
67782Sminkyu.jeong@arm.com// Redistribution and use in source and binary forms, with or without
77782Sminkyu.jeong@arm.com// modification, are permitted provided that the following conditions are
87782Sminkyu.jeong@arm.com// met: redistributions of source code must retain the above copyright
97782Sminkyu.jeong@arm.com// notice, this list of conditions and the following disclaimer;
107782Sminkyu.jeong@arm.com// redistributions in binary form must reproduce the above copyright
117782Sminkyu.jeong@arm.com// notice, this list of conditions and the following disclaimer in the
127782Sminkyu.jeong@arm.com// documentation and/or other materials provided with the distribution;
137782Sminkyu.jeong@arm.com// neither the name of the copyright holders nor the names of its
142326SN/A// contributors may be used to endorse or promote products derived from
151689SN/A// this software without specific prior written permission.
161689SN/A//
171689SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
181689SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
191689SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
201689SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
211689SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
221689SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
231689SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
241689SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
251689SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
261689SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
271689SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
281689SN/A//
291689SN/A// Authors: Steve Reinhardt
301689SN/A
311689SN/A////////////////////////////////////////////////////////////////////
321689SN/A//
331689SN/A// The actual decoder specification
341689SN/A//
351689SN/A
361689SN/Adecode OPCODE default Unknown::unknown() {
371689SN/A
381689SN/A    format LoadAddress {
392665Ssaidi@eecs.umich.edu        0x08: lda({{ Ra = Rb + disp; }});
402665Ssaidi@eecs.umich.edu        0x09: ldah({{ Ra = Rb + (disp << 16); }});
411689SN/A    }
421689SN/A
432292SN/A    format LoadOrNop {
442292SN/A        0x0a: ldbu({{ Ra.uq = Mem.ub; }});
451060SN/A        0x0c: ldwu({{ Ra.uq = Mem.uw; }});
461060SN/A        0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
478230Snate@binkert.org        0x23: ldt({{ Fa = Mem.df; }});
481060SN/A        0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
491461SN/A        0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
501717SN/A#ifdef USE_COPY
518229Snate@binkert.org        0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
522292SN/A                                      {{ fault = xc->copySrcTranslate(EA); }},
538229Snate@binkert.org                                      inst_flags = [IsMemRef, IsLoad, IsCopy]);
548232Snate@binkert.org#endif
5510023Smatt.horsnell@ARM.com    }
561060SN/A
578737Skoansin.tan@gmail.com    format LoadOrPrefetch {
582292SN/A        0x28: ldl({{ Ra.sl = Mem.sl; }});
592292SN/A        0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT);
602292SN/A        // IsFloating flag on lds gets the prefetch to disassemble
612326SN/A        // using f31 instead of r31... funcitonally it's unnecessary
622326SN/A        0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }},
632326SN/A                  pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
642326SN/A    }
652326SN/A
662292SN/A    format Store {
672326SN/A        0x0e: stb({{ Mem.ub = Ra<7:0>; }});
682326SN/A        0x0d: stw({{ Mem.uw = Ra<15:0>; }});
692326SN/A        0x2c: stl({{ Mem.ul = Ra<31:0>; }});
702326SN/A        0x2d: stq({{ Mem.uq = Ra.uq; }});
712326SN/A        0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }});
722326SN/A        0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }});
732326SN/A        0x27: stt({{ Mem.df = Fa; }});
742326SN/A#ifdef USE_COPY
752326SN/A        0x24: MiscPrefetch::copy_store({{ EA = Rb; }},
762326SN/A                                       {{ fault = xc->copy(EA); }},
772326SN/A                                       inst_flags = [IsMemRef, IsStore, IsCopy]);
782292SN/A#endif
791681SN/A    }
802292SN/A
811060SN/A    format StoreCond {
821060SN/A        0x2e: stl_c({{ Mem.ul = Ra<31:0>; }},
831060SN/A                    {{
841061SN/A                        uint64_t tmp = write_result;
851061SN/A                        // see stq_c
862733Sktlim@umich.edu                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
871060SN/A                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
881681SN/A        0x2f: stq_c({{ Mem.uq = Ra; }},
891061SN/A                    {{
902292SN/A                        uint64_t tmp = write_result;
911060SN/A                        // If the write operation returns 0 or 1, then
921061SN/A                        // this was a conventional store conditional,
931061SN/A                        // and the value indicates the success/failure
941061SN/A                        // of the operation.  If another value is
951061SN/A                        // returned, then this was a Turbolaser
961060SN/A                        // mailbox access, and we don't update the
971060SN/A                        // result register at all.
982292SN/A                        Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
992292SN/A                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
1002292SN/A    }
1011060SN/A
1022292SN/A    format IntegerOperate {
1032292SN/A
1042292SN/A        0x10: decode INTFUNC {	// integer arithmetic operations
1052292SN/A
1062292SN/A            0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }});
1072292SN/A            0x40: addlv({{
1081060SN/A                uint32_t tmp  = Ra.sl + Rb_or_imm.sl;
1091060SN/A                // signed overflow occurs when operands have same sign
1101060SN/A                // and sign of result does not match.
1112292SN/A                if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1121060SN/A                    fault = new IntegerOverflowFault;
1131060SN/A                Rc.sl = tmp;
1141060SN/A            }});
1151060SN/A            0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
1161060SN/A            0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }});
1172292SN/A
1181060SN/A            0x20: addq({{ Rc = Ra + Rb_or_imm; }});
1192292SN/A            0x60: addqv({{
1202292SN/A                uint64_t tmp = Ra + Rb_or_imm;
1212292SN/A                // signed overflow occurs when operands have same sign
1222292SN/A                // and sign of result does not match.
1232292SN/A                if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1242292SN/A                    fault = new IntegerOverflowFault;
1251060SN/A                Rc = tmp;
12610023Smatt.horsnell@ARM.com            }});
12710023Smatt.horsnell@ARM.com            0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
12810023Smatt.horsnell@ARM.com            0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
12911246Sradhika.jagtap@ARM.com
13011246Sradhika.jagtap@ARM.com            0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }});
13111246Sradhika.jagtap@ARM.com            0x49: sublv({{
13211246Sradhika.jagtap@ARM.com                uint32_t tmp  = Ra.sl - Rb_or_imm.sl;
13310023Smatt.horsnell@ARM.com                // signed overflow detection is same as for add,
1341060SN/A                // except we need to look at the *complemented*
1352292SN/A                // sign bit of the subtrahend (Rb), i.e., if the initial
1365529Snate@binkert.org                // signs are the *same* then no overflow can occur
1371060SN/A                if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
1382292SN/A                    fault = new IntegerOverflowFault;
1392292SN/A                Rc.sl = tmp;
1401062SN/A            }});
1412292SN/A            0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
1422632Sstever@eecs.umich.edu            0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }});
1432632Sstever@eecs.umich.edu
14410023Smatt.horsnell@ARM.com            0x29: subq({{ Rc = Ra - Rb_or_imm; }});
14510023Smatt.horsnell@ARM.com            0x69: subqv({{
14610023Smatt.horsnell@ARM.com                uint64_t tmp  = Ra - Rb_or_imm;
1472292SN/A                // signed overflow detection is same as for add,
1489427SAndreas.Sandberg@ARM.com                // except we need to look at the *complemented*
1492292SN/A                // sign bit of the subtrahend (Rb), i.e., if the initial
1502292SN/A                // signs are the *same* then no overflow can occur
1512632Sstever@eecs.umich.edu                if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
1522632Sstever@eecs.umich.edu                    fault = new IntegerOverflowFault;
1532292SN/A                Rc = tmp;
1542632Sstever@eecs.umich.edu            }});
1552632Sstever@eecs.umich.edu            0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
1562292SN/A            0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
1572632Sstever@eecs.umich.edu
1582632Sstever@eecs.umich.edu            0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
1592292SN/A            0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }});
1606221Snate@binkert.org            0x4d: cmplt({{ Rc = (Ra.sq <  Rb_or_imm.sq); }});
1612632Sstever@eecs.umich.edu            0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }});
1622292SN/A            0x1d: cmpult({{ Rc = (Ra.uq <  Rb_or_imm.uq); }});
1632292SN/A
1642632Sstever@eecs.umich.edu            0x0f: cmpbge({{
1659444SAndreas.Sandberg@ARM.com                int hi = 7;
1669444SAndreas.Sandberg@ARM.com                int lo = 0;
1672843Sktlim@umich.edu                uint64_t tmp = 0;
1689444SAndreas.Sandberg@ARM.com                for (int i = 0; i < 8; ++i) {
1699444SAndreas.Sandberg@ARM.com                    tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i;
1702632Sstever@eecs.umich.edu                    hi += 8;
1712348SN/A                    lo += 8;
1722307SN/A                }
1732632Sstever@eecs.umich.edu                Rc = tmp;
1742292SN/A            }});
1756221Snate@binkert.org        }
1762107SN/A
1772292SN/A        0x11: decode INTFUNC {	// integer logical operations
1782632Sstever@eecs.umich.edu
1792632Sstever@eecs.umich.edu            0x00: and({{ Rc = Ra & Rb_or_imm; }});
1802292SN/A            0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
1812292SN/A            0x20: bis({{ Rc = Ra | Rb_or_imm; }});
1822292SN/A            0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
1832292SN/A            0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
1842292SN/A            0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
1852292SN/A
1862292SN/A            // conditional moves
1872292SN/A            0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
18810333Smitch.hayenga@arm.com            0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
18910333Smitch.hayenga@arm.com            0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
19010333Smitch.hayenga@arm.com            0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
19110333Smitch.hayenga@arm.com            0x44: cmovlt({{ Rc = (Ra.sq <  0) ? Rb_or_imm : Rc; }});
19210333Smitch.hayenga@arm.com            0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }});
19310333Smitch.hayenga@arm.com            0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }});
1942292SN/A            0x66: cmovgt({{ Rc = (Ra.sq >  0) ? Rb_or_imm : Rc; }});
1952632Sstever@eecs.umich.edu
1962632Sstever@eecs.umich.edu            // For AMASK, RA must be R31.
1972292SN/A            0x61: decode RA {
1986221Snate@binkert.org                31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
1992292SN/A            }
2002292SN/A
2012292SN/A            // For IMPLVER, RA must be R31 and the B operand
2022292SN/A            // must be the immediate value 1.
2032292SN/A            0x6c: decode RA {
2042292SN/A                31: decode IMM {
2052292SN/A                    1: decode INTIMM {
2062292SN/A                        // return EV5 for FULL_SYSTEM and EV6 otherwise
2072292SN/A                        1: implver({{
2082292SN/A#if FULL_SYSTEM
2092292SN/A                             Rc = 1;
2102292SN/A#else
2112292SN/A                             Rc = 2;
2122292SN/A#endif
2132292SN/A                        }});
2142292SN/A                    }
2152292SN/A                }
2162292SN/A            }
2172292SN/A
2182292SN/A#if FULL_SYSTEM
2192292SN/A            // The mysterious 11.25...
2202292SN/A            0x25: WarnUnimpl::eleven25();
2212292SN/A#endif
2222292SN/A        }
2232292SN/A
2242292SN/A        0x12: decode INTFUNC {
2252292SN/A            0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
2262292SN/A            0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }});
2272292SN/A            0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }});
2282292SN/A
2295557Sktlim@umich.edu            0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
2306221Snate@binkert.org            0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
2315557Sktlim@umich.edu            0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
2327598Sminkyu.jeong@arm.com            0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
2337598Sminkyu.jeong@arm.com
2347598Sminkyu.jeong@arm.com            0x52: mskwh({{
2352632Sstever@eecs.umich.edu                int bv = Rb_or_imm<2:0>;
2362292SN/A                Rc =  bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
2372292SN/A            }});
2382292SN/A            0x62: msklh({{
2396221Snate@binkert.org                int bv = Rb_or_imm<2:0>;
2402632Sstever@eecs.umich.edu                Rc =  bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
2412292SN/A            }});
2422292SN/A            0x72: mskqh({{
2432292SN/A                int bv = Rb_or_imm<2:0>;
2446221Snate@binkert.org                Rc =  bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
2452292SN/A            }});
2462292SN/A
2476221Snate@binkert.org            0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
2482292SN/A            0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
2492292SN/A            0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
2502292SN/A            0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }});
2512292SN/A
2526221Snate@binkert.org            0x5a: extwh({{
2532292SN/A                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
2542292SN/A            0x6a: extlh({{
2556221Snate@binkert.org                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
2562292SN/A            0x7a: extqh({{
2572292SN/A                Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
2586221Snate@binkert.org
2592292SN/A            0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
2602292SN/A            0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
2612292SN/A            0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
2622292SN/A            0x3b: insql({{ Rc = Ra       << (Rb_or_imm<2:0> * 8); }});
2632292SN/A
2642632Sstever@eecs.umich.edu            0x57: inswh({{
2652632Sstever@eecs.umich.edu                int bv = Rb_or_imm<2:0>;
2662292SN/A                Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0;
2672292SN/A            }});
2682292SN/A            0x67: inslh({{
2692292SN/A                int bv = Rb_or_imm<2:0>;
2702292SN/A                Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0;
2712292SN/A            }});
2722292SN/A            0x77: insqh({{
2732292SN/A                int bv = Rb_or_imm<2:0>;
2742292SN/A                Rc = bv ? (Ra.uq       >> (64 - 8 * bv)) : 0;
2752292SN/A            }});
2762292SN/A
2772292SN/A            0x30: zap({{
2782292SN/A                uint64_t zapmask = 0;
2796221Snate@binkert.org                for (int i = 0; i < 8; ++i) {
2802292SN/A                    if (Rb_or_imm<i:>)
2812292SN/A                        zapmask |= (mask(8) << (i * 8));
2826221Snate@binkert.org                }
2832292SN/A                Rc = Ra & ~zapmask;
2842702Sktlim@umich.edu            }});
2856221Snate@binkert.org            0x31: zapnot({{
2862702Sktlim@umich.edu                uint64_t zapmask = 0;
2872292SN/A                for (int i = 0; i < 8; ++i) {
2882292SN/A                    if (!Rb_or_imm<i:>)
2891060SN/A                        zapmask |= (mask(8) << (i * 8));
2901060SN/A                }
2912292SN/A                Rc = Ra & ~zapmask;
2922292SN/A            }});
2932292SN/A        }
2942632Sstever@eecs.umich.edu
2951060SN/A        0x13: decode INTFUNC {	// integer multiplies
2961060SN/A            0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp);
2972348SN/A            0x20: mulq({{ Rc    = Ra    * Rb_or_imm;    }}, IntMultOp);
2982301SN/A            0x30: umulh({{
2991062SN/A                uint64_t hi, lo;
3002292SN/A                mul128(Ra, Rb_or_imm, hi, lo);
3012632Sstever@eecs.umich.edu                Rc = hi;
3021062SN/A            }}, IntMultOp);
3032292SN/A            0x40: mullv({{
3042292SN/A                // 32-bit multiply with trap on overflow
3051060SN/A                int64_t Rax = Ra.sl;	// sign extended version of Ra.sl
3061060SN/A                int64_t Rbx = Rb_or_imm.sl;
3071060SN/A                int64_t tmp = Rax * Rbx;
3081060SN/A                // To avoid overflow, all the upper 32 bits must match
3091060SN/A                // the sign bit of the lower 32.  We code this as
3101060SN/A                // checking the upper 33 bits for all 0s or all 1s.
3111060SN/A                uint64_t sign_bits = tmp<63:31>;
3121060SN/A                if (sign_bits != 0 && sign_bits != mask(33))
3131060SN/A                    fault = new IntegerOverflowFault;
3141060SN/A                Rc.sl = tmp<31:0>;
3151060SN/A            }}, IntMultOp);
3161060SN/A            0x60: mulqv({{
3171060SN/A                // 64-bit multiply with trap on overflow
3181060SN/A                uint64_t hi, lo;
3191060SN/A                mul128(Ra, Rb_or_imm, hi, lo);
3201060SN/A                // all the upper 64 bits must match the sign bit of
3211060SN/A                // the lower 64
3221060SN/A                if (!((hi == 0 && lo<63:> == 0) ||
3231060SN/A                      (hi == mask(64) && lo<63:> == 1)))
3241060SN/A                    fault = new IntegerOverflowFault;
3251060SN/A                Rc = lo;
3261060SN/A            }}, IntMultOp);
3271060SN/A        }
3281060SN/A
3291060SN/A        0x1c: decode INTFUNC {
3301060SN/A            0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
3311060SN/A            0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
3321060SN/A            0x32: ctlz({{
3332292SN/A                             uint64_t count = 0;
3342292SN/A                             uint64_t temp = Rb;
3352292SN/A                             if (temp<63:32>) temp >>= 32; else count += 32;
3361060SN/A                             if (temp<31:16>) temp >>= 16; else count += 16;
3372292SN/A                             if (temp<15:8>) temp >>= 8; else count += 8;
3381060SN/A                             if (temp<7:4>) temp >>= 4; else count += 4;
3392292SN/A                             if (temp<3:2>) temp >>= 2; else count += 2;
3402292SN/A                             if (temp<1:1>) temp >>= 1; else count += 1;
3412292SN/A                             if ((temp<0:0>) != 0x1) count += 1;
3421681SN/A                             Rc = count;
3432292SN/A                           }}, IntAluOp);
3442733Sktlim@umich.edu
3451060SN/A            0x33: cttz({{
3462292SN/A                             uint64_t count = 0;
3472292SN/A                             uint64_t temp = Rb;
3482292SN/A                             if (!(temp<31:0>)) { temp >>= 32; count += 32; }
3492292SN/A                             if (!(temp<15:0>)) { temp >>= 16; count += 16; }
3502292SN/A                             if (!(temp<7:0>)) { temp >>= 8; count += 8; }
3512292SN/A                             if (!(temp<3:0>)) { temp >>= 4; count += 4; }
3522292SN/A                             if (!(temp<1:0>)) { temp >>= 2; count += 2; }
3532292SN/A                             if (!(temp<0:0> & ULL(0x1))) count += 1;
3542292SN/A                             Rc = count;
3554329Sktlim@umich.edu                           }}, IntAluOp);
3564329Sktlim@umich.edu
3574329Sktlim@umich.edu            format FailUnimpl {
3584329Sktlim@umich.edu                0x30: ctpop();
3594329Sktlim@umich.edu                0x31: perr();
3604329Sktlim@umich.edu                0x34: unpkbw();
3614329Sktlim@umich.edu                0x35: unpkbl();
3624329Sktlim@umich.edu                0x36: pkwb();
3632292SN/A                0x37: pklb();
3642292SN/A                0x38: minsb8();
3652292SN/A                0x39: minsw4();
3662292SN/A                0x3a: minub8();
3672292SN/A                0x3b: minuw4();
3681060SN/A                0x3c: maxub8();
3692292SN/A                0x3d: maxuw4();
3702292SN/A                0x3e: maxsb8();
3712292SN/A                0x3f: maxsw4();
3722292SN/A            }
3732292SN/A
3742292SN/A            format BasicOperateWithNopCheck {
3752292SN/A                0x70: decode RB {
3762292SN/A                    31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp);
3779184Sandreas.hansson@arm.com                }
3789184Sandreas.hansson@arm.com                0x78: decode RB {
3791060SN/A                    31: ftois({{ Rc.sl = t_to_s(Fa.uq); }},
3809184Sandreas.hansson@arm.com                              FloatCvtOp);
3819184Sandreas.hansson@arm.com                }
3821060SN/A            }
3831060SN/A        }
3849184Sandreas.hansson@arm.com    }
3851060SN/A
3861060SN/A    // Conditional branches.
3871060SN/A    format CondBranch {
3889184Sandreas.hansson@arm.com        0x39: beq({{ cond = (Ra == 0); }});
3891060SN/A        0x3d: bne({{ cond = (Ra != 0); }});
3902820Sktlim@umich.edu        0x3e: bge({{ cond = (Ra.sq >= 0); }});
3912820Sktlim@umich.edu        0x3f: bgt({{ cond = (Ra.sq >  0); }});
3921060SN/A        0x3b: ble({{ cond = (Ra.sq <= 0); }});
3931060SN/A        0x3a: blt({{ cond = (Ra.sq < 0); }});
3941060SN/A        0x38: blbc({{ cond = ((Ra & 1) == 0); }});
3951060SN/A        0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
3962292SN/A
3972292SN/A        0x31: fbeq({{ cond = (Fa == 0); }});
3982292SN/A        0x35: fbne({{ cond = (Fa != 0); }});
3992292SN/A        0x36: fbge({{ cond = (Fa >= 0); }});
4002292SN/A        0x37: fbgt({{ cond = (Fa >  0); }});
4012292SN/A        0x33: fble({{ cond = (Fa <= 0); }});
4022292SN/A        0x32: fblt({{ cond = (Fa < 0); }});
4031060SN/A    }
4042292SN/A
4051060SN/A    // unconditional branches
4062820Sktlim@umich.edu    format UncondBranch {
4072820Sktlim@umich.edu        0x30: br();
4082820Sktlim@umich.edu        0x34: bsr(IsCall);
4092292SN/A    }
4106221Snate@binkert.org
4112292SN/A    // indirect branches
4122292SN/A    0x1a: decode JMPFUNC {
4136221Snate@binkert.org        format Jump {
4142292SN/A            0: jmp();
4152292SN/A            1: jsr(IsCall);
4162292SN/A            2: ret(IsReturn);
4172292SN/A            3: jsr_coroutine(IsCall, IsReturn);
4182292SN/A        }
4195999Snate@binkert.org    }
4202292SN/A
4215999Snate@binkert.org    // Square root and integer-to-FP moves
4222292SN/A    0x14: decode FP_SHORTFUNC {
4235999Snate@binkert.org        // Integer to FP register moves must have RB == 31
4242292SN/A        0x4: decode RB {
4255999Snate@binkert.org            31: decode FP_FULLFUNC {
4262292SN/A                format BasicOperateWithNopCheck {
4275999Snate@binkert.org                    0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp);
4282292SN/A                    0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp);
4295999Snate@binkert.org                    0x014: FailUnimpl::itoff();	// VAX-format conversion
4302292SN/A                }
4315999Snate@binkert.org            }
4322292SN/A        }
4335999Snate@binkert.org
4342292SN/A        // Square root instructions must have FA == 31
4355999Snate@binkert.org        0xb: decode FA {
4362292SN/A            31: decode FP_TYPEFUNC {
4375999Snate@binkert.org                format FloatingPointOperate {
4382292SN/A#if SS_COMPATIBLE_FP
4395999Snate@binkert.org                    0x0b: sqrts({{
4402292SN/A                        if (Fb < 0.0)
4415999Snate@binkert.org                            fault = new ArithmeticFault;
4422292SN/A                        Fc = sqrt(Fb);
4435999Snate@binkert.org                    }}, FloatSqrtOp);
4442292SN/A#else
4455999Snate@binkert.org                    0x0b: sqrts({{
4462292SN/A                        if (Fb.sf < 0.0)
4472292SN/A                            fault = new ArithmeticFault;
4482301SN/A                        Fc.sf = sqrt(Fb.sf);
4492727Sktlim@umich.edu                    }}, FloatSqrtOp);
4505999Snate@binkert.org#endif
4512727Sktlim@umich.edu                    0x2b: sqrtt({{
4525999Snate@binkert.org                        if (Fb < 0.0)
4532353SN/A                            fault = new ArithmeticFault;
4545999Snate@binkert.org                        Fc = sqrt(Fb);
4552727Sktlim@umich.edu                    }}, FloatSqrtOp);
4565999Snate@binkert.org                }
4572348SN/A            }
4585999Snate@binkert.org        }
4592348SN/A
4605999Snate@binkert.org        // VAX-format sqrtf and sqrtg are not implemented
4612348SN/A        0xa: FailUnimpl::sqrtfg();
4625999Snate@binkert.org    }
4632348SN/A
4645999Snate@binkert.org    // IEEE floating point
4652348SN/A    0x16: decode FP_SHORTFUNC_TOP2 {
4662301SN/A        // The top two bits of the short function code break this
4672727Sktlim@umich.edu        // space into four groups: binary ops, compares, reserved, and
4682727Sktlim@umich.edu        // conversions.  See Table 4-12 of AHB.  There are different
4692727Sktlim@umich.edu        // special cases in these different groups, so we decode on
4702348SN/A        // these top two bits first just to select a decode strategy.
4715999Snate@binkert.org        // Most of these instructions may have various trapping and
4722348SN/A        // rounding mode flags set; these are decoded in the
4735999Snate@binkert.org        // FloatingPointDecode template used by the
4742348SN/A        // FloatingPointOperate format.
4755999Snate@binkert.org
4762348SN/A        // add/sub/mul/div: just decode on the short function code
4775999Snate@binkert.org        // and source type.  All valid trapping and rounding modes apply.
4782348SN/A        0: decode FP_TRAPMODE {
4792326SN/A            // check for valid trapping modes here
4802348SN/A            0,1,5,7: decode FP_TYPEFUNC {
4812326SN/A                   format FloatingPointOperate {
4821060SN/A#if SS_COMPATIBLE_FP
4831060SN/A                       0x00: adds({{ Fc = Fa + Fb; }});
4842292SN/A                       0x01: subs({{ Fc = Fa - Fb; }});
485                       0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp);
486                       0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp);
487#else
488                       0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }});
489                       0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }});
490                       0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp);
491                       0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp);
492#endif
493
494                       0x20: addt({{ Fc = Fa + Fb; }});
495                       0x21: subt({{ Fc = Fa - Fb; }});
496                       0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
497                       0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
498                   }
499             }
500        }
501
502        // Floating-point compare instructions must have the default
503        // rounding mode, and may use the default trapping mode or
504        // /SU.  Both trapping modes are treated the same by M5; the
505        // only difference on the real hardware (as far a I can tell)
506        // is that without /SU you'd get an imprecise trap if you
507        // tried to compare a NaN with something else (instead of an
508        // "unordered" result).
509        1: decode FP_FULLFUNC {
510            format BasicOperateWithNopCheck {
511                0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
512                                     FloatCmpOp);
513                0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
514                                     FloatCmpOp);
515                0x0a6, 0x5a6: cmptlt({{ Fc = (Fa <  Fb) ? 2.0 : 0.0; }},
516                                     FloatCmpOp);
517                0x0a4, 0x5a4: cmptun({{ // unordered
518                    Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
519                }}, FloatCmpOp);
520            }
521        }
522
523        // The FP-to-integer and integer-to-FP conversion insts
524        // require that FA be 31.
525        3: decode FA {
526            31: decode FP_TYPEFUNC {
527                format FloatingPointOperate {
528                    0x2f: decode FP_ROUNDMODE {
529                        format FPFixedRounding {
530                            // "chopped" i.e. round toward zero
531                            0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }},
532                                     Chopped);
533                            // round to minus infinity
534                            1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }},
535                                     MinusInfinity);
536                        }
537                      default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }});
538                    }
539
540                    // The cvtts opcode is overloaded to be cvtst if the trap
541                    // mode is 2 or 6 (which are not valid otherwise)
542                    0x2c: decode FP_FULLFUNC {
543                        format BasicOperateWithNopCheck {
544                            // trap on denorm version "cvtst/s" is
545                            // simulated same as cvtst
546                            0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }});
547                        }
548                      default: cvtts({{ Fc.sf = Fb; }});
549                    }
550
551                    // The trapping mode for integer-to-FP conversions
552                    // must be /SUI or nothing; /U and /SU are not
553                    // allowed.  The full set of rounding modes are
554                    // supported though.
555                    0x3c: decode FP_TRAPMODE {
556                        0,7: cvtqs({{ Fc.sf = Fb.sq; }});
557                    }
558                    0x3e: decode FP_TRAPMODE {
559                        0,7: cvtqt({{ Fc    = Fb.sq; }});
560                    }
561                }
562            }
563        }
564    }
565
566    // misc FP operate
567    0x17: decode FP_FULLFUNC {
568        format BasicOperateWithNopCheck {
569            0x010: cvtlq({{
570                Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>;
571            }});
572            0x030: cvtql({{
573                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
574            }});
575
576            // We treat the precise & imprecise trapping versions of
577            // cvtql identically.
578            0x130, 0x530: cvtqlv({{
579                // To avoid overflow, all the upper 32 bits must match
580                // the sign bit of the lower 32.  We code this as
581                // checking the upper 33 bits for all 0s or all 1s.
582                uint64_t sign_bits = Fb.uq<63:31>;
583                if (sign_bits != 0 && sign_bits != mask(33))
584                    fault = new IntegerOverflowFault;
585                Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
586            }});
587
588            0x020: cpys({{  // copy sign
589                Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>;
590            }});
591            0x021: cpysn({{ // copy sign negated
592                Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>;
593            }});
594            0x022: cpyse({{ // copy sign and exponent
595                Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>;
596            }});
597
598            0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
599            0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
600            0x02c: fcmovlt({{ Fc = (Fa <  0) ? Fb : Fc; }});
601            0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
602            0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
603            0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
604
605            0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
606            0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
607        }
608    }
609
610    // miscellaneous mem-format ops
611    0x18: decode MEMFUNC {
612        format WarnUnimpl {
613            0x8000: fetch();
614            0xa000: fetch_m();
615            0xe800: ecb();
616        }
617
618        format MiscPrefetch {
619            0xf800: wh64({{ EA = Rb & ~ULL(63); }},
620                         {{ xc->writeHint(EA, 64, memAccessFlags); }},
621                         mem_flags = NO_FAULT,
622                         inst_flags = [IsMemRef, IsDataPrefetch,
623                                       IsStore, MemWriteOp]);
624        }
625
626        format BasicOperate {
627            0xc000: rpcc({{
628#if FULL_SYSTEM
629        /* Rb is a fake dependency so here is a fun way to get
630         * the parser to understand that.
631         */
632                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0);
633
634#else
635                Ra = curTick;
636#endif
637            }}, IsUnverifiable);
638
639            // All of the barrier instructions below do nothing in
640            // their execute() methods (hence the empty code blocks).
641            // All of their functionality is hard-coded in the
642            // pipeline based on the flags IsSerializing,
643            // IsMemBarrier, and IsWriteBarrier.  In the current
644            // detailed CPU model, the execute() function only gets
645            // called at fetch, so there's no way to generate pipeline
646            // behavior at any other stage.  Once we go to an
647            // exec-in-exec CPU model we should be able to get rid of
648            // these flags and implement this behavior via the
649            // execute() methods.
650
651            // trapb is just a barrier on integer traps, where excb is
652            // a barrier on integer and FP traps.  "EXCB is thus a
653            // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
654            // them the same though.
655            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
656            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
657            0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
658            0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
659        }
660
661#if FULL_SYSTEM
662        format BasicOperate {
663            0xe000: rc({{
664                Ra = xc->readIntrFlag();
665                xc->setIntrFlag(0);
666            }}, IsNonSpeculative, IsUnverifiable);
667            0xf000: rs({{
668                Ra = xc->readIntrFlag();
669                xc->setIntrFlag(1);
670            }}, IsNonSpeculative, IsUnverifiable);
671        }
672#else
673        format FailUnimpl {
674            0xe000: rc();
675            0xf000: rs();
676        }
677#endif
678    }
679
680#if FULL_SYSTEM
681    0x00: CallPal::call_pal({{
682        if (!palValid ||
683            (palPriv
684             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
685            // invalid pal function code, or attempt to do privileged
686            // PAL call in non-kernel mode
687            fault = new UnimplementedOpcodeFault;
688        }
689        else {
690            // check to see if simulator wants to do something special
691            // on this PAL call (including maybe suppress it)
692            bool dopal = xc->simPalCheck(palFunc);
693
694            if (dopal) {
695                xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
696                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset;
697            }
698        }
699    }}, IsNonSpeculative);
700#else
701    0x00: decode PALFUNC {
702        format EmulatedCallPal {
703            0x00: halt ({{
704                exitSimLoop("halt instruction encountered");
705            }}, IsNonSpeculative);
706            0x83: callsys({{
707                xc->syscall(R0);
708            }}, IsSerializeAfter, IsNonSpeculative);
709            // Read uniq reg into ABI return value register (r0)
710            0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
711            // Write uniq reg with value from ABI arg register (r16)
712            0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
713        }
714    }
715#endif
716
717#if FULL_SYSTEM
718    0x1b: decode PALMODE {
719        0: OpcdecFault::hw_st_quad();
720        1: decode HW_LDST_QUAD {
721            format HwLoad {
722                0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L);
723                1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q);
724            }
725        }
726    }
727
728    0x1f: decode PALMODE {
729        0: OpcdecFault::hw_st_cond();
730        format HwStore {
731            1: decode HW_LDST_COND {
732                0: decode HW_LDST_QUAD {
733                    0: hw_st({{ EA = (Rb + disp) & ~3; }},
734                {{ Mem.ul = Ra<31:0>; }}, L);
735                    1: hw_st({{ EA = (Rb + disp) & ~7; }},
736                {{ Mem.uq = Ra.uq; }}, Q);
737                }
738
739                1: FailUnimpl::hw_st_cond();
740            }
741        }
742    }
743
744    0x19: decode PALMODE {
745        0: OpcdecFault::hw_mfpr();
746        format HwMoveIPR {
747            1: hw_mfpr({{
748                Ra = xc->readMiscRegWithEffect(ipr_index, fault);
749            }}, IsIprAccess);
750        }
751    }
752
753    0x1d: decode PALMODE {
754        0: OpcdecFault::hw_mtpr();
755        format HwMoveIPR {
756            1: hw_mtpr({{
757                xc->setMiscRegWithEffect(ipr_index, Ra);
758                if (traceData) { traceData->setData(Ra); }
759            }}, IsIprAccess);
760        }
761    }
762
763    format BasicOperate {
764        0x1e: decode PALMODE {
765            0: OpcdecFault::hw_rei();
766            1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
767        }
768
769        // M5 special opcodes use the reserved 0x01 opcode space
770        0x01: decode M5FUNC {
771            0x00: arm({{
772                AlphaPseudo::arm(xc->tcBase());
773            }}, IsNonSpeculative);
774            0x01: quiesce({{
775                AlphaPseudo::quiesce(xc->tcBase());
776            }}, IsNonSpeculative, IsQuiesce);
777            0x02: quiesceNs({{
778                AlphaPseudo::quiesceNs(xc->tcBase(), R16);
779            }}, IsNonSpeculative, IsQuiesce);
780            0x03: quiesceCycles({{
781                AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
782            }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
783            0x04: quiesceTime({{
784                R0 = AlphaPseudo::quiesceTime(xc->tcBase());
785            }}, IsNonSpeculative, IsUnverifiable);
786            0x10: ivlb({{
787                AlphaPseudo::ivlb(xc->tcBase());
788            }}, No_OpClass, IsNonSpeculative);
789            0x11: ivle({{
790                AlphaPseudo::ivle(xc->tcBase());
791            }}, No_OpClass, IsNonSpeculative);
792            0x20: m5exit_old({{
793                AlphaPseudo::m5exit_old(xc->tcBase());
794            }}, No_OpClass, IsNonSpeculative);
795            0x21: m5exit({{
796                AlphaPseudo::m5exit(xc->tcBase(), R16);
797            }}, No_OpClass, IsNonSpeculative);
798            0x31: loadsymbol({{
799                AlphaPseudo::loadsymbol(xc->tcBase());
800            }}, No_OpClass, IsNonSpeculative);
801            0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
802            0x40: resetstats({{
803                AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
804            }}, IsNonSpeculative);
805            0x41: dumpstats({{
806                AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
807            }}, IsNonSpeculative);
808            0x42: dumpresetstats({{
809                AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
810            }}, IsNonSpeculative);
811            0x43: m5checkpoint({{
812                AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
813            }}, IsNonSpeculative);
814            0x50: m5readfile({{
815                R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
816            }}, IsNonSpeculative);
817            0x51: m5break({{
818                AlphaPseudo::debugbreak(xc->tcBase());
819            }}, IsNonSpeculative);
820            0x52: m5switchcpu({{
821                AlphaPseudo::switchcpu(xc->tcBase());
822            }}, IsNonSpeculative);
823            0x53: m5addsymbol({{
824                AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
825            }}, IsNonSpeculative);
826            0x54: m5panic({{
827                panic("M5 panic instruction called at pc=%#x.", xc->readPC());
828            }}, IsNonSpeculative);
829            0x55: m5anBegin({{
830                AlphaPseudo::anBegin(xc->tcBase(), R16);
831            }}, IsNonSpeculative);
832            0x56: m5anWait({{
833                AlphaPseudo::anWait(xc->tcBase(), R16, R17);
834            }}, IsNonSpeculative);
835        }
836    }
837#endif
838}
839