decoder.isa revision 2336
12292SN/A// -*- mode:c++ -*- 212355Snikos.nikoleris@arm.com 39444SAndreas.Sandberg@ARM.com// Copyright (c) 2003-2006 The Regents of The University of Michigan 49444SAndreas.Sandberg@ARM.com// All rights reserved. 59444SAndreas.Sandberg@ARM.com// 69444SAndreas.Sandberg@ARM.com// Redistribution and use in source and binary forms, with or without 79444SAndreas.Sandberg@ARM.com// modification, are permitted provided that the following conditions are 89444SAndreas.Sandberg@ARM.com// met: redistributions of source code must retain the above copyright 99444SAndreas.Sandberg@ARM.com// notice, this list of conditions and the following disclaimer; 109444SAndreas.Sandberg@ARM.com// redistributions in binary form must reproduce the above copyright 119444SAndreas.Sandberg@ARM.com// notice, this list of conditions and the following disclaimer in the 129444SAndreas.Sandberg@ARM.com// documentation and/or other materials provided with the distribution; 139444SAndreas.Sandberg@ARM.com// neither the name of the copyright holders nor the names of its 142329SN/A// contributors may be used to endorse or promote products derived from 1510239Sbinhpham@cs.rutgers.edu// this software without specific prior written permission. 162292SN/A// 172292SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182292SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192292SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202292SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212292SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222292SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232292SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242292SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252292SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262292SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272292SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282292SN/A 292292SN/Adecode OPCODE default Unknown::unknown() { 302292SN/A 312292SN/A format LoadAddress { 322292SN/A 0x08: lda({{ Ra = Rb + disp; }}); 332292SN/A 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 342292SN/A } 352292SN/A 362292SN/A format LoadOrNop { 372292SN/A 0x0a: ldbu({{ Ra.uq = Mem.ub; }}); 382292SN/A 0x0c: ldwu({{ Ra.uq = Mem.uw; }}); 392292SN/A 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 402689Sktlim@umich.edu 0x23: ldt({{ Fa = Mem.df; }}); 412689Sktlim@umich.edu 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED); 422689Sktlim@umich.edu 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED); 432292SN/A 0x20: MiscPrefetch::copy_load({{ EA = Ra; }}, 442292SN/A {{ fault = xc->copySrcTranslate(EA); }}, 452292SN/A inst_flags = [IsMemRef, IsLoad, IsCopy]); 462292SN/A } 472292SN/A 482329SN/A format LoadOrPrefetch { 494395Ssaidi@eecs.umich.edu 0x28: ldl({{ Ra.sl = Mem.sl; }}); 502292SN/A 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT); 512292SN/A // IsFloating flag on lds gets the prefetch to disassemble 522292SN/A // using f31 instead of r31... funcitonally it's unnecessary 538591Sgblack@eecs.umich.edu 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }}, 548506Sgblack@eecs.umich.edu pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 553326Sktlim@umich.edu } 568481Sgblack@eecs.umich.edu 576658Snate@binkert.org format Store { 582292SN/A 0x0e: stb({{ Mem.ub = Ra<7:0>; }}); 598230Snate@binkert.org 0x0d: stw({{ Mem.uw = Ra<15:0>; }}); 608232Snate@binkert.org 0x2c: stl({{ Mem.ul = Ra<31:0>; }}); 613348Sbinkertn@umich.edu 0x2d: stq({{ Mem.uq = Ra.uq; }}); 622669Sktlim@umich.edu 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 632292SN/A 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 648737Skoansin.tan@gmail.com 0x27: stt({{ Mem.df = Fa; }}); 655529Snate@binkert.org 0x24: MiscPrefetch::copy_store({{ EA = Rb; }}, 662292SN/A {{ fault = xc->copy(EA); }}, 672329SN/A inst_flags = [IsMemRef, IsStore, IsCopy]); 682329SN/A } 692329SN/A 702329SN/A format StoreCond { 712329SN/A 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }}, 722329SN/A {{ 732329SN/A uint64_t tmp = write_result; 742329SN/A // see stq_c 752329SN/A Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 762329SN/A }}, mem_flags = LOCKED, inst_flags = IsStoreConditional); 772292SN/A 0x2f: stq_c({{ Mem.uq = Ra; }}, 782292SN/A {{ 792292SN/A uint64_t tmp = write_result; 802292SN/A // If the write operation returns 0 or 1, then 812733Sktlim@umich.edu // this was a conventional store conditional, 822292SN/A // and the value indicates the success/failure 832292SN/A // of the operation. If another value is 842907Sktlim@umich.edu // returned, then this was a Turbolaser 852292SN/A // mailbox access, and we don't update the 862292SN/A // result register at all. 872292SN/A Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 882292SN/A }}, mem_flags = LOCKED, inst_flags = IsStoreConditional); 892292SN/A } 902292SN/A 912292SN/A format IntegerOperate { 925529Snate@binkert.org 935529Snate@binkert.org 0x10: decode INTFUNC { // integer arithmetic operations 945529Snate@binkert.org 952292SN/A 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 962292SN/A 0x40: addlv({{ 972292SN/A uint32_t tmp = Ra.sl + Rb_or_imm.sl; 982292SN/A // signed overflow occurs when operands have same sign 992727Sktlim@umich.edu // and sign of result does not match. 1002727Sktlim@umich.edu if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1012727Sktlim@umich.edu fault = new IntegerOverflowFault; 1022907Sktlim@umich.edu Rc.sl = tmp; 1038922Swilliam.wang@arm.com }}); 1042907Sktlim@umich.edu 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); 1059444SAndreas.Sandberg@ARM.com 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }}); 1069444SAndreas.Sandberg@ARM.com 1072307SN/A 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 1082348SN/A 0x60: addqv({{ 1092307SN/A uint64_t tmp = Ra + Rb_or_imm; 1102307SN/A // signed overflow occurs when operands have same sign 1112292SN/A // and sign of result does not match. 1122292SN/A if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1132292SN/A fault = new IntegerOverflowFault; 1142292SN/A Rc = tmp; 1152292SN/A }}); 11611780Sarthur.perais@inria.fr 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 1172292SN/A 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 1182292SN/A 1192292SN/A 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }}); 1202292SN/A 0x49: sublv({{ 1212292SN/A uint32_t tmp = Ra.sl - Rb_or_imm.sl; 1222292SN/A // signed overflow detection is same as for add, 1232292SN/A // except we need to look at the *complemented* 1242292SN/A // sign bit of the subtrahend (Rb), i.e., if the initial 1258545Ssaidi@eecs.umich.edu // signs are the *same* then no overflow can occur 1268545Ssaidi@eecs.umich.edu if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1278545Ssaidi@eecs.umich.edu fault = new IntegerOverflowFault; 1288199SAli.Saidi@ARM.com Rc.sl = tmp; 1298199SAli.Saidi@ARM.com }}); 1308199SAli.Saidi@ARM.com 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); 1318199SAli.Saidi@ARM.com 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }}); 1328199SAli.Saidi@ARM.com 1338545Ssaidi@eecs.umich.edu 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 1348545Ssaidi@eecs.umich.edu 0x69: subqv({{ 1358545Ssaidi@eecs.umich.edu uint64_t tmp = Ra - Rb_or_imm; 1368545Ssaidi@eecs.umich.edu // signed overflow detection is same as for add, 1378545Ssaidi@eecs.umich.edu // except we need to look at the *complemented* 1388545Ssaidi@eecs.umich.edu // sign bit of the subtrahend (Rb), i.e., if the initial 1392292SN/A // signs are the *same* then no overflow can occur 1402292SN/A if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1412292SN/A fault = new IntegerOverflowFault; 1422329SN/A Rc = tmp; 1432292SN/A }}); 1442292SN/A 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 1452292SN/A 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 1462292SN/A 1472292SN/A 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 1482292SN/A 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }}); 1492292SN/A 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }}); 1502292SN/A 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }}); 1512292SN/A 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }}); 1522292SN/A 1532292SN/A 0x0f: cmpbge({{ 1542292SN/A int hi = 7; 1552292SN/A int lo = 0; 1562292SN/A uint64_t tmp = 0; 1572790Sktlim@umich.edu for (int i = 0; i < 8; ++i) { 1582790Sktlim@umich.edu tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i; 1592669Sktlim@umich.edu hi += 8; 1602669Sktlim@umich.edu lo += 8; 1612292SN/A } 1622292SN/A Rc = tmp; 1632292SN/A }}); 1642292SN/A } 1652292SN/A 1662292SN/A 0x11: decode INTFUNC { // integer logical operations 1672292SN/A 1682292SN/A 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 1692292SN/A 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 1702292SN/A 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 1712292SN/A 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 1722292SN/A 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 1732292SN/A 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 1742292SN/A 1752292SN/A // conditional moves 1762292SN/A 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 1772292SN/A 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 1782292SN/A 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 1792292SN/A 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 1802292SN/A 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }}); 1812292SN/A 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }}); 1822292SN/A 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }}); 1832292SN/A 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }}); 18410239Sbinhpham@cs.rutgers.edu 18510239Sbinhpham@cs.rutgers.edu // For AMASK, RA must be R31. 18610239Sbinhpham@cs.rutgers.edu 0x61: decode RA { 18710239Sbinhpham@cs.rutgers.edu 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 18810239Sbinhpham@cs.rutgers.edu } 1892292SN/A 1902292SN/A // For IMPLVER, RA must be R31 and the B operand 1912292SN/A // must be the immediate value 1. 1922292SN/A 0x6c: decode RA { 1932292SN/A 31: decode IMM { 1942292SN/A 1: decode INTIMM { 1952292SN/A // return EV5 for FULL_SYSTEM and EV6 otherwise 1962292SN/A 1: implver({{ 1972292SN/A#if FULL_SYSTEM 1982292SN/A Rc = 1; 1999444SAndreas.Sandberg@ARM.com#else 2009444SAndreas.Sandberg@ARM.com Rc = 2; 2019444SAndreas.Sandberg@ARM.com#endif 2022292SN/A }}); 2032292SN/A } 2042292SN/A } 2052292SN/A } 2062292SN/A 2072292SN/A#if FULL_SYSTEM 2089444SAndreas.Sandberg@ARM.com // The mysterious 11.25... 2099444SAndreas.Sandberg@ARM.com 0x25: WarnUnimpl::eleven25(); 2109444SAndreas.Sandberg@ARM.com#endif 2119444SAndreas.Sandberg@ARM.com } 2129444SAndreas.Sandberg@ARM.com 2139444SAndreas.Sandberg@ARM.com 0x12: decode INTFUNC { 2142292SN/A 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 2152292SN/A 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }}); 2162292SN/A 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }}); 2172292SN/A 2182292SN/A 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 2192292SN/A 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 2202292SN/A 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 2212292SN/A 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 2222292SN/A 2232292SN/A 0x52: mskwh({{ 2242292SN/A int bv = Rb_or_imm<2:0>; 2252678Sktlim@umich.edu Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 2262678Sktlim@umich.edu }}); 2272292SN/A 0x62: msklh({{ 2282907Sktlim@umich.edu int bv = Rb_or_imm<2:0>; 2292907Sktlim@umich.edu Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 2302907Sktlim@umich.edu }}); 2312292SN/A 0x72: mskqh({{ 2329444SAndreas.Sandberg@ARM.com int bv = Rb_or_imm<2:0>; 2339444SAndreas.Sandberg@ARM.com Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 2349444SAndreas.Sandberg@ARM.com }}); 2352698Sktlim@umich.edu 2362678Sktlim@umich.edu 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 2372678Sktlim@umich.edu 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 2386974Stjones1@inf.ed.ac.uk 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 2396974Stjones1@inf.ed.ac.uk 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }}); 2406974Stjones1@inf.ed.ac.uk 2412698Sktlim@umich.edu 0x5a: extwh({{ 2423349Sbinkertn@umich.edu Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 2432693Sktlim@umich.edu 0x6a: extlh({{ 2442292SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 2452292SN/A 0x7a: extqh({{ 2462292SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 2476974Stjones1@inf.ed.ac.uk 2486974Stjones1@inf.ed.ac.uk 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 2496974Stjones1@inf.ed.ac.uk 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 2502292SN/A 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 2519440SAndreas.Sandberg@ARM.com 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 2522292SN/A 2539440SAndreas.Sandberg@ARM.com 0x57: inswh({{ 2542292SN/A int bv = Rb_or_imm<2:0>; 2559440SAndreas.Sandberg@ARM.com Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0; 2562292SN/A }}); 2579440SAndreas.Sandberg@ARM.com 0x67: inslh({{ 2582292SN/A int bv = Rb_or_imm<2:0>; 2592329SN/A Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0; 2602329SN/A }}); 2619440SAndreas.Sandberg@ARM.com 0x77: insqh({{ 2622329SN/A int bv = Rb_or_imm<2:0>; 2632292SN/A Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0; 2642292SN/A }}); 2652733Sktlim@umich.edu 2662292SN/A 0x30: zap({{ 2672292SN/A uint64_t zapmask = 0; 2682292SN/A for (int i = 0; i < 8; ++i) { 2692292SN/A if (Rb_or_imm<i:>) 2702907Sktlim@umich.edu zapmask |= (mask(8) << (i * 8)); 2712907Sktlim@umich.edu } 2722669Sktlim@umich.edu Rc = Ra & ~zapmask; 2732907Sktlim@umich.edu }}); 2748922Swilliam.wang@arm.com 0x31: zapnot({{ 2752292SN/A uint64_t zapmask = 0; 2762698Sktlim@umich.edu for (int i = 0; i < 8; ++i) { 2779044SAli.Saidi@ARM.com if (!Rb_or_imm<i:>) 2782678Sktlim@umich.edu zapmask |= (mask(8) << (i * 8)); 2792678Sktlim@umich.edu } 2802698Sktlim@umich.edu Rc = Ra & ~zapmask; 2812678Sktlim@umich.edu }}); 28210537Sandreas.hansson@arm.com } 28310537Sandreas.hansson@arm.com 28410537Sandreas.hansson@arm.com 0x13: decode INTFUNC { // integer multiplies 2859046SAli.Saidi@ARM.com 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 2862678Sktlim@umich.edu 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 2872698Sktlim@umich.edu 0x30: umulh({{ 2882678Sktlim@umich.edu uint64_t hi, lo; 2899046SAli.Saidi@ARM.com mul128(Ra, Rb_or_imm, hi, lo); 2909046SAli.Saidi@ARM.com Rc = hi; 2919046SAli.Saidi@ARM.com }}, IntMultOp); 2929046SAli.Saidi@ARM.com 0x40: mullv({{ 2939046SAli.Saidi@ARM.com // 32-bit multiply with trap on overflow 2949046SAli.Saidi@ARM.com int64_t Rax = Ra.sl; // sign extended version of Ra.sl 2959046SAli.Saidi@ARM.com int64_t Rbx = Rb_or_imm.sl; 2969046SAli.Saidi@ARM.com int64_t tmp = Rax * Rbx; 2972698Sktlim@umich.edu // To avoid overflow, all the upper 32 bits must match 2982678Sktlim@umich.edu // the sign bit of the lower 32. We code this as 2992698Sktlim@umich.edu // checking the upper 33 bits for all 0s or all 1s. 3002678Sktlim@umich.edu uint64_t sign_bits = tmp<63:31>; 3016974Stjones1@inf.ed.ac.uk if (sign_bits != 0 && sign_bits != mask(33)) 3026974Stjones1@inf.ed.ac.uk fault = new IntegerOverflowFault; 3036974Stjones1@inf.ed.ac.uk Rc.sl = tmp<31:0>; 3046974Stjones1@inf.ed.ac.uk }}, IntMultOp); 30510333Smitch.hayenga@arm.com 0x60: mulqv({{ 30610333Smitch.hayenga@arm.com // 64-bit multiply with trap on overflow 3076974Stjones1@inf.ed.ac.uk uint64_t hi, lo; 3086974Stjones1@inf.ed.ac.uk mul128(Ra, Rb_or_imm, hi, lo); 3096974Stjones1@inf.ed.ac.uk // all the upper 64 bits must match the sign bit of 3102678Sktlim@umich.edu // the lower 64 3112678Sktlim@umich.edu if (!((hi == 0 && lo<63:> == 0) || 3122698Sktlim@umich.edu (hi == mask(64) && lo<63:> == 1))) 3132678Sktlim@umich.edu fault = new IntegerOverflowFault; 3142678Sktlim@umich.edu Rc = lo; 3152678Sktlim@umich.edu }}, IntMultOp); 3162678Sktlim@umich.edu } 3172678Sktlim@umich.edu 3182678Sktlim@umich.edu 0x1c: decode INTFUNC { 3192678Sktlim@umich.edu 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 3202678Sktlim@umich.edu 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } 3212678Sktlim@umich.edu 0x32: ctlz({{ 3225336Shines@cs.fsu.edu uint64_t count = 0; 3232678Sktlim@umich.edu uint64_t temp = Rb; 3242678Sktlim@umich.edu if (temp<63:32>) temp >>= 32; else count += 32; 3252698Sktlim@umich.edu if (temp<31:16>) temp >>= 16; else count += 16; 3262678Sktlim@umich.edu if (temp<15:8>) temp >>= 8; else count += 8; 3272678Sktlim@umich.edu if (temp<7:4>) temp >>= 4; else count += 4; 3282698Sktlim@umich.edu if (temp<3:2>) temp >>= 2; else count += 2; 3292678Sktlim@umich.edu if (temp<1:1>) temp >>= 1; else count += 1; 3302678Sktlim@umich.edu if ((temp<0:0>) != 0x1) count += 1; 3312678Sktlim@umich.edu Rc = count; 3322678Sktlim@umich.edu }}, IntAluOp); 3332678Sktlim@umich.edu 3342678Sktlim@umich.edu 0x33: cttz({{ 3352292SN/A uint64_t count = 0; 3362292SN/A uint64_t temp = Rb; 3372292SN/A if (!(temp<31:0>)) { temp >>= 32; count += 32; } 3382292SN/A if (!(temp<15:0>)) { temp >>= 16; count += 16; } 3394326Sgblack@eecs.umich.edu if (!(temp<7:0>)) { temp >>= 8; count += 8; } 3402292SN/A if (!(temp<3:0>)) { temp >>= 4; count += 4; } 3414326Sgblack@eecs.umich.edu if (!(temp<1:0>)) { temp >>= 2; count += 2; } 3424395Ssaidi@eecs.umich.edu if (!(temp<0:0> & ULL(0x1))) count += 1; 3434326Sgblack@eecs.umich.edu Rc = count; 3442292SN/A }}, IntAluOp); 3459152Satgutier@umich.edu 3469152Satgutier@umich.edu format FailUnimpl { 3479152Satgutier@umich.edu 0x30: ctpop(); 3489152Satgutier@umich.edu 0x31: perr(); 3499152Satgutier@umich.edu 0x34: unpkbw(); 3502292SN/A 0x35: unpkbl(); 3512292SN/A 0x36: pkwb(); 3526974Stjones1@inf.ed.ac.uk 0x37: pklb(); 35310031SAli.Saidi@ARM.com 0x38: minsb8(); 3544326Sgblack@eecs.umich.edu 0x39: minsw4(); 3554395Ssaidi@eecs.umich.edu 0x3a: minub8(); 3564326Sgblack@eecs.umich.edu 0x3b: minuw4(); 3579046SAli.Saidi@ARM.com 0x3c: maxub8(); 3589046SAli.Saidi@ARM.com 0x3d: maxuw4(); 3592292SN/A 0x3e: maxsb8(); 3602292SN/A 0x3f: maxsw4(); 3612669Sktlim@umich.edu } 3622669Sktlim@umich.edu 3636974Stjones1@inf.ed.ac.uk format BasicOperateWithNopCheck { 3646974Stjones1@inf.ed.ac.uk 0x70: decode RB { 3656974Stjones1@inf.ed.ac.uk 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp); 3662292SN/A } 3679046SAli.Saidi@ARM.com 0x78: decode RB { 3686974Stjones1@inf.ed.ac.uk 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }}, 3696974Stjones1@inf.ed.ac.uk FloatCvtOp); 3702292SN/A } 3712292SN/A } 3722292SN/A } 3732292SN/A } 3742292SN/A 3752292SN/A // Conditional branches. 37610031SAli.Saidi@ARM.com format CondBranch { 37710031SAli.Saidi@ARM.com 0x39: beq({{ cond = (Ra == 0); }}); 37810031SAli.Saidi@ARM.com 0x3d: bne({{ cond = (Ra != 0); }}); 37910031SAli.Saidi@ARM.com 0x3e: bge({{ cond = (Ra.sq >= 0); }}); 38010031SAli.Saidi@ARM.com 0x3f: bgt({{ cond = (Ra.sq > 0); }}); 3812292SN/A 0x3b: ble({{ cond = (Ra.sq <= 0); }}); 3822329SN/A 0x3a: blt({{ cond = (Ra.sq < 0); }}); 3832292SN/A 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 3842292SN/A 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 3856221Snate@binkert.org 3862292SN/A 0x31: fbeq({{ cond = (Fa == 0); }}); 3872292SN/A 0x35: fbne({{ cond = (Fa != 0); }}); 3882292SN/A 0x36: fbge({{ cond = (Fa >= 0); }}); 3892292SN/A 0x37: fbgt({{ cond = (Fa > 0); }}); 3902292SN/A 0x33: fble({{ cond = (Fa <= 0); }}); 3912292SN/A 0x32: fblt({{ cond = (Fa < 0); }}); 3922292SN/A } 3932329SN/A 3942329SN/A // unconditional branches 3952329SN/A format UncondBranch { 3962292SN/A 0x30: br(); 3972329SN/A 0x34: bsr(IsCall); 3982329SN/A } 3992329SN/A 4002292SN/A // indirect branches 4012292SN/A 0x1a: decode JMPFUNC { 4028199SAli.Saidi@ARM.com format Jump { 4038199SAli.Saidi@ARM.com 0: jmp(); 4048199SAli.Saidi@ARM.com 1: jsr(IsCall); 4058199SAli.Saidi@ARM.com 2: ret(IsReturn); 4068199SAli.Saidi@ARM.com 3: jsr_coroutine(IsCall, IsReturn); 4078199SAli.Saidi@ARM.com } 4088199SAli.Saidi@ARM.com } 4098199SAli.Saidi@ARM.com 4102292SN/A // Square root and integer-to-FP moves 4112292SN/A 0x14: decode FP_SHORTFUNC { 4122329SN/A // Integer to FP register moves must have RB == 31 4132292SN/A 0x4: decode RB { 4142292SN/A 31: decode FP_FULLFUNC { 4152292SN/A format BasicOperateWithNopCheck { 4162292SN/A 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 4172292SN/A 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 4182292SN/A 0x014: FailUnimpl::itoff(); // VAX-format conversion 4192292SN/A } 4202292SN/A } 4212292SN/A } 4222292SN/A 4232292SN/A // Square root instructions must have FA == 31 4242329SN/A 0xb: decode FA { 4252329SN/A 31: decode FP_TYPEFUNC { 4262292SN/A format FloatingPointOperate { 4272292SN/A#if SS_COMPATIBLE_FP 4282292SN/A 0x0b: sqrts({{ 4292292SN/A if (Fb < 0.0) 4302292SN/A fault = new ArithmeticFault; 4312292SN/A Fc = sqrt(Fb); 43211780Sarthur.perais@inria.fr }}, FloatSqrtOp); 43311780Sarthur.perais@inria.fr#else 4342292SN/A 0x0b: sqrts({{ 43511780Sarthur.perais@inria.fr if (Fb.sf < 0.0) 43611780Sarthur.perais@inria.fr fault = new ArithmeticFault; 4372292SN/A Fc.sf = sqrt(Fb.sf); 4382292SN/A }}, FloatSqrtOp); 4392292SN/A#endif 4408545Ssaidi@eecs.umich.edu 0x2b: sqrtt({{ 4418545Ssaidi@eecs.umich.edu if (Fb < 0.0) 4428545Ssaidi@eecs.umich.edu fault = new ArithmeticFault; 4432292SN/A Fc = sqrt(Fb); 4442292SN/A }}, FloatSqrtOp); 4452292SN/A } 4462292SN/A } 4472292SN/A } 4482292SN/A 4492292SN/A // VAX-format sqrtf and sqrtg are not implemented 4502292SN/A 0xa: FailUnimpl::sqrtfg(); 4512292SN/A } 4522292SN/A 4532292SN/A // IEEE floating point 4542292SN/A 0x16: decode FP_SHORTFUNC_TOP2 { 4552698Sktlim@umich.edu // The top two bits of the short function code break this 4562698Sktlim@umich.edu // space into four groups: binary ops, compares, reserved, and 4572693Sktlim@umich.edu // conversions. See Table 4-12 of AHB. There are different 4582698Sktlim@umich.edu // special cases in these different groups, so we decode on 4592678Sktlim@umich.edu // these top two bits first just to select a decode strategy. 4602678Sktlim@umich.edu // Most of these instructions may have various trapping and 4618727Snilay@cs.wisc.edu // rounding mode flags set; these are decoded in the 4628727Snilay@cs.wisc.edu // FloatingPointDecode template used by the 4638727Snilay@cs.wisc.edu // FloatingPointOperate format. 4642292SN/A 4652292SN/A // add/sub/mul/div: just decode on the short function code 4662292SN/A // and source type. All valid trapping and rounding modes apply. 4676974Stjones1@inf.ed.ac.uk 0: decode FP_TRAPMODE { 4686974Stjones1@inf.ed.ac.uk // check for valid trapping modes here 4696974Stjones1@inf.ed.ac.uk 0,1,5,7: decode FP_TYPEFUNC { 4706974Stjones1@inf.ed.ac.uk format FloatingPointOperate { 4716974Stjones1@inf.ed.ac.uk#if SS_COMPATIBLE_FP 4726974Stjones1@inf.ed.ac.uk 0x00: adds({{ Fc = Fa + Fb; }}); 4736974Stjones1@inf.ed.ac.uk 0x01: subs({{ Fc = Fa - Fb; }}); 4748727Snilay@cs.wisc.edu 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 4758727Snilay@cs.wisc.edu 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 4768727Snilay@cs.wisc.edu#else 4772292SN/A 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }}); 4782292SN/A 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }}); 4792292SN/A 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); 4802727Sktlim@umich.edu 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp); 4815999Snate@binkert.org#endif 4822307SN/A 4833126Sktlim@umich.edu 0x20: addt({{ Fc = Fa + Fb; }}); 4845999Snate@binkert.org 0x21: subt({{ Fc = Fa - Fb; }}); 4853126Sktlim@umich.edu 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 4863126Sktlim@umich.edu 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 4875999Snate@binkert.org } 4883126Sktlim@umich.edu } 4893126Sktlim@umich.edu } 4903126Sktlim@umich.edu 4915999Snate@binkert.org // Floating-point compare instructions must have the default 4923126Sktlim@umich.edu // rounding mode, and may use the default trapping mode or 4933126Sktlim@umich.edu // /SU. Both trapping modes are treated the same by M5; the 4945999Snate@binkert.org // only difference on the real hardware (as far a I can tell) 4953126Sktlim@umich.edu // is that without /SU you'd get an imprecise trap if you 4962727Sktlim@umich.edu // tried to compare a NaN with something else (instead of an 4975999Snate@binkert.org // "unordered" result). 4982727Sktlim@umich.edu 1: decode FP_FULLFUNC { 4992727Sktlim@umich.edu format BasicOperateWithNopCheck { 5005999Snate@binkert.org 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 5012727Sktlim@umich.edu FloatCmpOp); 5022727Sktlim@umich.edu 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 5035999Snate@binkert.org FloatCmpOp); 5042727Sktlim@umich.edu 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 5052727Sktlim@umich.edu FloatCmpOp); 5065999Snate@binkert.org 0x0a4, 0x5a4: cmptun({{ // unordered 5072727Sktlim@umich.edu Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 5082727Sktlim@umich.edu }}, FloatCmpOp); 5095999Snate@binkert.org } 5102727Sktlim@umich.edu } 5112292SN/A 5122292SN/A // The FP-to-integer and integer-to-FP conversion insts 5137520Sgblack@eecs.umich.edu // require that FA be 31. 51411302Ssteve.reinhardt@amd.com 3: decode FA { 5152292SN/A 31: decode FP_TYPEFUNC { 5162292SN/A format FloatingPointOperate { 5177520Sgblack@eecs.umich.edu 0x2f: decode FP_ROUNDMODE { 5187520Sgblack@eecs.umich.edu format FPFixedRounding { 5192292SN/A // "chopped" i.e. round toward zero 5202292SN/A 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }}, 5212292SN/A Chopped); 5222292SN/A // round to minus infinity 5232292SN/A 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }}, 5242292SN/A MinusInfinity); 5252292SN/A } 5262292SN/A default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }}); 5272292SN/A } 5282292SN/A 5292292SN/A // The cvtts opcode is overloaded to be cvtst if the trap 5302292SN/A // mode is 2 or 6 (which are not valid otherwise) 5312292SN/A 0x2c: decode FP_FULLFUNC { 5322292SN/A format BasicOperateWithNopCheck { 5332292SN/A // trap on denorm version "cvtst/s" is 5342292SN/A // simulated same as cvtst 5352292SN/A 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }}); 5362292SN/A } 5372292SN/A default: cvtts({{ Fc.sf = Fb; }}); 5382292SN/A } 5392292SN/A 5402292SN/A // The trapping mode for integer-to-FP conversions 5412292SN/A // must be /SUI or nothing; /U and /SU are not 5422292SN/A // allowed. The full set of rounding modes are 5432292SN/A // supported though. 5442292SN/A 0x3c: decode FP_TRAPMODE { 5452292SN/A 0,7: cvtqs({{ Fc.sf = Fb.sq; }}); 5462292SN/A } 5472292SN/A 0x3e: decode FP_TRAPMODE { 5482292SN/A 0,7: cvtqt({{ Fc = Fb.sq; }}); 5492292SN/A } 5502292SN/A } 5512292SN/A } 5526974Stjones1@inf.ed.ac.uk } 55311302Ssteve.reinhardt@amd.com } 5542292SN/A 5552669Sktlim@umich.edu // misc FP operate 5562292SN/A 0x17: decode FP_FULLFUNC { 5572669Sktlim@umich.edu format BasicOperateWithNopCheck { 5582669Sktlim@umich.edu 0x010: cvtlq({{ 5592669Sktlim@umich.edu Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>; 5602292SN/A }}); 56110824SAndreas.Sandberg@ARM.com 0x030: cvtql({{ 56210824SAndreas.Sandberg@ARM.com Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 56310824SAndreas.Sandberg@ARM.com }}); 56410824SAndreas.Sandberg@ARM.com 56510824SAndreas.Sandberg@ARM.com // We treat the precise & imprecise trapping versions of 5662731Sktlim@umich.edu // cvtql identically. 5672669Sktlim@umich.edu 0x130, 0x530: cvtqlv({{ 5682727Sktlim@umich.edu // To avoid overflow, all the upper 32 bits must match 56910824SAndreas.Sandberg@ARM.com // the sign bit of the lower 32. We code this as 5707720Sgblack@eecs.umich.edu // checking the upper 33 bits for all 0s or all 1s. 5714032Sktlim@umich.edu uint64_t sign_bits = Fb.uq<63:31>; 5724032Sktlim@umich.edu if (sign_bits != 0 && sign_bits != mask(33)) 5734032Sktlim@umich.edu fault = new IntegerOverflowFault; 5744032Sktlim@umich.edu Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 5754032Sktlim@umich.edu }}); 5766974Stjones1@inf.ed.ac.uk 5776974Stjones1@inf.ed.ac.uk 0x020: cpys({{ // copy sign 5786974Stjones1@inf.ed.ac.uk Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>; 5796974Stjones1@inf.ed.ac.uk }}); 58010474Sandreas.hansson@arm.com 0x021: cpysn({{ // copy sign negated 58110824SAndreas.Sandberg@ARM.com Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>; 58210474Sandreas.hansson@arm.com }}); 5832292SN/A 0x022: cpyse({{ // copy sign and exponent 5842292SN/A Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>; 5852292SN/A }}); 5862669Sktlim@umich.edu 5872292SN/A 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 5882292SN/A 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 5892292SN/A 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 5902292SN/A 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 5916974Stjones1@inf.ed.ac.uk 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 5926974Stjones1@inf.ed.ac.uk 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 5936974Stjones1@inf.ed.ac.uk 5942292SN/A 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess); 5956102Sgblack@eecs.umich.edu 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess); 5966974Stjones1@inf.ed.ac.uk } 5973326Sktlim@umich.edu } 5983326Sktlim@umich.edu 5993326Sktlim@umich.edu // miscellaneous mem-format ops 6009046SAli.Saidi@ARM.com 0x18: decode MEMFUNC { 6013326Sktlim@umich.edu format WarnUnimpl { 6029046SAli.Saidi@ARM.com 0x8000: fetch(); 6032292SN/A 0xa000: fetch_m(); 6042292SN/A 0xe800: ecb(); 6058481Sgblack@eecs.umich.edu } 6068481Sgblack@eecs.umich.edu 6078481Sgblack@eecs.umich.edu format MiscPrefetch { 6088481Sgblack@eecs.umich.edu 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 6098481Sgblack@eecs.umich.edu {{ xc->writeHint(EA, 64, memAccessFlags); }}, 6109180Sandreas.hansson@arm.com mem_flags = NO_FAULT, 6118949Sandreas.hansson@arm.com inst_flags = [IsMemRef, IsDataPrefetch, 6128481Sgblack@eecs.umich.edu IsStore, MemWriteOp]); 61312171Smatthiashille8@gmail.com } 6148481Sgblack@eecs.umich.edu 6158481Sgblack@eecs.umich.edu format BasicOperate { 6168481Sgblack@eecs.umich.edu 0xc000: rpcc({{ 6178481Sgblack@eecs.umich.edu#if FULL_SYSTEM 6188949Sandreas.hansson@arm.com /* Rb is a fake dependency so here is a fun way to get 6198949Sandreas.hansson@arm.com * the parser to understand that. 6208481Sgblack@eecs.umich.edu */ 6218481Sgblack@eecs.umich.edu Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC, fault) + (Rb & 0); 6228481Sgblack@eecs.umich.edu 6238481Sgblack@eecs.umich.edu#else 6248481Sgblack@eecs.umich.edu Ra = curTick; 6259180Sandreas.hansson@arm.com#endif 6268481Sgblack@eecs.umich.edu }}, IsUnverifiable); 6278481Sgblack@eecs.umich.edu 6288481Sgblack@eecs.umich.edu // All of the barrier instructions below do nothing in 6298481Sgblack@eecs.umich.edu // their execute() methods (hence the empty code blocks). 6308481Sgblack@eecs.umich.edu // All of their functionality is hard-coded in the 6318481Sgblack@eecs.umich.edu // pipeline based on the flags IsSerializing, 6328481Sgblack@eecs.umich.edu // IsMemBarrier, and IsWriteBarrier. In the current 6338481Sgblack@eecs.umich.edu // detailed CPU model, the execute() function only gets 6348481Sgblack@eecs.umich.edu // called at fetch, so there's no way to generate pipeline 6359179Sandreas.hansson@arm.com // behavior at any other stage. Once we go to an 6368481Sgblack@eecs.umich.edu // exec-in-exec CPU model we should be able to get rid of 6378481Sgblack@eecs.umich.edu // these flags and implement this behavior via the 6388481Sgblack@eecs.umich.edu // execute() methods. 6392292SN/A 6402292SN/A // trapb is just a barrier on integer traps, where excb is 6412292SN/A // a barrier on integer and FP traps. "EXCB is thus a 6422292SN/A // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 6432292SN/A // them the same though. 6442292SN/A 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 6452292SN/A 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); 6462292SN/A 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 6472292SN/A 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 6482292SN/A } 6492292SN/A 6502292SN/A#if FULL_SYSTEM 6512292SN/A format BasicOperate { 6522292SN/A 0xe000: rc({{ 65312355Snikos.nikoleris@arm.com Ra = xc->readIntrFlag(); 65412355Snikos.nikoleris@arm.com xc->setIntrFlag(0); 65512355Snikos.nikoleris@arm.com }}, IsNonSpeculative); 65612355Snikos.nikoleris@arm.com 0xf000: rs({{ 65712355Snikos.nikoleris@arm.com Ra = xc->readIntrFlag(); 65812355Snikos.nikoleris@arm.com xc->setIntrFlag(1); 6592292SN/A }}, IsNonSpeculative); 66012355Snikos.nikoleris@arm.com } 6614032Sktlim@umich.edu#else 6629046SAli.Saidi@ARM.com format FailUnimpl { 6632292SN/A 0xe000: rc(); 6642292SN/A 0xf000: rs(); 6652292SN/A } 6662292SN/A#endif 6672669Sktlim@umich.edu } 6682292SN/A 6692669Sktlim@umich.edu#if FULL_SYSTEM 6702669Sktlim@umich.edu 0x00: CallPal::call_pal({{ 6712292SN/A if (!palValid || 6722669Sktlim@umich.edu (palPriv 6732292SN/A && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { 6742292SN/A // invalid pal function code, or attempt to do privileged 6752669Sktlim@umich.edu // PAL call in non-kernel mode 6762669Sktlim@umich.edu fault = new UnimplementedOpcodeFault; 6772292SN/A } 67812022Sar4jc@virginia.edu else { 67912022Sar4jc@virginia.edu // check to see if simulator wants to do something special 68012022Sar4jc@virginia.edu // on this PAL call (including maybe suppress it) 6812329SN/A bool dopal = xc->simPalCheck(palFunc); 6828316Sgeoffrey.blake@arm.com 6832292SN/A if (dopal) { 68410333Smitch.hayenga@arm.com xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC); 68510333Smitch.hayenga@arm.com NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE, fault) + palOffset; 68610333Smitch.hayenga@arm.com } 68710333Smitch.hayenga@arm.com } 68810031SAli.Saidi@ARM.com }}, IsNonSpeculative); 68910031SAli.Saidi@ARM.com#else 69010031SAli.Saidi@ARM.com 0x00: decode PALFUNC { 69110031SAli.Saidi@ARM.com format EmulatedCallPal { 6924326Sgblack@eecs.umich.edu 0x00: halt ({{ 6932292SN/A SimExit(curTick, "halt instruction encountered"); 6942292SN/A }}, IsNonSpeculative); 69510175SMitch.Hayenga@ARM.com 0x83: callsys({{ 6962678Sktlim@umich.edu xc->syscall(); 6978949Sandreas.hansson@arm.com }}, IsNonSpeculative); 6982678Sktlim@umich.edu // Read uniq reg into ABI return value register (r0) 6992678Sktlim@umich.edu 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); 7002678Sktlim@umich.edu // Write uniq reg with value from ABI arg register (r16) 7012292SN/A 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess); 7022292SN/A } 7032292SN/A } 7042292SN/A#endif 7057823Ssteve.reinhardt@amd.com 7062678Sktlim@umich.edu#if FULL_SYSTEM 7076974Stjones1@inf.ed.ac.uk 0x1b: decode PALMODE { 7086974Stjones1@inf.ed.ac.uk 0: OpcdecFault::hw_st_quad(); 7096974Stjones1@inf.ed.ac.uk 1: decode HW_LDST_QUAD { 7106974Stjones1@inf.ed.ac.uk format HwLoad { 7116974Stjones1@inf.ed.ac.uk 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L); 7126974Stjones1@inf.ed.ac.uk 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q); 7132727Sktlim@umich.edu } 7142292SN/A } 71512022Sar4jc@virginia.edu } 71612022Sar4jc@virginia.edu 71712022Sar4jc@virginia.edu 0x1f: decode PALMODE { 71812022Sar4jc@virginia.edu 0: OpcdecFault::hw_st_cond(); 71912022Sar4jc@virginia.edu format HwStore { 72012022Sar4jc@virginia.edu 1: decode HW_LDST_COND { 72112022Sar4jc@virginia.edu 0: decode HW_LDST_QUAD { 72212022Sar4jc@virginia.edu 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 7232292SN/A {{ Mem.ul = Ra<31:0>; }}, L); 72412022Sar4jc@virginia.edu 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 72512022Sar4jc@virginia.edu {{ Mem.uq = Ra.uq; }}, Q); 72612022Sar4jc@virginia.edu } 7272292SN/A 7282292SN/A 1: FailUnimpl::hw_st_cond(); 7292292SN/A } 7302292SN/A } 7314032Sktlim@umich.edu } 7322292SN/A 7332292SN/A 0x19: decode PALMODE { 7342292SN/A 0: OpcdecFault::hw_mfpr(); 7352292SN/A format HwMoveIPR { 7362292SN/A 1: hw_mfpr({{ 7372292SN/A Ra = xc->readMiscRegWithEffect(ipr_index, fault); 7382292SN/A }}, IsIprAccess); 7392669Sktlim@umich.edu } 7402292SN/A } 7412292SN/A 7422292SN/A 0x1d: decode PALMODE { 7432292SN/A 0: OpcdecFault::hw_mtpr(); 7442292SN/A format HwMoveIPR { 7452292SN/A 1: hw_mtpr({{ 7462292SN/A xc->setMiscRegWithEffect(ipr_index, Ra); 7472292SN/A if (traceData) { traceData->setData(Ra); } 7482669Sktlim@umich.edu }}, IsIprAccess); 7494032Sktlim@umich.edu } 7502727Sktlim@umich.edu } 7512292SN/A 7522292SN/A format BasicOperate { 7532292SN/A 0x1e: decode PALMODE { 7542292SN/A 0: OpcdecFault::hw_rei(); 7552292SN/A 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); 7562669Sktlim@umich.edu } 7572292SN/A 7584032Sktlim@umich.edu // M5 special opcodes use the reserved 0x01 opcode space 7594032Sktlim@umich.edu 0x01: decode M5FUNC { 7604032Sktlim@umich.edu 0x00: arm({{ 7614032Sktlim@umich.edu AlphaPseudo::arm(xc->xcBase()); 7626974Stjones1@inf.ed.ac.uk }}, IsNonSpeculative); 7636974Stjones1@inf.ed.ac.uk 0x01: quiesce({{ 7646974Stjones1@inf.ed.ac.uk AlphaPseudo::quiesce(xc->xcBase()); 7656974Stjones1@inf.ed.ac.uk }}, IsNonSpeculative, IsQuiesce); 7664032Sktlim@umich.edu 0x02: quiesceNs({{ 7672292SN/A AlphaPseudo::quiesceNs(xc->xcBase(), R16); 7682292SN/A }}, IsNonSpeculative, IsQuiesce); 7692292SN/A 0x03: quiesceCycles({{ 7702292SN/A AlphaPseudo::quiesceCycles(xc->xcBase(), R16); 7712292SN/A }}, IsNonSpeculative, IsQuiesce); 7727720Sgblack@eecs.umich.edu 0x04: quiesceTime({{ 7737720Sgblack@eecs.umich.edu R0 = AlphaPseudo::quiesceTime(xc->xcBase()); 7742292SN/A }}, IsNonSpeculative); 77510333Smitch.hayenga@arm.com 0x10: ivlb({{ 77610333Smitch.hayenga@arm.com AlphaPseudo::ivlb(xc->xcBase()); 77710333Smitch.hayenga@arm.com }}, No_OpClass, IsNonSpeculative); 77810333Smitch.hayenga@arm.com 0x11: ivle({{ 7792292SN/A AlphaPseudo::ivle(xc->xcBase()); 7802907Sktlim@umich.edu }}, No_OpClass, IsNonSpeculative); 7816974Stjones1@inf.ed.ac.uk 0x20: m5exit_old({{ 78210342SCurtis.Dunham@arm.com AlphaPseudo::m5exit_old(xc->xcBase()); 78310333Smitch.hayenga@arm.com }}, No_OpClass, IsNonSpeculative); 78410333Smitch.hayenga@arm.com 0x21: m5exit({{ 7856974Stjones1@inf.ed.ac.uk AlphaPseudo::m5exit(xc->xcBase(), R16); 78610333Smitch.hayenga@arm.com }}, No_OpClass, IsNonSpeculative); 7873228Sktlim@umich.edu 0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }}); 78810333Smitch.hayenga@arm.com 0x40: resetstats({{ 78910333Smitch.hayenga@arm.com AlphaPseudo::resetstats(xc->xcBase(), R16, R17); 79010333Smitch.hayenga@arm.com }}, IsNonSpeculative); 79110333Smitch.hayenga@arm.com 0x41: dumpstats({{ 79210333Smitch.hayenga@arm.com AlphaPseudo::dumpstats(xc->xcBase(), R16, R17); 7933228Sktlim@umich.edu }}, IsNonSpeculative); 79410333Smitch.hayenga@arm.com 0x42: dumpresetstats({{ 79510333Smitch.hayenga@arm.com AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17); 79610333Smitch.hayenga@arm.com }}, IsNonSpeculative); 79710333Smitch.hayenga@arm.com 0x43: m5checkpoint({{ 79810333Smitch.hayenga@arm.com AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17); 79910342SCurtis.Dunham@arm.com }}, IsNonSpeculative); 80010342SCurtis.Dunham@arm.com 0x50: m5readfile({{ 8016974Stjones1@inf.ed.ac.uk R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18); 80210333Smitch.hayenga@arm.com }}, IsNonSpeculative); 80310333Smitch.hayenga@arm.com 0x51: m5break({{ 8046974Stjones1@inf.ed.ac.uk AlphaPseudo::debugbreak(xc->xcBase()); 80510333Smitch.hayenga@arm.com }}, IsNonSpeculative); 80610333Smitch.hayenga@arm.com 0x52: m5switchcpu({{ 8076974Stjones1@inf.ed.ac.uk AlphaPseudo::switchcpu(xc->xcBase()); 80810333Smitch.hayenga@arm.com }}, IsNonSpeculative); 80910333Smitch.hayenga@arm.com 0x53: m5addsymbol({{ 81010333Smitch.hayenga@arm.com AlphaPseudo::addsymbol(xc->xcBase(), R16, R17); 81110333Smitch.hayenga@arm.com }}, IsNonSpeculative); 8126974Stjones1@inf.ed.ac.uk 0x54: m5panic({{ 81311780Sarthur.perais@inria.fr panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 81411780Sarthur.perais@inria.fr }}, IsNonSpeculative); 81511780Sarthur.perais@inria.fr 81611780Sarthur.perais@inria.fr } 81711780Sarthur.perais@inria.fr } 81810333Smitch.hayenga@arm.com#endif 81910333Smitch.hayenga@arm.com} 82010333Smitch.hayenga@arm.com