decoder.isa revision 2147
12810SN/A// -*- mode:c++ -*- 28856Sandreas.hansson@arm.com 38856Sandreas.hansson@arm.com// Copyright (c) 2003-2005 The Regents of The University of Michigan 48856Sandreas.hansson@arm.com// All rights reserved. 58856Sandreas.hansson@arm.com// 68856Sandreas.hansson@arm.com// Redistribution and use in source and binary forms, with or without 78856Sandreas.hansson@arm.com// modification, are permitted provided that the following conditions are 88856Sandreas.hansson@arm.com// met: redistributions of source code must retain the above copyright 98856Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer; 108856Sandreas.hansson@arm.com// redistributions in binary form must reproduce the above copyright 118856Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer in the 128856Sandreas.hansson@arm.com// documentation and/or other materials provided with the distribution; 138856Sandreas.hansson@arm.com// neither the name of the copyright holders nor the names of its 142810SN/A// contributors may be used to endorse or promote products derived from 152810SN/A// this software without specific prior written permission. 162810SN/A// 172810SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182810SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192810SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202810SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212810SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222810SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232810SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242810SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252810SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262810SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272810SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282810SN/A 292810SN/Adecode OPCODE default Unknown::unknown() { 302810SN/A 312810SN/A format LoadAddress { 322810SN/A 0x08: lda({{ Ra = Rb + disp; }}); 332810SN/A 0x09: ldah({{ Ra = Rb + (disp << 16); }}); 342810SN/A } 352810SN/A 362810SN/A format LoadOrNop { 372810SN/A 0x0a: ldbu({{ Ra.uq = Mem.ub; }}); 382810SN/A 0x0c: ldwu({{ Ra.uq = Mem.uw; }}); 392810SN/A 0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); 402810SN/A 0x23: ldt({{ Fa = Mem.df; }}); 412810SN/A 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED); 422810SN/A 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED); 432810SN/A 0x20: MiscPrefetch::copy_load({{ EA = Ra; }}, 442810SN/A {{ fault = xc->copySrcTranslate(EA); }}, 452810SN/A inst_flags = [IsMemRef, IsLoad, IsCopy]); 462810SN/A } 472810SN/A 483348SN/A format LoadOrPrefetch { 493348SN/A 0x28: ldl({{ Ra.sl = Mem.sl; }}); 508232Snate@binkert.org 0x29: ldq({{ Ra.uq = Mem.uq; }}, pf_flags = EVICT_NEXT); 519152Satgutier@umich.edu // IsFloating flag on lds gets the prefetch to disassemble 525338Sstever@gmail.com // using f31 instead of r31... funcitonally it's unnecessary 535338Sstever@gmail.com 0x22: lds({{ Fa.uq = s_to_t(Mem.ul); }}, 548786Sgblack@eecs.umich.edu pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); 552810SN/A } 562810SN/A 572810SN/A format Store { 588856Sandreas.hansson@arm.com 0x0e: stb({{ Mem.ub = Ra<7:0>; }}); 598856Sandreas.hansson@arm.com 0x0d: stw({{ Mem.uw = Ra<15:0>; }}); 608856Sandreas.hansson@arm.com 0x2c: stl({{ Mem.ul = Ra<31:0>; }}); 618922Swilliam.wang@arm.com 0x2d: stq({{ Mem.uq = Ra.uq; }}); 628914Sandreas.hansson@arm.com 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 638856Sandreas.hansson@arm.com 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 648856Sandreas.hansson@arm.com 0x27: stt({{ Mem.df = Fa; }}); 654475SN/A 0x24: MiscPrefetch::copy_store({{ EA = Rb; }}, 665034SN/A {{ fault = xc->copy(EA); }}, 675034SN/A inst_flags = [IsMemRef, IsStore, IsCopy]); 685314SN/A } 695314SN/A 704628SN/A format StoreCond { 715034SN/A 0x2e: stl_c({{ Mem.ul = Ra<31:0>; }}, 725034SN/A {{ 735034SN/A uint64_t tmp = write_result; 746122SSteve.Reinhardt@amd.com // see stq_c 758134SAli.Saidi@ARM.com Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 764626SN/A }}, mem_flags = LOCKED); 774626SN/A 0x2f: stq_c({{ Mem.uq = Ra; }}, 785034SN/A {{ 796122SSteve.Reinhardt@amd.com uint64_t tmp = write_result; 808883SAli.Saidi@ARM.com // If the write operation returns 0 or 1, then 818833Sdam.sunwoo@arm.com // this was a conventional store conditional, 824458SN/A // and the value indicates the success/failure 832810SN/A // of the operation. If another value is 842810SN/A // returned, then this was a Turbolaser 853013SN/A // mailbox access, and we don't update the 868856Sandreas.hansson@arm.com // result register at all. 872810SN/A Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; 883013SN/A }}, mem_flags = LOCKED); 898856Sandreas.hansson@arm.com } 902810SN/A 912810SN/A format IntegerOperate { 922810SN/A 932810SN/A 0x10: decode INTFUNC { // integer arithmetic operations 948856Sandreas.hansson@arm.com 952810SN/A 0x00: addl({{ Rc.sl = Ra.sl + Rb_or_imm.sl; }}); 963013SN/A 0x40: addlv({{ 978856Sandreas.hansson@arm.com uint32_t tmp = Ra.sl + Rb_or_imm.sl; 983013SN/A // signed overflow occurs when operands have same sign 998856Sandreas.hansson@arm.com // and sign of result does not match. 1008856Sandreas.hansson@arm.com if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1012897SN/A fault = new IntegerOverflowFault; 1024666SN/A Rc.sl = tmp; 1038922Swilliam.wang@arm.com }}); 1042897SN/A 0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }}); 1052810SN/A 0x12: s8addl({{ Rc.sl = (Ra.sl << 3) + Rb_or_imm.sl; }}); 1062810SN/A 1072844SN/A 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); 1082810SN/A 0x60: addqv({{ 1092858SN/A uint64_t tmp = Ra + Rb_or_imm; 1102858SN/A // signed overflow occurs when operands have same sign 1118856Sandreas.hansson@arm.com // and sign of result does not match. 1128922Swilliam.wang@arm.com if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1138711Sandreas.hansson@arm.com fault = new IntegerOverflowFault; 1142858SN/A Rc = tmp; 1152858SN/A }}); 1168922Swilliam.wang@arm.com 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); 1178922Swilliam.wang@arm.com 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); 1188922Swilliam.wang@arm.com 1198922Swilliam.wang@arm.com 0x09: subl({{ Rc.sl = Ra.sl - Rb_or_imm.sl; }}); 1208922Swilliam.wang@arm.com 0x49: sublv({{ 1218922Swilliam.wang@arm.com uint32_t tmp = Ra.sl - Rb_or_imm.sl; 1228922Swilliam.wang@arm.com // signed overflow detection is same as for add, 1238922Swilliam.wang@arm.com // except we need to look at the *complemented* 1248922Swilliam.wang@arm.com // sign bit of the subtrahend (Rb), i.e., if the initial 1258922Swilliam.wang@arm.com // signs are the *same* then no overflow can occur 1268922Swilliam.wang@arm.com if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>) 1278922Swilliam.wang@arm.com fault = new IntegerOverflowFault; 1288922Swilliam.wang@arm.com Rc.sl = tmp; 1298922Swilliam.wang@arm.com }}); 1308922Swilliam.wang@arm.com 0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }}); 1318922Swilliam.wang@arm.com 0x1b: s8subl({{ Rc.sl = (Ra.sl << 3) - Rb_or_imm.sl; }}); 1328922Swilliam.wang@arm.com 1338922Swilliam.wang@arm.com 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); 1348922Swilliam.wang@arm.com 0x69: subqv({{ 1354628SN/A uint64_t tmp = Ra - Rb_or_imm; 1362858SN/A // signed overflow detection is same as for add, 1372810SN/A // except we need to look at the *complemented* 1382810SN/A // sign bit of the subtrahend (Rb), i.e., if the initial 1392810SN/A // signs are the *same* then no overflow can occur 1402810SN/A if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) 1412810SN/A fault = new IntegerOverflowFault; 1424022SN/A Rc = tmp; 1434022SN/A }}); 1444022SN/A 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); 1452810SN/A 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); 1462810SN/A 1478833Sdam.sunwoo@arm.com 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); 1482810SN/A 0x6d: cmple({{ Rc = (Ra.sq <= Rb_or_imm.sq); }}); 1492810SN/A 0x4d: cmplt({{ Rc = (Ra.sq < Rb_or_imm.sq); }}); 1502810SN/A 0x3d: cmpule({{ Rc = (Ra.uq <= Rb_or_imm.uq); }}); 1512810SN/A 0x1d: cmpult({{ Rc = (Ra.uq < Rb_or_imm.uq); }}); 1528833Sdam.sunwoo@arm.com 1538833Sdam.sunwoo@arm.com 0x0f: cmpbge({{ 1548833Sdam.sunwoo@arm.com int hi = 7; 1552810SN/A int lo = 0; 1562810SN/A uint64_t tmp = 0; 1574871SN/A for (int i = 0; i < 8; ++i) { 1584871SN/A tmp |= (Ra.uq<hi:lo> >= Rb_or_imm.uq<hi:lo>) << i; 1594871SN/A hi += 8; 1604871SN/A lo += 8; 1614871SN/A } 1624871SN/A Rc = tmp; 1634871SN/A }}); 1644871SN/A } 1654871SN/A 1664871SN/A 0x11: decode INTFUNC { // integer logical operations 1672810SN/A 1682810SN/A 0x00: and({{ Rc = Ra & Rb_or_imm; }}); 1692810SN/A 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); 1708833Sdam.sunwoo@arm.com 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); 1712810SN/A 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); 1724871SN/A 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); 1738833Sdam.sunwoo@arm.com 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); 1748833Sdam.sunwoo@arm.com 1758833Sdam.sunwoo@arm.com // conditional moves 1762810SN/A 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); 1772810SN/A 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); 1782810SN/A 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); 1792810SN/A 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); 1808833Sdam.sunwoo@arm.com 0x44: cmovlt({{ Rc = (Ra.sq < 0) ? Rb_or_imm : Rc; }}); 1812810SN/A 0x46: cmovge({{ Rc = (Ra.sq >= 0) ? Rb_or_imm : Rc; }}); 1824871SN/A 0x64: cmovle({{ Rc = (Ra.sq <= 0) ? Rb_or_imm : Rc; }}); 1838833Sdam.sunwoo@arm.com 0x66: cmovgt({{ Rc = (Ra.sq > 0) ? Rb_or_imm : Rc; }}); 1848833Sdam.sunwoo@arm.com 1858833Sdam.sunwoo@arm.com // For AMASK, RA must be R31. 1862810SN/A 0x61: decode RA { 1872810SN/A 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); 1884022SN/A } 1894022SN/A 1904022SN/A // For IMPLVER, RA must be R31 and the B operand 1912810SN/A // must be the immediate value 1. 1922810SN/A 0x6c: decode RA { 1938833Sdam.sunwoo@arm.com 31: decode IMM { 1942810SN/A 1: decode INTIMM { 1952810SN/A // return EV5 for FULL_SYSTEM and EV6 otherwise 1962810SN/A 1: implver({{ 1972810SN/A#if FULL_SYSTEM 1988833Sdam.sunwoo@arm.com Rc = 1; 1998833Sdam.sunwoo@arm.com#else 2008833Sdam.sunwoo@arm.com Rc = 2; 2012810SN/A#endif 2022810SN/A }}); 2032810SN/A } 2042810SN/A } 2052810SN/A } 2068833Sdam.sunwoo@arm.com 2072810SN/A#if FULL_SYSTEM 2084871SN/A // The mysterious 11.25... 2098833Sdam.sunwoo@arm.com 0x25: WarnUnimpl::eleven25(); 2108833Sdam.sunwoo@arm.com#endif 2118833Sdam.sunwoo@arm.com } 2122810SN/A 2132810SN/A 0x12: decode INTFUNC { 2142810SN/A 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); 2152810SN/A 0x34: srl({{ Rc = Ra.uq >> Rb_or_imm<5:0>; }}); 2168833Sdam.sunwoo@arm.com 0x3c: sra({{ Rc = Ra.sq >> Rb_or_imm<5:0>; }}); 2172810SN/A 2184871SN/A 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); 2198833Sdam.sunwoo@arm.com 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); 2208833Sdam.sunwoo@arm.com 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); 2218833Sdam.sunwoo@arm.com 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); 2222810SN/A 2232810SN/A 0x52: mskwh({{ 2244022SN/A int bv = Rb_or_imm<2:0>; 2254022SN/A Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; 2264022SN/A }}); 2272810SN/A 0x62: msklh({{ 2282810SN/A int bv = Rb_or_imm<2:0>; 2298833Sdam.sunwoo@arm.com Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; 2302810SN/A }}); 2312810SN/A 0x72: mskqh({{ 2322810SN/A int bv = Rb_or_imm<2:0>; 2332810SN/A Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; 2348833Sdam.sunwoo@arm.com }}); 2358833Sdam.sunwoo@arm.com 2368833Sdam.sunwoo@arm.com 0x06: extbl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); 2372810SN/A 0x16: extwl({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); 2382810SN/A 0x26: extll({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); 2392810SN/A 0x36: extql({{ Rc = (Ra.uq >> (Rb_or_imm<2:0> * 8)); }}); 2402810SN/A 2412810SN/A 0x5a: extwh({{ 2428833Sdam.sunwoo@arm.com Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); 2432810SN/A 0x6a: extlh({{ 2444871SN/A Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); 2458833Sdam.sunwoo@arm.com 0x7a: extqh({{ 2468833Sdam.sunwoo@arm.com Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); 2478833Sdam.sunwoo@arm.com 2482810SN/A 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); 2492810SN/A 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); 2502810SN/A 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); 2512810SN/A 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); 2528833Sdam.sunwoo@arm.com 2532810SN/A 0x57: inswh({{ 2544871SN/A int bv = Rb_or_imm<2:0>; 2558833Sdam.sunwoo@arm.com Rc = bv ? (Ra.uq<15:0> >> (64 - 8 * bv)) : 0; 2568833Sdam.sunwoo@arm.com }}); 2578833Sdam.sunwoo@arm.com 0x67: inslh({{ 2582810SN/A int bv = Rb_or_imm<2:0>; 2592810SN/A Rc = bv ? (Ra.uq<31:0> >> (64 - 8 * bv)) : 0; 2604022SN/A }}); 2614022SN/A 0x77: insqh({{ 2624022SN/A int bv = Rb_or_imm<2:0>; 2632810SN/A Rc = bv ? (Ra.uq >> (64 - 8 * bv)) : 0; 2642810SN/A }}); 2652810SN/A 2662810SN/A 0x30: zap({{ 2672810SN/A uint64_t zapmask = 0; 2682810SN/A for (int i = 0; i < 8; ++i) { 2698833Sdam.sunwoo@arm.com if (Rb_or_imm<i:>) 2702810SN/A zapmask |= (mask(8) << (i * 8)); 2718833Sdam.sunwoo@arm.com } 2728833Sdam.sunwoo@arm.com Rc = Ra & ~zapmask; 2738833Sdam.sunwoo@arm.com }}); 2742810SN/A 0x31: zapnot({{ 2752810SN/A uint64_t zapmask = 0; 2762810SN/A for (int i = 0; i < 8; ++i) { 2772810SN/A if (!Rb_or_imm<i:>) 2782810SN/A zapmask |= (mask(8) << (i * 8)); 2798833Sdam.sunwoo@arm.com } 2802810SN/A Rc = Ra & ~zapmask; 2812810SN/A }}); 2828833Sdam.sunwoo@arm.com } 2838833Sdam.sunwoo@arm.com 2848833Sdam.sunwoo@arm.com 0x13: decode INTFUNC { // integer multiplies 2852810SN/A 0x00: mull({{ Rc.sl = Ra.sl * Rb_or_imm.sl; }}, IntMultOp); 2862810SN/A 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); 2872810SN/A 0x30: umulh({{ 2882810SN/A uint64_t hi, lo; 2898833Sdam.sunwoo@arm.com mul128(Ra, Rb_or_imm, hi, lo); 2902810SN/A Rc = hi; 2912810SN/A }}, IntMultOp); 2928833Sdam.sunwoo@arm.com 0x40: mullv({{ 2938833Sdam.sunwoo@arm.com // 32-bit multiply with trap on overflow 2948833Sdam.sunwoo@arm.com int64_t Rax = Ra.sl; // sign extended version of Ra.sl 2952810SN/A int64_t Rbx = Rb_or_imm.sl; 2962810SN/A int64_t tmp = Rax * Rbx; 2974022SN/A // To avoid overflow, all the upper 32 bits must match 2984022SN/A // the sign bit of the lower 32. We code this as 2994022SN/A // checking the upper 33 bits for all 0s or all 1s. 3002810SN/A uint64_t sign_bits = tmp<63:31>; 3012810SN/A if (sign_bits != 0 && sign_bits != mask(33)) 3022810SN/A fault = new IntegerOverflowFault; 3032810SN/A Rc.sl = tmp<31:0>; 3042810SN/A }}, IntMultOp); 3052810SN/A 0x60: mulqv({{ 3068833Sdam.sunwoo@arm.com // 64-bit multiply with trap on overflow 3072810SN/A uint64_t hi, lo; 3088833Sdam.sunwoo@arm.com mul128(Ra, Rb_or_imm, hi, lo); 3098833Sdam.sunwoo@arm.com // all the upper 64 bits must match the sign bit of 3108833Sdam.sunwoo@arm.com // the lower 64 3112810SN/A if (!((hi == 0 && lo<63:> == 0) || 3122810SN/A (hi == mask(64) && lo<63:> == 1))) 3132810SN/A fault = new IntegerOverflowFault; 3142810SN/A Rc = lo; 3152810SN/A }}, IntMultOp); 3168833Sdam.sunwoo@arm.com } 3172810SN/A 3182810SN/A 0x1c: decode INTFUNC { 3198833Sdam.sunwoo@arm.com 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 3208833Sdam.sunwoo@arm.com 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } 3218833Sdam.sunwoo@arm.com 0x32: ctlz({{ 3222810SN/A uint64_t count = 0; 3232810SN/A uint64_t temp = Rb; 3242810SN/A if (temp<63:32>) temp >>= 32; else count += 32; 3252810SN/A if (temp<31:16>) temp >>= 16; else count += 16; 3268833Sdam.sunwoo@arm.com if (temp<15:8>) temp >>= 8; else count += 8; 3272810SN/A if (temp<7:4>) temp >>= 4; else count += 4; 3282810SN/A if (temp<3:2>) temp >>= 2; else count += 2; 3298833Sdam.sunwoo@arm.com if (temp<1:1>) temp >>= 1; else count += 1; 3308833Sdam.sunwoo@arm.com if ((temp<0:0>) != 0x1) count += 1; 3318833Sdam.sunwoo@arm.com Rc = count; 3322810SN/A }}, IntAluOp); 3332810SN/A 3344022SN/A 0x33: cttz({{ 3354022SN/A uint64_t count = 0; 3364022SN/A uint64_t temp = Rb; 3372810SN/A if (!(temp<31:0>)) { temp >>= 32; count += 32; } 3382810SN/A if (!(temp<15:0>)) { temp >>= 16; count += 16; } 3392810SN/A if (!(temp<7:0>)) { temp >>= 8; count += 8; } 3402810SN/A if (!(temp<3:0>)) { temp >>= 4; count += 4; } 3412810SN/A if (!(temp<1:0>)) { temp >>= 2; count += 2; } 3422810SN/A if (!(temp<0:0> & ULL(0x1))) count += 1; 3432810SN/A Rc = count; 3442810SN/A }}, IntAluOp); 3458833Sdam.sunwoo@arm.com 3468833Sdam.sunwoo@arm.com format FailUnimpl { 3478833Sdam.sunwoo@arm.com 0x30: ctpop(); 3488833Sdam.sunwoo@arm.com 0x31: perr(); 3492810SN/A 0x34: unpkbw(); 3502810SN/A 0x35: unpkbl(); 3512810SN/A 0x36: pkwb(); 3522810SN/A 0x37: pklb(); 3532810SN/A 0x38: minsb8(); 3548833Sdam.sunwoo@arm.com 0x39: minsw4(); 3552810SN/A 0x3a: minub8(); 3562810SN/A 0x3b: minuw4(); 3578833Sdam.sunwoo@arm.com 0x3c: maxub8(); 3588833Sdam.sunwoo@arm.com 0x3d: maxuw4(); 3598833Sdam.sunwoo@arm.com 0x3e: maxsb8(); 3602810SN/A 0x3f: maxsw4(); 3612810SN/A } 3622810SN/A 3632810SN/A format BasicOperateWithNopCheck { 3648833Sdam.sunwoo@arm.com 0x70: decode RB { 3652810SN/A 31: ftoit({{ Rc = Fa.uq; }}, FloatCvtOp); 3662810SN/A } 3678833Sdam.sunwoo@arm.com 0x78: decode RB { 3688833Sdam.sunwoo@arm.com 31: ftois({{ Rc.sl = t_to_s(Fa.uq); }}, 3698833Sdam.sunwoo@arm.com FloatCvtOp); 3702810SN/A } 3712810SN/A } 3722810SN/A } 3732810SN/A } 3742810SN/A 3752810SN/A // Conditional branches. 3762810SN/A format CondBranch { 3772810SN/A 0x39: beq({{ cond = (Ra == 0); }}); 3782810SN/A 0x3d: bne({{ cond = (Ra != 0); }}); 3792810SN/A 0x3e: bge({{ cond = (Ra.sq >= 0); }}); 3802810SN/A 0x3f: bgt({{ cond = (Ra.sq > 0); }}); 3812810SN/A 0x3b: ble({{ cond = (Ra.sq <= 0); }}); 3822810SN/A 0x3a: blt({{ cond = (Ra.sq < 0); }}); 3832810SN/A 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); 3842810SN/A 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); 3852810SN/A 3862810SN/A 0x31: fbeq({{ cond = (Fa == 0); }}); 3872810SN/A 0x35: fbne({{ cond = (Fa != 0); }}); 3882810SN/A 0x36: fbge({{ cond = (Fa >= 0); }}); 3892810SN/A 0x37: fbgt({{ cond = (Fa > 0); }}); 3902810SN/A 0x33: fble({{ cond = (Fa <= 0); }}); 3912810SN/A 0x32: fblt({{ cond = (Fa < 0); }}); 3922810SN/A } 3932810SN/A 3942810SN/A // unconditional branches 3952810SN/A format UncondBranch { 3962810SN/A 0x30: br(); 3972810SN/A 0x34: bsr(IsCall); 3982810SN/A } 3992810SN/A 4002810SN/A // indirect branches 4012810SN/A 0x1a: decode JMPFUNC { 4022810SN/A format Jump { 4032810SN/A 0: jmp(); 4042810SN/A 1: jsr(IsCall); 4052810SN/A 2: ret(IsReturn); 4062826SN/A 3: jsr_coroutine(IsCall, IsReturn); 4074626SN/A } 4088833Sdam.sunwoo@arm.com } 4094626SN/A 4104626SN/A // Square root and integer-to-FP moves 4118833Sdam.sunwoo@arm.com 0x14: decode FP_SHORTFUNC { 4124626SN/A // Integer to FP register moves must have RB == 31 4138833Sdam.sunwoo@arm.com 0x4: decode RB { 4148833Sdam.sunwoo@arm.com 31: decode FP_FULLFUNC { 4158833Sdam.sunwoo@arm.com format BasicOperateWithNopCheck { 4164626SN/A 0x004: itofs({{ Fc.uq = s_to_t(Ra.ul); }}, FloatCvtOp); 4174626SN/A 0x024: itoft({{ Fc.uq = Ra.uq; }}, FloatCvtOp); 4184626SN/A 0x014: FailUnimpl::itoff(); // VAX-format conversion 4194626SN/A } 4204626SN/A } 4214626SN/A } 4224626SN/A 4234626SN/A // Square root instructions must have FA == 31 4248833Sdam.sunwoo@arm.com 0xb: decode FA { 4254626SN/A 31: decode FP_TYPEFUNC { 4264626SN/A format FloatingPointOperate { 4274626SN/A#if SS_COMPATIBLE_FP 4284626SN/A 0x0b: sqrts({{ 4298833Sdam.sunwoo@arm.com if (Fb < 0.0) 4308833Sdam.sunwoo@arm.com fault = new ArithmeticFault; 4318833Sdam.sunwoo@arm.com Fc = sqrt(Fb); 4324626SN/A }}, FloatSqrtOp); 4334626SN/A#else 4344626SN/A 0x0b: sqrts({{ 4354626SN/A if (Fb.sf < 0.0) 4364626SN/A fault = new ArithmeticFault; 4378833Sdam.sunwoo@arm.com Fc.sf = sqrt(Fb.sf); 4384626SN/A }}, FloatSqrtOp); 4394871SN/A#endif 4408833Sdam.sunwoo@arm.com 0x2b: sqrtt({{ 4418833Sdam.sunwoo@arm.com if (Fb < 0.0) 4428833Sdam.sunwoo@arm.com fault = new ArithmeticFault; 4434626SN/A Fc = sqrt(Fb); 4444626SN/A }}, FloatSqrtOp); 4454626SN/A } 4464626SN/A } 4478833Sdam.sunwoo@arm.com } 4484626SN/A 4494871SN/A // VAX-format sqrtf and sqrtg are not implemented 4508833Sdam.sunwoo@arm.com 0xa: FailUnimpl::sqrtfg(); 4518833Sdam.sunwoo@arm.com } 4528833Sdam.sunwoo@arm.com 4534626SN/A // IEEE floating point 4544626SN/A 0x16: decode FP_SHORTFUNC_TOP2 { 4554626SN/A // The top two bits of the short function code break this 4564626SN/A // space into four groups: binary ops, compares, reserved, and 4574626SN/A // conversions. See Table 4-12 of AHB. There are different 4584626SN/A // special cases in these different groups, so we decode on 4594626SN/A // these top two bits first just to select a decode strategy. 4608833Sdam.sunwoo@arm.com // Most of these instructions may have various trapping and 4614626SN/A // rounding mode flags set; these are decoded in the 4624626SN/A // FloatingPointDecode template used by the 4634626SN/A // FloatingPointOperate format. 4644626SN/A 4658833Sdam.sunwoo@arm.com // add/sub/mul/div: just decode on the short function code 4668833Sdam.sunwoo@arm.com // and source type. All valid trapping and rounding modes apply. 4678833Sdam.sunwoo@arm.com 0: decode FP_TRAPMODE { 4684626SN/A // check for valid trapping modes here 4694626SN/A 0,1,5,7: decode FP_TYPEFUNC { 4704626SN/A format FloatingPointOperate { 4714626SN/A#if SS_COMPATIBLE_FP 4724626SN/A 0x00: adds({{ Fc = Fa + Fb; }}); 4738833Sdam.sunwoo@arm.com 0x01: subs({{ Fc = Fa - Fb; }}); 4744626SN/A 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); 4754871SN/A 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); 4768833Sdam.sunwoo@arm.com#else 4778833Sdam.sunwoo@arm.com 0x00: adds({{ Fc.sf = Fa.sf + Fb.sf; }}); 4788833Sdam.sunwoo@arm.com 0x01: subs({{ Fc.sf = Fa.sf - Fb.sf; }}); 4794626SN/A 0x02: muls({{ Fc.sf = Fa.sf * Fb.sf; }}, FloatMultOp); 4804626SN/A 0x03: divs({{ Fc.sf = Fa.sf / Fb.sf; }}, FloatDivOp); 4814626SN/A#endif 4824626SN/A 4838833Sdam.sunwoo@arm.com 0x20: addt({{ Fc = Fa + Fb; }}); 4844626SN/A 0x21: subt({{ Fc = Fa - Fb; }}); 4854871SN/A 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); 4868833Sdam.sunwoo@arm.com 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); 4878833Sdam.sunwoo@arm.com } 4888833Sdam.sunwoo@arm.com } 4894626SN/A } 4904626SN/A 4914626SN/A // Floating-point compare instructions must have the default 4924626SN/A // rounding mode, and may use the default trapping mode or 4934626SN/A // /SU. Both trapping modes are treated the same by M5; the 4944626SN/A // only difference on the real hardware (as far a I can tell) 4954626SN/A // is that without /SU you'd get an imprecise trap if you 4968833Sdam.sunwoo@arm.com // tried to compare a NaN with something else (instead of an 4974626SN/A // "unordered" result). 4984626SN/A 1: decode FP_FULLFUNC { 4994626SN/A format BasicOperateWithNopCheck { 5004626SN/A 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, 5018833Sdam.sunwoo@arm.com FloatCmpOp); 5028833Sdam.sunwoo@arm.com 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, 5038833Sdam.sunwoo@arm.com FloatCmpOp); 5044626SN/A 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, 5054626SN/A FloatCmpOp); 5064626SN/A 0x0a4, 0x5a4: cmptun({{ // unordered 5074626SN/A Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; 5084626SN/A }}, FloatCmpOp); 5098833Sdam.sunwoo@arm.com } 5104626SN/A } 5114871SN/A 5128833Sdam.sunwoo@arm.com // The FP-to-integer and integer-to-FP conversion insts 5138833Sdam.sunwoo@arm.com // require that FA be 31. 5148833Sdam.sunwoo@arm.com 3: decode FA { 5154626SN/A 31: decode FP_TYPEFUNC { 5164626SN/A format FloatingPointOperate { 5174626SN/A 0x2f: decode FP_ROUNDMODE { 5184626SN/A format FPFixedRounding { 5198833Sdam.sunwoo@arm.com // "chopped" i.e. round toward zero 5204626SN/A 0: cvttq({{ Fc.sq = (int64_t)trunc(Fb); }}, 5214871SN/A Chopped); 5224871SN/A // round to minus infinity 5238833Sdam.sunwoo@arm.com 1: cvttq({{ Fc.sq = (int64_t)floor(Fb); }}, 5248833Sdam.sunwoo@arm.com MinusInfinity); 5258833Sdam.sunwoo@arm.com } 5264626SN/A default: cvttq({{ Fc.sq = (int64_t)nearbyint(Fb); }}); 5274626SN/A } 5284626SN/A 5294626SN/A // The cvtts opcode is overloaded to be cvtst if the trap 5304626SN/A // mode is 2 or 6 (which are not valid otherwise) 5314626SN/A 0x2c: decode FP_FULLFUNC { 5324626SN/A format BasicOperateWithNopCheck { 5338833Sdam.sunwoo@arm.com // trap on denorm version "cvtst/s" is 5344626SN/A // simulated same as cvtst 5354626SN/A 0x2ac, 0x6ac: cvtst({{ Fc = Fb.sf; }}); 5364626SN/A } 5374626SN/A default: cvtts({{ Fc.sf = Fb; }}); 5388833Sdam.sunwoo@arm.com } 5398833Sdam.sunwoo@arm.com 5408833Sdam.sunwoo@arm.com // The trapping mode for integer-to-FP conversions 5414626SN/A // must be /SUI or nothing; /U and /SU are not 5424626SN/A // allowed. The full set of rounding modes are 5434626SN/A // supported though. 5444626SN/A 0x3c: decode FP_TRAPMODE { 5454626SN/A 0,7: cvtqs({{ Fc.sf = Fb.sq; }}); 5468833Sdam.sunwoo@arm.com } 5474626SN/A 0x3e: decode FP_TRAPMODE { 5484871SN/A 0,7: cvtqt({{ Fc = Fb.sq; }}); 5494871SN/A } 5508833Sdam.sunwoo@arm.com } 5518833Sdam.sunwoo@arm.com } 5528833Sdam.sunwoo@arm.com } 5534626SN/A } 5544626SN/A 5554626SN/A // misc FP operate 5564626SN/A 0x17: decode FP_FULLFUNC { 5574626SN/A format BasicOperateWithNopCheck { 5584626SN/A 0x010: cvtlq({{ 5594626SN/A Fc.sl = (Fb.uq<63:62> << 30) | Fb.uq<58:29>; 5608833Sdam.sunwoo@arm.com }}); 5614626SN/A 0x030: cvtql({{ 5624626SN/A Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 5634626SN/A }}); 5644626SN/A 5658833Sdam.sunwoo@arm.com // We treat the precise & imprecise trapping versions of 5668833Sdam.sunwoo@arm.com // cvtql identically. 5678833Sdam.sunwoo@arm.com 0x130, 0x530: cvtqlv({{ 5684626SN/A // To avoid overflow, all the upper 32 bits must match 5694626SN/A // the sign bit of the lower 32. We code this as 5704626SN/A // checking the upper 33 bits for all 0s or all 1s. 5714626SN/A uint64_t sign_bits = Fb.uq<63:31>; 5724626SN/A if (sign_bits != 0 && sign_bits != mask(33)) 5738833Sdam.sunwoo@arm.com fault = new IntegerOverflowFault; 5744626SN/A Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29); 5754871SN/A }}); 5764871SN/A 5774871SN/A 0x020: cpys({{ // copy sign 5788833Sdam.sunwoo@arm.com Fc.uq = (Fa.uq<63:> << 63) | Fb.uq<62:0>; 5798833Sdam.sunwoo@arm.com }}); 5808833Sdam.sunwoo@arm.com 0x021: cpysn({{ // copy sign negated 5814626SN/A Fc.uq = (~Fa.uq<63:> << 63) | Fb.uq<62:0>; 5824626SN/A }}); 5834626SN/A 0x022: cpyse({{ // copy sign and exponent 5844626SN/A Fc.uq = (Fa.uq<63:52> << 52) | Fb.uq<51:0>; 5854626SN/A }}); 5864626SN/A 5874626SN/A 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); 5884626SN/A 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); 5894626SN/A 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); 5904626SN/A 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); 5914626SN/A 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); 5924626SN/A 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); 5934626SN/A 5944626SN/A 0x024: mt_fpcr({{ FPCR = Fa.uq; }}); 5954626SN/A 0x025: mf_fpcr({{ Fa.uq = FPCR; }}); 5964626SN/A } 5974626SN/A } 5984626SN/A 5994626SN/A // miscellaneous mem-format ops 6004626SN/A 0x18: decode MEMFUNC { 6014626SN/A format WarnUnimpl { 6024626SN/A 0x8000: fetch(); 6034626SN/A 0xa000: fetch_m(); 6044626SN/A 0xe800: ecb(); 6054626SN/A } 6064626SN/A 6074626SN/A format MiscPrefetch { 6084626SN/A 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, 6094626SN/A {{ xc->writeHint(EA, 64, memAccessFlags); }}, 6104626SN/A mem_flags = NO_FAULT, 6114626SN/A inst_flags = [IsMemRef, IsDataPrefetch, 6124626SN/A IsStore, MemWriteOp]); 6134626SN/A } 6144626SN/A 6154626SN/A format BasicOperate { 6164626SN/A 0xc000: rpcc({{ 6174626SN/A#if FULL_SYSTEM 6184626SN/A /* Rb is a fake dependency so here is a fun way to get 6194626SN/A * the parser to understand that. 6204626SN/A */ 6214626SN/A Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0); 6224626SN/A 6234626SN/A#else 6244626SN/A Ra = curTick; 6254626SN/A#endif 6268833Sdam.sunwoo@arm.com }}); 6278833Sdam.sunwoo@arm.com 6288833Sdam.sunwoo@arm.com // All of the barrier instructions below do nothing in 6298833Sdam.sunwoo@arm.com // their execute() methods (hence the empty code blocks). 6304626SN/A // All of their functionality is hard-coded in the 6314626SN/A // pipeline based on the flags IsSerializing, 6324626SN/A // IsMemBarrier, and IsWriteBarrier. In the current 6334626SN/A // detailed CPU model, the execute() function only gets 6344626SN/A // called at fetch, so there's no way to generate pipeline 6358833Sdam.sunwoo@arm.com // behavior at any other stage. Once we go to an 6364626SN/A // exec-in-exec CPU model we should be able to get rid of 6374626SN/A // these flags and implement this behavior via the 6388833Sdam.sunwoo@arm.com // execute() methods. 6398833Sdam.sunwoo@arm.com 6408833Sdam.sunwoo@arm.com // trapb is just a barrier on integer traps, where excb is 6414626SN/A // a barrier on integer and FP traps. "EXCB is thus a 6424626SN/A // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat 6434626SN/A // them the same though. 6444626SN/A 0x0000: trapb({{ }}, IsSerializing, No_OpClass); 6458833Sdam.sunwoo@arm.com 0x0400: excb({{ }}, IsSerializing, No_OpClass); 6464626SN/A 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); 6474626SN/A 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 6488833Sdam.sunwoo@arm.com } 6498833Sdam.sunwoo@arm.com 6508833Sdam.sunwoo@arm.com#if FULL_SYSTEM 6514626SN/A format BasicOperate { 6524626SN/A 0xe000: rc({{ 6534626SN/A Ra = xc->readIntrFlag(); 6544626SN/A xc->setIntrFlag(0); 6554626SN/A }}, IsNonSpeculative); 6564626SN/A 0xf000: rs({{ 6574626SN/A Ra = xc->readIntrFlag(); 6584626SN/A xc->setIntrFlag(1); 6594626SN/A }}, IsNonSpeculative); 6604626SN/A } 6614626SN/A#else 6624626SN/A format FailUnimpl { 6634626SN/A 0xe000: rc(); 6648833Sdam.sunwoo@arm.com 0xf000: rs(); 6658833Sdam.sunwoo@arm.com } 6668833Sdam.sunwoo@arm.com#endif 6678833Sdam.sunwoo@arm.com } 6684626SN/A 6694626SN/A#if FULL_SYSTEM 6704626SN/A 0x00: CallPal::call_pal({{ 6714626SN/A if (!palValid || 6724626SN/A (palPriv 6738833Sdam.sunwoo@arm.com && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) { 6744626SN/A // invalid pal function code, or attempt to do privileged 6754626SN/A // PAL call in non-kernel mode 6768833Sdam.sunwoo@arm.com fault = new UnimplementedOpcodeFault; 6778833Sdam.sunwoo@arm.com } 6788833Sdam.sunwoo@arm.com else { 6794626SN/A // check to see if simulator wants to do something special 6804626SN/A // on this PAL call (including maybe suppress it) 6814626SN/A bool dopal = xc->simPalCheck(palFunc); 6824626SN/A 6838833Sdam.sunwoo@arm.com if (dopal) { 6844626SN/A AlphaISA::swap_palshadow(&xc->xcBase()->regs, true); 6854626SN/A xc->setIpr(AlphaISA::IPR_EXC_ADDR, NPC); 6868833Sdam.sunwoo@arm.com NPC = xc->readIpr(AlphaISA::IPR_PAL_BASE, fault) + palOffset; 6878833Sdam.sunwoo@arm.com } 6888833Sdam.sunwoo@arm.com } 6894626SN/A }}, IsNonSpeculative); 6904626SN/A#else 6914626SN/A 0x00: decode PALFUNC { 6924626SN/A format EmulatedCallPal { 6934626SN/A 0x00: halt ({{ 6944626SN/A SimExit(curTick, "halt instruction encountered"); 6954626SN/A }}, IsNonSpeculative); 6964626SN/A 0x83: callsys({{ 6974626SN/A xc->syscall(); 6984626SN/A }}, IsNonSpeculative); 6994626SN/A // Read uniq reg into ABI return value register (r0) 7004626SN/A 0x9e: rduniq({{ R0 = Runiq; }}); 7014626SN/A // Write uniq reg with value from ABI arg register (r16) 7028833Sdam.sunwoo@arm.com 0x9f: wruniq({{ Runiq = R16; }}); 7038833Sdam.sunwoo@arm.com } 7048833Sdam.sunwoo@arm.com } 7058833Sdam.sunwoo@arm.com#endif 7064626SN/A 7074626SN/A#if FULL_SYSTEM 7084626SN/A format HwLoad { 7094626SN/A 0x1b: decode HW_LDST_QUAD { 7104626SN/A 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem.ul; }}, L); 7118833Sdam.sunwoo@arm.com 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem.uq; }}, Q); 7124626SN/A } 7134626SN/A } 7148833Sdam.sunwoo@arm.com 7158833Sdam.sunwoo@arm.com format HwStore { 7168833Sdam.sunwoo@arm.com 0x1f: decode HW_LDST_COND { 7174626SN/A 0: decode HW_LDST_QUAD { 7184626SN/A 0: hw_st({{ EA = (Rb + disp) & ~3; }}, 7198833Sdam.sunwoo@arm.com {{ Mem.ul = Ra<31:0>; }}, L); 7204626SN/A 1: hw_st({{ EA = (Rb + disp) & ~7; }}, 7214626SN/A {{ Mem.uq = Ra.uq; }}, Q); 7228833Sdam.sunwoo@arm.com } 7234626SN/A 7248833Sdam.sunwoo@arm.com 1: FailUnimpl::hw_st_cond(); 7258833Sdam.sunwoo@arm.com } 7268833Sdam.sunwoo@arm.com } 7274626SN/A 7284626SN/A format HwMoveIPR { 7294626SN/A 0x19: hw_mfpr({{ 7308833Sdam.sunwoo@arm.com // this instruction is only valid in PAL mode 7314626SN/A if (!xc->inPalMode()) { 7324626SN/A fault = new UnimplementedOpcodeFault; 7338833Sdam.sunwoo@arm.com } 7344626SN/A else { 7358833Sdam.sunwoo@arm.com Ra = xc->readIpr(ipr_index, fault); 7368833Sdam.sunwoo@arm.com } 7378833Sdam.sunwoo@arm.com }}); 7384626SN/A 0x1d: hw_mtpr({{ 7394626SN/A // this instruction is only valid in PAL mode 7404626SN/A if (!xc->inPalMode()) { 7414626SN/A fault = new UnimplementedOpcodeFault; 7424626SN/A } 7434626SN/A else { 7442810SN/A xc->setIpr(ipr_index, Ra); 7453503SN/A if (traceData) { traceData->setData(Ra); } 7463503SN/A } 7473503SN/A }}); 7483503SN/A } 7494626SN/A 7504626SN/A format BasicOperate { 7513503SN/A 0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing); 7524626SN/A 7533503SN/A // M5 special opcodes use the reserved 0x01 opcode space 7543503SN/A 0x01: decode M5FUNC { 7553503SN/A 0x00: arm({{ 7569152Satgutier@umich.edu AlphaPseudo::arm(xc->xcBase()); 7574626SN/A }}, IsNonSpeculative); 7583503SN/A 0x01: quiesce({{ 7593503SN/A AlphaPseudo::quiesce(xc->xcBase()); 7603503SN/A }}, IsNonSpeculative); 7613503SN/A 0x10: ivlb({{ 7623503SN/A AlphaPseudo::ivlb(xc->xcBase()); 763 }}, No_OpClass, IsNonSpeculative); 764 0x11: ivle({{ 765 AlphaPseudo::ivle(xc->xcBase()); 766 }}, No_OpClass, IsNonSpeculative); 767 0x20: m5exit_old({{ 768 AlphaPseudo::m5exit_old(xc->xcBase()); 769 }}, No_OpClass, IsNonSpeculative); 770 0x21: m5exit({{ 771 AlphaPseudo::m5exit(xc->xcBase(), R16); 772 }}, No_OpClass, IsNonSpeculative); 773 0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }}); 774 0x40: resetstats({{ 775 AlphaPseudo::resetstats(xc->xcBase(), R16, R17); 776 }}, IsNonSpeculative); 777 0x41: dumpstats({{ 778 AlphaPseudo::dumpstats(xc->xcBase(), R16, R17); 779 }}, IsNonSpeculative); 780 0x42: dumpresetstats({{ 781 AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17); 782 }}, IsNonSpeculative); 783 0x43: m5checkpoint({{ 784 AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17); 785 }}, IsNonSpeculative); 786 0x50: m5readfile({{ 787 R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18); 788 }}, IsNonSpeculative); 789 0x51: m5break({{ 790 AlphaPseudo::debugbreak(xc->xcBase()); 791 }}, IsNonSpeculative); 792 0x52: m5switchcpu({{ 793 AlphaPseudo::switchcpu(xc->xcBase()); 794 }}, IsNonSpeculative); 795 0x53: m5addsymbol({{ 796 AlphaPseudo::addsymbol(xc->xcBase(), R16, R17); 797 }}, IsNonSpeculative); 798 799 } 800 } 801#endif 802} 803